JP2007174841A - Uniform charge/discharge circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve energy efficiency in switching control of a uniform charge/discharge circuit, and to further improve tolerance for load variation. <P>SOLUTION: In the uniform charge/discharge circuit 1b, each FET switch TR1-TR4 is constituted of an MOSFET and switching control is performed by an oscillation circuit 2A generating a sine wave signal A through parallel resonance of its gate capacitance and an inductor connected in parallel therewith. Since energy is not consumed by switching control, energy efficiency of the uniform charge/discharge circuit 1b is improved correspondingly. Furthermore, a choke inductor Lc1-Lc4 is connected between the gate/source of each FET switch TR1-TR4. Consequently, gate potential can be followed up with no lag even if source potential of each FET switch TR1-TR4 varies due to load variation and tolerance for load variation is improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to improvement in energy efficiency of an equal storage / discharge circuit that stores a plurality of power storage elements connected in series with an equal voltage, and further to improvement in resistance to load fluctuations.

  An electric double layer capacitor is considered promising as a battery of an electric vehicle (Patent Documents 1 and 2). On the other hand, as pointed out in Patent Documents 1 and 2, a large-capacity electric double layer capacitor is difficult to store at a high voltage. For this reason, in order to use a large-capacity electric double layer capacitor at a high voltage, it is necessary to connect a plurality of electric double layer capacitors in series.

  When electricity is stored in the electric double layer capacitors connected in series, each electric double layer capacitor is charged with the same charge. On the other hand, there is a deviation in the capacitance of each electric double layer capacitor. For this reason, a deviation occurs in the stored voltage between the electric double layer capacitors connected in series. Such deviation of the stored voltage between the electric double layer capacitors is undesirable because it causes deterioration or failure of the battery (or electric double layer capacitor) (and such a problem is limited to the electric double layer capacitor). In addition, a capacitive storage element (for example, a Li ion battery, a polymer secondary battery, a large capacity Al electrolytic capacitor, etc.) is also present in series).

  For this reason, in Patent Documents 1 and 2 described above, an “energy transfer device” or a “cell energy amount adjustment device” (hereinafter referred to as this energy storage device) (hereinafter referred to as “cell energy amount adjustment device”) that transfers charges as stored energy so that the stored voltage of each capacitor (ie, storage element) becomes equal. Such devices related to energy transfer are collectively referred to as “equal storage and discharge circuit”).

  Here, the structure of the conventional equal storage / discharge circuit described in Patent Documents 1 and 2 is shown in FIG. The equal storage / discharge circuit 1e shown in FIG. 11 includes a plurality of series circuits in which the same number of windings L1 to L4 and FET switches TR1 to TR4 are connected in series. Storage elements C1 to C4 are connected in parallel to each series circuit. The windings L1 to L4 form a transformer T1 via an iron core and are magnetically coupled to each other. The regenerative winding Lr is magnetically coupled to each of the windings L1 to L4 and is connected in parallel to the power storage elements C1 to C4 via the regenerative diode Dr connected in series.

  In the FET switches TR1 to TR4, resistors Rd1 to Rd4 and clamp diodes Dc1 to Dc4 are connected in parallel between the respective gates and sources, and couple capacitors Cc1 to Cc4 are connected to the respective gates. The direction of the current flowing between the drain and source of the FET switches TR1 to TR4 changes according to the potential difference between the drain and source. The rectangular wave signal generation circuit 2C is connected to the gates of the FET switches TR1 to TR4 via the coupled capacitors Cc1 to Cc4, and outputs a rectangular wave signal for performing switching control.

  The operation of the equal storage / discharge circuit 1e will be described below with reference to FIGS. FIG. 12 is a diagram illustrating operation waveforms of the equal storage / discharge circuit 1e, in which the horizontal axis is a time axis and the vertical axis is a voltage or current axis. First, when a DC voltage is applied to the power storage elements C1 to C4 connected in series, each of the power storage elements C1 to C4 is stored with a voltage corresponding to its electrostatic capacity.

  The rectangular wave signal output from the rectangular wave signal generating circuit 2C is applied between the gates and sources of the FET switches TR1 to TR4 via the coupled capacitors Cc1 to Cc4. As described above, the clamp diodes Dc1 to Dc4 are connected between the gate and source of the FET switches TR1 to TR4. For this reason, between the gates and the sources of the FET switches TR1 to TR4, as indicated by the rectangular wave signal waveform 111 in FIG. 12, the source potential is reduced by the forward bias voltage of the clamp diodes Dc1 to Dc4. A rectangular wave signal is applied at a potential equal to or greater than (potential).

  Further, as shown in FIG. 11, each of the FET switches TR1 to TR4 (because it is an n-channel FET) has a threshold level at a potential higher than the source potential. Therefore, each FET switch TR1 to TR4 is turned on when the potential of the rectangular wave signal applied to its gate exceeds the threshold level, as shown by the rectangular wave signal waveform 111 in FIG. Off when below the value level.

  When each of the FET switches TR1 to TR4 is turned on, a voltage is applied to each of the windings L1 to L4 by a voltage across each of the storage elements C1 to C4, and at the same time each of the windings L1 is excited by the transformer T1. A voltage is induced in ~ L4 according to the ratio of the number of turns.

  Further, as described above, the windings L1 to L4 are wound in the same number. Therefore, the same voltage (a voltage obtained by averaging the voltages across the power storage elements C1 to C4) is generated in each of the windings L1 to L4 (assuming that there is no magnetic leakage). The drain voltages of the FET switches TR1 to TR4 are the drain voltage waveform 112 of the FET switch TR1, the drain voltage waveform 113 of the FET switch TR2, the drain voltage waveform 114 of the FET switch TR3, and the drain voltage waveform 115 of the FET switch TR4 in FIG. Fluctuate as shown). At this time, if there is a potential difference between the voltage generated in the windings L1 to L4 and the voltage across the storage elements C1 to C4, energy is transferred.

  For example, as shown in the discharge waveform 116 of FIG. 12, the storage element (for example, C1) with the higher storage voltage is discharged, and the energy (charge) discharged thereby (via the FET switch TR2) is changed to FIG. As shown in the storage waveform 118, the storage element having a lower voltage (for example, C2) stores power.

  By such energy (charge) transfer, voltage averaging processing between the power storage elements C1 to C4 is performed. In addition, as shown in the average current waveform 117 of FIG. 12, a current (average) of the discharge current and the storage current of each of the storage elements C1 to C4 flows, and magnetic energy is accumulated in the transformer T1, When the FET switches TR1 to TR4 are turned off, voltages are generated in the respective windings L1 to L4 in the direction opposite to that when the FET switches TR1 to TR4 are turned on. As described above, the voltage generated in the reverse direction of each of the windings L1 to L4 generates a regenerative voltage in the regenerative winding Lr via the transformer T1, and as shown in the regenerative current waveform 119 in FIG. 12, the regenerative diode Dr. The energy is recovered in each of the power storage elements C1 to C4 via. As described above, the equal storage / discharge circuit 1e shown in FIG. 11 transfers energy and averages the storage voltage between the storage elements by switching control of the FET switches TR1 to TR4.

  The equal storage and discharge circuits described in Patent Documents 1 and 2 are averaged because the transfer of stored energy for averaging the voltage between the storage elements is limited to the period in which the switches are on. Processing takes a long time. For such a problem, another series circuit in which a winding and a switch are connected in series is further connected in parallel to a power storage element, and the two series circuits are alternately turned on, thereby quickly storing power. A configuration for performing energy averaging processing has been proposed (Patent Document 3).

  Since the “energy transfer device” described in Patent Document 3 has two windings for one power storage element, the configuration becomes larger as the number of windings is larger. In addition, the “energy transfer device” described in Patent Document 3 uses only one of the windings connected to each power storage element whose switch is turned on to transfer the stored energy. Therefore, the “energy transfer device” described in Patent Document 3 can save space by sharing windings between adjacent power storage elements (Patent Document 4).

JP 2000-308271 A JP 2002-159145 A JP 2001-177987 A JP 2004-119455 A

  In the equal storage / discharge circuits described in Patent Documents 1 to 4 as described above, switching control is performed by a rectangular wave signal generated by the rectangular wave signal generation circuit. When the FET switch as described above is configured by, for example, a MOSFET, when the rectangular wave signal is “high level”, electric charge is stored (charged) in the gate capacitance, and when the rectangular wave signal is “low level”, the gate capacitance is charged. The charged charge is forcibly discharged (discharged). For this reason, the configurations described in Patent Documents 1 to 4 consume energy by the switching control.

Here, the gate-source capacitance of the FET switch is Cgs [F], the amplitude of the rectangular wave signal is Vgs [V], the power supply voltage of the rectangular wave signal generating circuit is Vcc [V], and the frequency of the rectangular wave signal to be switched is f When [Hz] and the number of FET switches are n, the power consumption Wg [W] accompanying switching is given by the following equation (1).
Wg = Cgs × Vgs × Vcc × f × n (1)

  As an example, when Vcc = 15 V, Cgs = 2 nF (in the case of an n-channel MOSFET), Vgs = 14 V (half of 7 V when using a clamp diode), f = 100 kHz, and n = 20, the power consumption Wg is 0 .84 W (0.42 W, half when using a clamp diode). Such power consumption associated with the switching control is not preferable because it reduces the energy efficiency of a device (for example, an electric vehicle or a hybrid vehicle) on which a power storage element is mounted.

  Furthermore, the equal storage / discharge circuits described in Patent Documents 1 to 4 as described above have room for improvement in resistance to sudden load fluctuations. Hereinafter, this will be described with reference to FIG. As described above, as shown in the rectangular wave signal waveform 121 (rectangular wave signal waveform 122 when no clamp diode is used) in FIG. The switch turns on and off alternately.

  Here, if there is a sudden load fluctuation with respect to the power storage elements connected in series, the power storage voltage of each power storage element rapidly decreases mainly due to the internal resistance of the power storage elements (that is, the terminal voltage of each power storage element). Suddenly drops pressure). As a result, each FET switch (because the source is connected to the storage element) has its source potential rapidly lowered as shown in FIG. On the other hand, the gate potential of each FET switch decreases as the source potential decreases, but the time constant between the resistor and the coupled capacitor (connected between the gate and source) with respect to the decrease in source potential. Only follow up is delayed.

  As a result, each FET switch continues to be applied with a voltage equal to or higher than the threshold level to the gate until the gate potential is lowered, and the abnormal ON period 123 in FIG. 13 (the abnormal ON period 124 when a clamp diode is not used). ), The section that is originally off is turned on and continues to be on. Thus, if the FET switch continues to be turned on, the current continues to flow from the storage element to each FET switch, causing failure or deterioration of each FET switch. For this reason, some countermeasure against such load fluctuation is desired.

  The objective of this invention is improving the energy efficiency in the switching control in a uniform storage / discharge circuit, and also improving the tolerance with respect to a load fluctuation.

  The present invention comprises a plurality of series circuits each having a winding, a FET switch connected in series with the windings, and a plurality of power storage elements connected in parallel to each of the plurality of series circuits. Are equivalently accumulating and discharging circuits in which FET switches are controlled to be synchronized with each other, and the FET switches are controlled to be switched by an oscillation circuit that generates a sine wave signal.

  Further, according to the present invention, the FET switch is configured by a MOSFET, and the oscillation circuit has a sine wave signal by parallel resonance of a capacitor including a gate capacitor of the FET switch and an inductor connected in parallel to the capacitor. It is desirable to generate

  In addition, according to the present invention, all or part of the FET switch has a choke inductor connected between its gate and source, a capacitor connected to the gate, and a sine wave generated by the oscillation circuit via the capacitor. It is desirable that a signal is input.

  ADVANTAGE OF THE INVENTION According to this invention, the energy efficiency in the switching control in a uniform storage / discharge circuit can be improved, and also the tolerance with respect to load fluctuation | variation can be improved.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In the equal storage / discharge circuit described in this embodiment, the storage elements C1 to C4 are connected in series. As will be described later, the FET switch of the equal storage / discharge circuit according to the present embodiment is configured by a MOSFET. In addition, the same code | symbol is attached | subjected to the structure similar to the conventional equal storage / discharge circuit, and description is abbreviate | omitted.

“First Embodiment”
Hereinafter, the equal storage / discharge circuit according to the first embodiment will be described. The equal storage / discharge circuit 1a shown in FIG. 1 further includes a sine wave signal oscillation circuit 2A, and switching control of each of the FET switches TR1 to TR4 is performed by the sine wave signal output from the sine wave signal oscillation circuit 2A. I do. The equal storage / discharge circuit 1a shown in FIG. 1 does not include a clamp diode because the FET switches TR1 to TR4 are driven by sine wave signals (improves energy efficiency).

  Next, the configuration and operation of the sine wave signal oscillation circuit 2A in the equal storage / discharge circuit 1a shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is a diagram illustrating a configuration of a sine wave signal oscillation circuit 2A that generates a sine wave signal for performing switching control of the FET switch. FIG. 3 is a diagram showing operation waveforms of the equal storage / discharge circuit 1a, in which the horizontal axis is a time axis and the vertical axis is a voltage or current axis.

  As shown in FIG. 2, the sine wave signal oscillation circuit 2A includes transistors 21 and 22 which are pnp bipolar transistors, capacitors 23a, 23c, 24a and 24c, resistors 23b, 24b, 25 and 27, a smoothing capacitor 29, and an inductor La. , Lb and (external) capacitor Ca2.

  The base of the transistor 21 is connected to capacitors 24a and 24b and a resistor 24c. The emitter of the transistor 21 is connected to a resistor 27 (which becomes a current source). The collector of the transistor 21 is connected to the base of the transistor 22 through a capacitor 23a and a resistor 23b. The collector of the transistor 23a is connected to the gates of the FET switches TR1 to TR4 (through the couple capacitors Cc1 to Cc4).

  Similarly, the base of the transistor 22 is connected to the capacitors 23a and 23b and the resistor 23c, the emitter thereof is connected to the resistor 27, and the collector thereof is connected to the base of the transistor 21 via the capacitor 24a and the resistor 24b. .

  The inductor La (Lb) has one terminal connected to the collector of the transistor 21 (22) and the other terminal via the resistor 25. The FET switch having the lowest source potential among the FET switches TR1 to TR4 described above. To the source (point e in FIG. 1).

  As described above, each FET switch is composed of a MOSFET. For this reason, it can be considered that the gate capacitance (the combined capacitance) Ca1 of the FET switches TR1 to TR4 is equivalently connected in parallel to the inductor La (via the coupled capacitors Cc1 to Cc4). A capacitor Ca2 is connected in parallel to the inductor Lb (note that the value of the capacitor Ca2 is preferably set to an appropriate value in consideration of the value of the gate capacitor Ca1 and the like).

  The resistor 25 is connected (to generate a potential difference) between the connection point of the inductors La and Lb and the connection point of the gate capacitors Ca1 and Ca2. The sine wave signal oscillation circuit 2A is provided with a smoothing capacitor 29 for suppressing fluctuations in the power supply voltage Vcc (potential difference from Vdd) due to generation of a sine wave signal, which will be described later.

  Next, the operation of the sine wave signal oscillation circuit 2A shown in FIG. 2 will be described using the operation waveforms of FIG. When the capacitor Ca2 discharges the electric charge, the electric charge is stored in the inductor Lb. The electric charge discharged from the capacitor 24a is also stored in the inductor Lb. As charge moves from the capacitor 24 a to the inductor Lb, a current flows through the base of the transistor 21. The transistor 21 through which the base current flows outputs a collector current corresponding to the base current.

  Due to the collector current output from the transistor 21 (and the discharge current from the inductor La), charges are stored in the gate capacitance Ca1. In the FET switches TR1 to TR4, charges are stored in the gate capacitance Ca1, so that the potential of each gate rises and becomes high level. As a result, the FET switches TR1 to TR4, which are n-channel MOSFETs, are turned on. In parallel with this, the capacitor 23a is charged by the collector current output from the transistor 21.

  The gate capacitance Ca1 stored by the transistor 21 starts to discharge as the amount of discharge from the capacitance Ca2 decreases. The electric charge discharged from the capacitor Ca1 is stored in the inductor La. In parallel with this, the charge stored in the capacitor 23a is discharged and stored in the inductor La.

  As the electric charge is discharged from the capacitor 23a (the electric charge is stored in the inductor La), a current flows through the base of the transistor 22. The transistor 22 through which the base current flows outputs a collector current corresponding to the base current. Charge is stored in the capacitor Ca2 by the collector current output from the transistor 22 (and the discharge current from the inductor La).

  Further, as described above, since the FET switches TR1 to TR4 are discharged from the gate capacitance Ca1, the potential of each gate is lowered to a low level. Therefore, the FET switches TR1 to TR4 that are n-channel MOSFETs are turned off. In parallel with this, the capacitor 24 a is charged by the collector current output from the transistor 22.

  The sine wave signal oscillation circuit 2A generates (oscillates) a sine wave signal by repeating the above-described operation (that is, the positive phase component of the sine wave signal is output from the transistor 21 and the sine wave is output from the transistor 22). The anti-phase component of the signal is output). Further, as shown by the sine wave waveform 31 in FIG. 3, a voltage that swings around the source potential is applied between the gates and sources of the FET switches TR1 to TR4 (because there is no clamp diode), and the FET switches TR1 to TR1. 4 is switching-controlled.

Thus, since the sine wave signal oscillation circuit 2A stores and discharges electric charge between the inductor La (Lb) and the gate capacitance Ca1 (capacitance Ca2), the power consumption related to the switching control hardly occurs. For example, the value of the gate capacitance Ca1 Cgs [F], the sine wave amplitude ^{Vgs P-P} [V], the switching frequency f [Hz], the Q value of the resonance circuit Q, when the number n of the FET switch, FIG. When the sine wave signal oscillation circuit 2A as shown in FIG. 2 is used, the power Wg consumed by the switching control is given by the following equation (2).
Wg = (1/8) × Cgs × (Vgs P-P) 2 × f × n / Q ··· (2)

As an example, (the case of n-channel ^{MOSFET) Cgs = 2nF, Vgs P} -P = 28V, f = 100kHz, When Q = 100, n = 20, the Wgs = 0.42mW. Therefore, the equal storage / discharge circuit 1a shown in FIG. 1 hardly generates power consumption associated with the switching control as compared with the conventional switching control using the rectangular wave signal.

  In addition, with such switching control, a voltage is generated in each of the windings L1 to L4, and there is a potential difference between the voltage generated in the windings L1 to L4 and the voltage across the storage elements C1 to C4. Energy is transferred (at this time, the voltages generated in the windings L1 to L4 cause the drain voltages of the FET switches TR1 to TR4 to be the drain voltage waveform 32 of the FET switch TR1 and the drain of the FET switch TR2 in FIG. The voltage waveform 33, the drain voltage waveform 34 of the FET switch TR3, and the drain voltage waveform 35 of the FET switch TR4 vary).

  For example, as shown in the discharge waveform 36 of FIG. 3, the storage element (for example, C1) with the higher storage voltage is discharged, and the energy (charge) discharged thereby (via the FET switch TR2) is changed to FIG. As shown in the storage waveform 38, the storage element having the lower voltage (for example, C2) stores power. Further, at this time, as shown in the average current waveform 37 of FIG. 12, a current (average) obtained by averaging the discharge current and the storage current of each of the storage elements C1 to C4 flows through each of the storage elements C1 to C4. .

  Further, when each FET switch TR1 to TR4 is turned off, a voltage is generated in each winding L1 to L4 in a direction opposite to that when each FET switch TR1 to TR4 is turned on. As described above, the voltage generated in the reverse direction of each of the windings L1 to L4 generates a regenerative voltage in the regenerative winding Lr via the transformer T1, and the regenerative diode Dr as shown in the regenerative current waveform 39 in FIG. The energy is recovered in each of the power storage elements C1 to C4 via. By such energy (charge) transfer, voltage averaging processing between the power storage elements C1 to C4 is performed.

  As described above, in the equal storage / discharge circuit according to the present embodiment, each FET switch is switching-controlled by the oscillation circuit that generates (oscillates) the sine wave signal. Furthermore, the oscillation circuit according to the present embodiment generates a sine wave signal by parallel resonance of a capacitance including the gate capacitance of the FET switch and an inductor connected in parallel with the capacitance. Thereby, in the equal storage / discharge circuit according to the present embodiment, since the electric charge stored in the gate capacitance is stored / discharged with the inductor (according to its parallel resonance), the power consumption accompanying the switching control hardly occurs. . Therefore, the energy storage efficiency of the equal storage / discharge circuit according to the present embodiment is improved by the fact that the power consumption accompanying the switching control hardly occurs.

“Second Embodiment”
Hereinafter, the equal storage / discharge circuit according to the second embodiment will be described. In the equal storage / discharge circuit 1b shown in FIG. 4, choke inductors Lc1 to Lc4 are newly connected between the gates and sources of the FET switches TR1 to TR4 in place of the resistors Rd1 to Rd4.

  As described above, the inductor La of the sine wave signal oscillation circuit 2A is connected in parallel with the gate capacitance Ca1 of each of the FET switches TR1 to TR4. That is, the choke inductors Lc1 to Lc4 are connected in parallel with the inductor La (through the coupled capacitors Cc1 to Cc4). Therefore, the choke inductors Lc1 to Lc4 contribute to the oscillation by the sine wave signal oscillation circuit 2A together with the inductor La, and apply the sine wave signal thus oscillated between the gates and the sources of the FET switches TR1 to TR4. .

  The equal storage / discharge circuit 1b shown in FIG. 4 transfers energy of each of the power storage elements C1 to C4 by switching control by the sine wave signal oscillation circuit 2A described above. Detailed description of the switching control will be omitted. Further, the equal storage / discharge circuit 1b shown in FIG. 4 is normally turned on without the FET switches TR1 to TR4 being kept on even if there is a sudden load fluctuation with respect to the power storage elements C1 to C4 connected in series. Off switching control is performed. Hereinafter, this will be described with reference to FIG.

  As described above, in the steady storage / discharge circuit 1b, in the steady state, the FET switches TR1 to TR4 are subjected to switching control by the sine wave signal oscillation circuit 2A, and energy is transferred to the respective storage elements C1 to C4.

  Here, when there is a sudden load fluctuation with respect to the power storage elements connected in series, the power storage voltage of each power storage element C1 to C4 rapidly decreases (that is, the terminal voltage of each power storage element rapidly decreases). . Thereby, as shown in FIG. 5, the source potential of each FET switch rapidly decreases (because the source is connected to the storage elements C1 to C4). On the other hand, the gate potential of each FET switch can follow the source potential without delay because the choke coils Lc1 to Lc4 have almost no resistance component. Therefore, even charge / discharge circuit 1b shown in FIG. 4 can follow the gate potential without delay even if the source potential fluctuates rapidly, and the resistance to load fluctuation is improved.

  As shown in FIG. 6, the choke coils Lc1 to L4 may be connected between some of the gates and sources of the FET switches TR1 to TR4. Thereby, the abnormal ON period as described above can be shortened. Such a combination of choke coil and resistor is desirably designed as appropriate in accordance with cost, performance, and the like. Furthermore, if only the resistance against load fluctuations is improved, a choke inductor is connected between the gate and source of the FET switch and the LC oscillation circuit (FET switch) can be used instead of the configuration that oscillates using the gate capacitance of the FET switch. The sine wave signal oscillated (without using the gate capacitance) may be input to the FET switch.

  As described above, in the equal storage / discharge circuit according to the present embodiment, each FET switch is switching-controlled by the oscillation circuit that generates (oscillates) the sine wave signal. Further, all or part of the FET switch according to the present embodiment has a choke inductor connected between its gate and source, a capacitor connected to the gate, and a sine wave generated by the oscillation circuit via the capacitor. A signal is input. As a result, the equal storage / discharge circuit according to the present embodiment causes the gate potential to follow up even if the source potential of each FET switch suddenly drops due to a sudden load fluctuation in the storage circuit, causing the FET switch to fail or fail. Etc., and resistance to load fluctuations can be improved.

“Third Embodiment”
Hereinafter, the equal storage / discharge circuit according to the third embodiment will be described. The equal storage / discharge circuit 1c shown in FIG. 7 is configured to transfer energy by push-pull drive between first and second series circuits described later. Thereby, the equal storage / discharge circuit 1c shown in FIG. 7 can perform the storage energy averaging process earlier.

  Next, the configuration of the equal storage / discharge circuit 1c shown in FIG. 7 will be described. In FIG. 7, a series circuit (first series circuit (1)) is configured by the winding L1 and the FET switch TRA-b1 connected in series to the winding L1. Further, the series circuit (first series circuit (1)) is connected in parallel with the power storage element C1.

  Similarly, a series circuit (first series circuit (2)) is configured by the winding L2 and the FET switch TRA-a2 connected in series to the winding L2. Further, the series circuit (first series circuit (2)) is connected in parallel with the power storage element C2.

  Furthermore, a series circuit (second series circuit (1)) is configured by the winding L2 and the FET switch TRB-a1 connected in series to the winding L2. This series circuit (second series circuit (1)) is connected in parallel with the storage element C1.

  Similarly, a series circuit (second series circuit (2)) is configured by the winding L1 and the FET switch TRB-b2 connected in series to the winding L1. This series circuit (second series circuit (2)) is connected in parallel with the storage element C2.

  These series circuits (first series circuit (1) and (2), second series circuit (1) and (2)) are switched by a sine wave signal generated (oscillated) by the sine wave signal oscillation circuit 2B. Be controlled. FIG. 8 shows the configuration of the sine wave signal oscillation circuit 2B. The sine wave signal oscillating circuit 2B shown in FIG. 8 has the same configuration as the sine wave signal oscillating circuit 2A described above (except that the collectors of the transistors 21 and 22 are connected to different collectors) and operates similarly. do.

  That is, in the sine wave signal oscillation circuit 2B shown in FIG. 8, the collector of the transistor 21 is connected to the gates of the FET switches TRB-a1, TRA-a2, TRB-a3, TRA-a4, and the collector of the transistor 22 is connected to the FET. The switches TRA-b1, TRB-b2, TRA-b3, and TRB-b4 are connected to the gates.

  Therefore, it can be considered that the gate capacitance (the combined capacitance) Ca of the FET switches TRB-a1, TRA-a2, TRB-a3, and TRA-a4 is equivalently connected to the inductor La in parallel. Similarly, it can be considered that the inductor Lb is equivalently connected in parallel with the gate capacitance (the resultant capacitance) Cb of the FET switches TRA-b1, TRB-b2, TRA-b3, and TRB-b4. .

  Next, the operation of the equal storage / discharge circuit 1c will be described using the operation waveforms of FIG. In FIG. 9, a sine wave waveform 71 represents the waveform of the positive phase component of the sine wave signal generated by the sine wave signal oscillation circuit, and the sine wave waveform 72 represents the waveform of the negative phase component of the sine wave signal.

  Charge is stored in the gate capacitor Ca by the collector current output from the transistor 21 (and the discharge current from the inductor La). The FET switches TRB-a1, TRA-a2, TRB-a3, and TRA-a4 have their gate potentials raised as shown by the sine wave waveform 71 of FIG. And it becomes high level. As a result, the FET switch TRA-a2 (and -a4), which is an n-channel MOSFET, is turned on. Further, the FET switch TRB-a1 (and -a3) which is a p-channel MOSFET is turned off.

  Further, as described above, when the gate capacitance Ca is stored, the gate capacitance Cb is discharged. For this reason, the FET switches TRA-b1, TRB-b2, TRA-b3, and TRB-b4 have their gate potentials lowered to a low level as shown by the sine wave waveform 72 of FIG. Therefore, the FET switch TRA-b1 (and -b3) which is a p-channel MOSFET is turned on. Further, the FET switch TRB-b2 (and -b4) which is an n-channel MOSFET is turned off.

  Next, in the sine wave signal oscillation circuit 2B, the gate capacitance Ca starts to discharge as the discharge amount from the gate capacitance Cb decreases. The FET switches TRB-a1, TRA-a2, TRB-a3, and TRA-a4 have their gate voltages lowered as shown by the sine wave waveform 71 of FIG. And it becomes low level. As a result, the FET switch TRA-a2 (and -a4), which is an n-channel MOSFET, is turned off. Further, the FET switch TRB-a1 (and -a3) which is a p-channel MOSFET is turned on.

  Further, when the gate capacitance Ca is discharged, the gate capacitance Cb is charged. For this reason, the gate voltages of the FET switches TRA-b1, TRB-b2, TRA-b3, and TRB-b4 rise to high level as indicated by the sine wave waveform 72 of FIG. Therefore, the FET switch TRA-b1 (and -b3) which is a p-channel MOSFET is turned off. Further, the FET switch TRB-b2 (and -b4) which is an n-channel MOSFET is turned on.

  When the sine wave signal oscillation circuit 2B outputs a sine wave signal (the normal phase and the reverse phase thereof), the FET switches TRA and TRB are alternately switched and energy is transferred between the storage elements C1 to C4 ( Further, due to the voltages generated in the windings L1 to L4, the drain voltages of the FET switches TR1 to TR4 are changed to the drain voltage waveform 73 of the FET switch TRA-b1 (and -b3) in FIG. 9, the FET switch TRB-a1 ( And -a3), a drain voltage waveform 74 of the FET switch TRA-b1 (and -b3), and a drain voltage waveform 76 of the FET switch TRB-b2 (and -b4).

  For example, as shown in the discharge waveform 77 of FIG. 9, the storage element (for example, C1) with the higher storage voltage discharges, and the energy (charge) discharged thereby is changed to the FET switch TRA-a2 or TRB-a2. As shown in the storage waveform 79 in FIG. 9, the storage element having the lower voltage (for example, C2) stores power. Further, at this time, as shown in the average current waveform 78 of FIG. 9, a current (average) obtained by averaging the discharge current and the storage current of each of the storage elements C1 to C4 flows through each of the storage elements C1 to C4. .

  Therefore, the FET switch TRA (-b1, -a2, -b3, -a4) and the FET switch TRB (-a1, -b2, -a3, -b4) are alternately turned on / off (push-pull drive). 1), the equal storage / discharge circuit 1 shown in FIG. 1 can perform the voltage averaging process (in a short time) by transferring energy between the power storage elements C1 and C2.

  Further, instead of the above-described configuration, as shown in FIG. 10, the equal storage / discharge circuit 1d may supply a gate voltage to each FET switch via the transformer T2. That is, the equal storage / discharge circuit 1d shown in FIG. 10 newly includes a transformer T2. The transformer T2 has a primary winding connected to the output side of the sine wave signal oscillation circuit 2B, and a secondary winding connected between the gate and source of each FET switch. Push-pull driving as described above can also be performed by such switching control via the transformer T2. The choke coils LA1 to LA4 and LB1 to LB4 may be connected between a part of the gates and sources of the FET switch, as in the second embodiment described above. Thereby, the abnormal ON period as described above can be shortened.

  As described above, in the equal storage / discharge circuit according to the present embodiment, the series circuit is constituted by the first and second series circuits each having the winding and the FET switch, and the winding is the first series. The windings of the circuit are magnetically coupled to each other, and the windings of the second series circuit are magnetically coupled to each other. By alternately turning on the first and second series circuits, between the storage elements C1 to C4 The energy can be transferred more efficiently. Note that the threshold voltage setting for push-pull driving the FET switch may be designed according to the specifications as appropriate.

  The oscillation circuit shown in this embodiment is an embodiment for carrying out the present invention, and it goes without saying that a similar oscillation circuit can be realized by other configurations.

It is a circuit diagram which shows the structure of the equal storage / discharge circuit which concerns on 1st Embodiment. It is a circuit diagram which shows the structure of the sine wave signal oscillation circuit which concerns on 1st Embodiment. It is a circuit diagram which shows the operation | movement waveform of the equal storage / discharge circuit which concerns on 1st Embodiment. It is a circuit diagram which shows the structure of the equal storage / discharge circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the operation | movement waveform of the equal storage / discharge circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the other structure of the equal storage-and-discharge circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the equal storage / discharge circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows the structure of the sine wave signal oscillation circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows the operation | movement waveform of the equal storage / discharge circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows the other structure of the equal storage-and-discharge circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows the structure of the conventional equal storage / discharge circuit. It is a circuit diagram which shows the operation | movement waveform of the conventional equal storage / discharge circuit. It is a circuit diagram which shows the operation | movement waveform of the conventional equal storage / discharge circuit.

Explanation of symbols

  1a, 1b, 1c, 1e Equal storage / discharge circuit, 2A, 2B sine wave signal oscillation circuit, 2C rectangular wave signal generation circuit, 21, 22 transistor, 23a, 24a capacitor, C1-C4 storage element, Ca1, Ca, Cb gate Capacitance, Ca2 external capacitance, L1-L4 winding, La, Lb inductor, T1 transformer, TR1-TR4 FET switch.

Claims (3)

A plurality of series circuits having windings and FET switches connected in series with the windings;
A plurality of power storage elements connected in parallel to each of a plurality of series circuits;
With
An equal storage and discharge circuit in which the windings are magnetically coupled to each other, and the FET switches are controlled to be synchronized with each other,
The FET switch is controlled by an oscillation circuit that generates a sine wave signal. The equal storage and discharge circuit according to claim 1,
The FET switch is composed of a MOSFET,
The oscillation circuit generates a sine wave signal by parallel resonance of a capacitor including a gate capacitor of the FET switch and an inductor connected in parallel to the capacitor. The equal storage and discharge circuit according to claim 1 or 2,
A choke inductor is connected between the gate and source of all or part of the FET switch, a capacitor is connected to the gate, and a sine wave signal generated by the oscillation circuit is input via the capacitor. An equal storage and discharge circuit.

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