JP2007174492A - Memory circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent malfunctions from occurring in a memory circuit, even due to the noise propagated to a power supply line or a ground line, at switching on the memory circuit, or while operating the memory circuit, and to prevent content from being rewritten unexpectedly, even when a memory circuit is used as a control latch circuit for write and erasure of a memory device. <P>SOLUTION: A storage circuit constituting a memory circuit of the present invention includes a first latch circuit 5, a second latch circuit 6 for inputting inverse data thereof, and an AND circuit 13 for inputting inverted output signals of the first latch circuit 5 and the second latch circuit 6. Normally, data held are mutually inverted in the first and second latch circuits, so that there is no change in an output of the AND circuit 13; but when data to be held by the first and second latch circuits become identical due to noise or the like, data will not be outputted from the AND circuit 13. Accordingly, malfunctions can be prevented, regardless of whether the memory circuit is being switched on or is in operation. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory circuit having a memory circuit for holding data and a predetermined circuit output, and in particular, has a serial data terminal for bidirectional communication, and functions of external data writing and external data reading. Relates to the circuit.

  A memory circuit having a serial data terminal designates a write operation and an erase operation by serially inputting a control command from the outside and decoding the captured serial data. This decoded output needs to hold the presence or absence of the operation designated by the memory circuit until the operation is completed.

In a conventionally known memory circuit, initial information stored in the memory circuit may be changed due to noise superimposed on the power supply line and the ground line when the power is turned on.
As noise generated when the power is turned on, spike-like noise caused by an inrush current generated in a circuit energized when the power is turned on, or noise generated by the power circuit itself is known. The noise generated by the power supply circuit itself is due to feedback being applied to the power supply circuit so as to quickly stabilize the voltage to a desired potential when the system is turned on. That is, for example, when the power source is raised from 0 V to +5 V, the control is performed so that the current is suddenly supplied and the voltage is decreased when it exceeds +5 V. This is repeated until the power supply potential is stabilized, and this fluctuation becomes power supply noise.

This will be described using a timing chart. FIG. 3 is a timing chart showing a state before and after power-on of a memory circuit known in the art.
VDD is a high-level power supply potential, and VSS is a low-level potential. For example, VDD is + 5V and VSS is 0V (ground potential). DATA is a data signal, CK is a clock signal, and OUT is an output signal. The memory circuit of this timing chart is a latch circuit that latches the data signal at the rising edge of the clock signal CK.
The power-on timing is often synchronized with the power supply of the system that drives the storage circuit, and noise is superimposed on the power supply line and the ground line when the system power is turned on. 22a indicates noise generated in the VDD potential as the power supply potential, and 22b indicates noise generated in the VSS potential as the ground potential.
A signal which is initially at a low level and becomes a high level at a certain timing is input to the memory circuit as the data signal DATA.

The memory circuit has an internal logic state that is not determined immediately after the power is turned on. When the power is turned on, noises 22a and 22b are generated in the power supply line and the ground line until the power supply line is stabilized on the VDD potential side. This noise fixes the internal logic state of the memory circuit, and outputs a high-level signal as the output signal OUT at the timing T2.
This erroneous output signal continues to be output for the time indicated by the period 21 until the timing T3 when the rising edge of the regular clock signal CK is input.

  Such a malfunction is caused by the fact that a memory circuit whose internal logic state is not fixed immediately after power-on is fixed to an incorrect logic state due to noise on the power supply line or ground line. This can be solved by providing an on-reset circuit and resetting the memory circuit immediately after power-on.

  In some cases, a reset terminal is provided in the memory circuit itself, and when data is actually read or read, the data stored in the memory circuit is forcibly changed to initial information by resetting in advance. In this way, there is no actual harm even if the initial state of the memory circuit is rewritten unintentionally. As described above, means for preventing malfunction of the memory circuit by resetting is widely known (see, for example, Patent Document 1).

[Description of Operation of Conventional Technology: FIG. 4]
FIG. 4 is a diagram showing the memory circuit of the prior art disclosed in Patent Document 1. In FIG. The prior art shown in FIG. 4 describes an example of resetting a memory circuit, and the contents are rewritten so as to facilitate explanation. 1 is a data signal line, 2 is a clock signal line, 3 is an output signal line, 4 is a reset signal line, and 5 is a latch circuit constituting a memory circuit. The latch circuit 5 shows an example using a flip-flop circuit, and is indicated by a symbol FF. The data signal DATA is input to the data signal line 1, the clock signal CK is input to the clock signal line 2, the reset signal RESET is input to the reset signal line 4, and the output signal OUT is output to the output signal line 3. Is done.
The data signal DATA is latched by the latch circuit 5 at the rising edge of the clock signal CK, and the output signal OUT is output from the output signal line 3.

  In the prior art disclosed in Patent Document 1, the reset signal RESET is input to the latch circuit 5 via the reset signal line 4 so that the content is rewritten to initial information when the operation of the latch circuit 5 is started. For example, the latch circuit 5 whose internal logic state is not fixed immediately after power-on is brought to a low level by the reset signal RESET. Thereby, it is possible to prevent unintended rewriting of information caused by noise or the like.

Japanese Patent Laid-Open No. 2002-50200 (FIG. 1)

Conventionally known technology is that unintentional information generated by noise etc. because the contents are rewritten to initial information at the start of operation of the memory circuit by inputting a reset signal to the memory circuit immediately after power-on. Can be prevented from being rewritten.
However, noise does not occur only when the power is turned on (when the operation of the memory circuit starts). There is known a power supply voltage fluctuation noise caused by a power supply potential fluctuating with the operation of another circuit connected to the power supply line. For example, the power supply potential of the power supply line or the ground line may fluctuate due to the operation of a liquid crystal display device or a motor drive circuit that passes a large current. These are so-called fluctuations of the power supply system wiring, and such power supply system noise is called power supply voltage fluctuation noise.

  Such power supply voltage fluctuation noise due to circuit operation is generated in connection with the operation of a circuit or the like that creates a factor that fluctuates the potential of the power supply line or the ground line. It doesn't matter. Therefore, even after the memory circuit is reset, the power supply voltage fluctuation noise is applied to the memory circuit by propagating through the power line, and the memory circuit may rewrite data unintentionally. .

Such a malfunction of the memory circuit has a serious problem on the system. For example, a memory circuit is used as a control circuit of a memory circuit having memory means such as an EEPROM. The control circuit generates a control signal used for writing and erasing the memory means, and a memory circuit is often used as a latch circuit for latching the control signal. The unintentional rewriting of the control signal of the memory circuit is regarded as a signal for permitting the memory means to perform a write or erase operation, and as a result, the information in the memory means is rewritten unintentionally.

[Block diagram of memory means: FIG. 5]
explain in detail. FIG. 5 is a block diagram for explaining a memory circuit having the memory circuit described above as a control circuit. 14 is a bi-directional data line, 15 is a signal line for inputting the shift clock CK of the shift register, 16 is a power line for a high voltage VPP used for writing and erasing, 17 is a shift register, and 18 is for decoding shift register data. Decoding circuit 19 is a control circuit, and 20 is an EEPROM as a memory means.
A signal DATA is input to the bidirectional data line 14 at the time of input, and read data of the EEPROM 20 is output at the time of output. The signal DATA is input to the shift register 17 and decoded by the decoding circuit 18.
The control circuit 19 uses a latch circuit (memory circuit) and creates a flag for controlling operations for writing and erasing. The flag is an electric signal. For example, when the control circuit 19 outputs a signal for controlling writing to the EEPROM 20, the writing flag is set.

  A high potential VPP which is a voltage used for writing and erasing of the EEPROM 20 is supplied from the power supply line 16. For example, when writing is performed, the control circuit 19 sets a writing flag. In this state, the output of the latch circuit included in the control circuit 19 is “1”. The value of this flag is held until the control is completed, and the high potential VPP which is the write voltage of the EEPROM 20 is controlled to be supplied during the holding period.

  The power supply voltage fluctuation noise propagating through the power supply line and the ground line fluctuates the output of the latch circuit included in the control circuit 19. For example, if the flag of the control circuit 19 changes from “1” to “0” due to a malfunction of the latch circuit, writing to the EEPROM 20 may be terminated halfway. Of course, a malfunction also occurs in the case of erasing to the EEPROM 20. Therefore, a malfunction of the latch circuit causes the EEPROM 20 to perform a write operation and an erase operation unintentionally.

  In this way, a circuit different from the memory circuit operates, and it is very difficult to accurately know whether or not the power supply voltage fluctuation noise propagates to the power supply line or the ground line of the memory circuit, and the generation timing thereof. The technology cannot completely prevent unintended data rewriting and erasing of the memory circuit.

  In order to solve the above-described problems, the memory circuit of the present invention has the following characteristics.

A data input terminal for inputting data, a clock input terminal for inputting a timing for holding the value of the data, and an output terminal for outputting the held data are provided. In a memory circuit having a bit storage circuit,
The memory circuit includes a first latch circuit that holds data and a second latch circuit that holds an inverted signal of the data, and an inverting output unit that inverts and outputs the output of the second latch circuit And an AND circuit that calculates the product of the output of the inverting output means and the output of the first latch circuit.

  The first latch circuit and the second latch circuit are characterized by being supplied with a driving voltage through the same power line or arranged close to each other.

  The first latch circuit and the second latch circuit have the same circuit configuration or the same element.

  The first latch circuit or the second latch circuit is a data input type flip-flop.

According to the memory circuit of the present invention, no malfunction occurs even if noise propagates to the power supply line or the ground line. Even if a memory circuit constituting the memory circuit malfunctions due to noise, an erroneous signal is not output from the memory circuit.
The memory circuit of the present invention can prevent malfunction caused by noise caused by the circuit operation not only when the power is turned on but also during the circuit operation.

  The memory circuit of the present invention can be used for a control circuit of a nonvolatile memory such as an EEPROM. That is, the memory circuit of the present invention can be used as a latch circuit for control signals for writing and erasing of a nonvolatile memory. In such a case, erroneous writing to the nonvolatile memory and erroneous erasure can be prevented, and a highly reliable memory device can be configured.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a memory circuit of the present invention. In FIG. 1, 1 is a data signal line, 2 is a clock signal line, 3 is an output signal line, 5 is a first latch circuit, 6 is a second latch circuit, and 7 is an output signal line of the first latch circuit 5. , 8 is an output signal line of the second latch circuit 6, 11 is a first inverted output means, 12 is a second inverted output means, 9 is an output signal line of the second inverted output means, and 13 is an AND circuit. is there.
Each of the first latch circuit 5 and the second latch circuit 6 is a 1-bit storage circuit in which two states change alternately, and is, for example, a data input type flip-flop circuit. In FIG. 1, it is indicated by a symbol FF. The memory circuit of the present invention inputs the first latch circuit 5, the second latch circuit 6 for inputting inverted data thereof, and the inverted output signals of the first latch circuit 5 and the second latch circuit 6. And an AND circuit 13.

A data signal DATA is input to the data signal line 1, a clock signal CK is input to the clock signal line 2, and an output signal OUT is output to the output signal line 3.
The data signal DATA is connected to the data input terminal of the first latch circuit 5 and the input terminal of the first inverting output means 11. An inverted signal of the data signal DATA is generated and inputted to the data input terminal of the second latch circuit 6 by the first inverted output means 11.
The first inversion output unit 11 and the second inversion output unit 12 are, for example, inverter circuits.

The clock signal CK is input to the clock input terminals of the first latch circuit 5 and the second latch circuit 6, and the first latch circuit 5 and the second latch circuit 6 are connected to the rising edge of the clock signal CK. To latch the data signal and output the output signal from the output signal lines 7 and 8.
The output signal 8 of the second latch circuit 6 is inverted by the second inversion output means 12. The output signal line 7 of the first latch circuit and the output signal line 9 of the second output inverting means 12 are connected to the input terminal of the AND circuit 13, and the output of the first latch circuit 5 and the second latch The product with the inverted output of the circuit 6 is calculated.

The first latch circuit 5 and the second latch circuit 6 are supplied with a driving voltage through the same power supply line or arranged close to each other.
By doing so, a malfunction that occurs due to noise propagating through the power supply line and the ground line occurs with high probability in either one or both of the first latch circuit 5 and the second latch circuit 6.

  In normal times, the data held by the first latch circuit 5 and the second latch circuit 6 are inverted from each other. Therefore, a signal obtained by inverting the output of the second latch circuit 6 (signal of the output signal line 8). The (signal of the output signal line 9) is in phase with the output of the first latch circuit 5 (signal of the output signal line 7), and does not change even if the AND circuit 13 calculates the logical product.

  When a malfunction occurs due to noise propagating through the power supply line or the ground line, the data held by the first latch circuit 5 and the second latch circuit 6 are the same (for example, high level), and the second latch circuit 6 (the signal of the output signal line 9) is inverted in phase with the output of the first latch circuit 5 (the signal of the output signal line 7). Then, even if the AND circuit 13 calculates the logical product, no data is output from the output signal line 3. That is, even if the first latch circuit 5 and the second latch circuit 6 malfunction, the memory circuit does not output an erroneous signal.

  It is preferable that the first latch circuit 5 and the second latch circuit 6 have the same circuit configuration. In addition, when these latch circuits are constituted by switching elements such as semiconductor elements, it is preferable that the circuits are constituted by elements having the same electrical characteristics. With such a configuration, the first latch circuit 5 and the second latch circuit 6 are easily affected by the same noise with respect to noise propagating through the power supply line and the ground line.

[Timing chart of the present invention: FIG. 2]
FIG. 2 is a diagram illustrating a timing chart of the memory circuit of the present invention. VDD is a positive power supply potential of the memory circuit and a high level power supply potential, and VSS is a negative power supply potential and a low level potential. For example, for example, VDD is + 5V and VSS is 0V (ground potential). 22a indicates noise generated in the VDD potential as the power supply potential, and 22b indicates noise generated in the VSS potential as the ground potential.

A signal 70 is a signal of the output signal line 7 of the first latch circuit 5, a signal 80 is a signal of the output signal line 8 of the second latch circuit 6, and OUT is an output signal of the AND circuit 13.
Normally, the first latch circuit 5 and the second latch circuit 6 latch the signals that are inverted with each other, but the internal logic state is not determined immediately after the power is turned on. Therefore, the internal logic states of the first latch circuit 5 and the second latch circuit 6 are fixed to a high level by the noises 22a and 22b generated when the power is turned on. This is because the first latch circuit 5 and the second latch circuit 6 are supplied with driving voltage through the same power supply line or arranged close to each other, so that It is because it receives the same influence.

  As shown in FIG. 2, even if the signal 70 and the signal 80 are at a high level due to the influence of noise at the timing T1, the period of the AND circuit 13 during the period up to the timing T3 when the rising edge of the regular clock signal CK is input. The output signal OUT is not affected by the malfunction of the first latch circuit 5 and the second latch circuit 6. That is, in order to output the logical product of the output signal of the first latch circuit 5 and the output signal obtained by inverting the output signal of the second latch circuit 6 to the output line OUT as the operation result, the output OUT of the memory circuit itself is The malfunction of the latch circuit is not reflected.

  Although the influence of noise generated when the power of the memory circuit of the present invention is turned on has been described with reference to FIG. 2, the memory circuit of the present invention can of course be affected even by the influence of noise caused by the operation of other circuits during normal operation. Needless to say, it operates normally.

As is apparent from the above description, the memory circuit of the present invention does not malfunction as a whole memory circuit even if the memory circuit constituting the circuit malfunctions due to noise propagating to the power supply line or the ground line. It is.
Although noise propagated to the power supply line and the ground line is generated not only when the memory circuit is powered on but also during circuit operation, the memory circuit of the present invention does not malfunction.

  The memory circuit of the present invention does not malfunction due to noise even when the memory circuit is powered on or in operation. Therefore, it can be applied to a control circuit of a memory device such as an EEPROM. In particular, it is suitable for a memory device for electronic equipment that should not be affected by noise.

It is a block diagram of a memory circuit of the present invention. 3 is a timing chart illustrating a memory circuit of the present invention. It is a timing chart of a prior art. It is a block diagram of the memory circuit of a prior art. It is a block diagram explaining the control circuit of the EEPROM of a prior art.

Explanation of symbols

1 data signal line 2 clock signal line 3 output signal line 5 first latch circuit 6 second latch circuit 7 output signal line of first latch circuit 5 8 output signal line of second latch circuit 6 11 first Inverted output means 12 Second inverted output means 13 AND circuit 70 Signal on output signal line 7 80 Signal on output signal line 8

Claims (4)

A data input terminal for inputting data, a clock input terminal for inputting timing for holding the value of the data, and an output terminal for outputting the held data, and the two states change alternately In a memory circuit having a 1-bit storage circuit,
The memory circuit includes a first latch circuit that holds the data, and a second latch circuit that holds an inverted signal of the data,
Inverting output means for inverting and outputting the output of the second latch circuit;
A memory circuit comprising: an AND circuit for calculating a product of an output of the inverting output means and an output of the first latch circuit.   2. The memory according to claim 1, wherein the first latch circuit and the second latch circuit are supplied with a driving voltage through the same power line or are arranged close to each other. circuit.   3. The memory circuit according to claim 1, wherein the first latch circuit and the second latch circuit are configured with the same circuit configuration or the same element.   4. The memory circuit according to claim 1, wherein the first latch circuit or the second latch circuit is a data input type flip-flop. 5.

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