JP2007173503A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the ON-state resistance or the ON-state voltage is effectively reduced and the OFF-state withstand voltage is effectively improved. <P>SOLUTION: This semiconductor device 1 comprises an n-type drift region 20, a p-type body region 30, a source region 40 formed on the surface of the semiconductor device 1 and separated from the drift region 20 by the body region 30, a trench 61 extending from the surface of the source region 40 to the body region 30, and gate insulating films 62 and 65 formed on the inner wall of the trench 61. The depth from the surface of the semiconductor device 1 to the surface side of the gate insulating film 65 on the bottom is less than the depth from the surface of the semiconductor device 1 to the drift region 20. Further, the semiconductor device has semiconductor regions 70 containing a high concentration n-type impurity and formed in the body region 30 to be opposed to the thickness portion of the gate insulating film 65 on the bottom, and to be in contact with the drift region 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device that effectively reduces on-resistance or on-voltage, and effectively improves off-breakdown voltage, and a method for manufacturing the same.

A drift region, a body region provided above the drift region, a source region formed on a part of the surface of the body region and separated from the drift region by the body region, and a surface of the source region A vertical MOSFET having a trench gate electrode extending in a drift region is known.
A gate insulating film is provided on the inner wall of the trench gate electrode, and a conductive member such as polysilicon is embedded in the trench. Generally, the depth from the surface of the semiconductor device to the bottom of the conductive member (depth to the surface of the gate insulating film formed at the bottom of the trench) is configured to reach the drift region. Thereby, when the semiconductor device is turned on, the conductivity type of the body region opposed to the side wall of the trench gate electrode through the gate insulating film is inverted to form a channel region. The source region and the drift region are conducted through the channel region.
However, according to this configuration, when the semiconductor device is in the OFF state, the electric field due to the voltage applied between the gate and the drain tends to concentrate on the edge portion at the bottom of the trench gate electrode. As a result, the off breakdown voltage of the semiconductor device is determined by the degree of concentration of the electric field in the vicinity of the edge portion at the bottom of the trench gate electrode, and the off breakdown voltage may be lowered.

Therefore, in the semiconductor device 100 of Patent Document 1 shown in FIG. 17, the bottom of the trench gate electrode 160 does not reach the drift region 120. That is, the trench gate electrode 160 is formed from the surface of the source region 140 to the middle of the body region 130 in the depth direction. Further, a semiconductor region 170 containing impurities of the same conductivity type as the drift region 120 is disposed from the bottom of the trench gate electrode 160 to the drift region 120. As a result, when the semiconductor device 100 is turned on, the channel region 160a formed in the body region 130 (x mark portion in FIG. 17) facing the sidewall of the trench gate electrode 160 with the gate insulating film 162 therebetween. The source region 140 and the drift region 120 can be brought into conduction through the semiconductor region 170. According to this configuration, the electric field due to the voltage applied between the gate and the drain when the semiconductor device is in the off state is less likely to concentrate on the edge portion E at the bottom of the trench gate electrode, thereby improving the off breakdown voltage. be able to.
JP 2000-269487 A

In the semiconductor device 100 of Patent Document 1, the source region 140 and the drift region 120 are turned on through the channel region 160a and the semiconductor region 170, as shown in FIG. Since the semiconductor region 170 serves as a current path, the on-resistance can be reduced when the impurity concentration is high. However, the vicinity of the semiconductor region 170 is a region that should be depleted in the off state. When the impurity concentration of the semiconductor region 170 is high, a depletion layer is hardly formed, and the off breakdown voltage can be effectively improved. Can not. Therefore, the impurity concentration of the semiconductor region 170 is set according to the balance between the off breakdown voltage and the on resistance, and it is difficult to set the impurity concentration that sufficiently satisfies both.
The present invention has been devised to solve the above problems. The present invention provides a technique for effectively reducing on-resistance or on-voltage and effectively improving off-breakdown voltage.

(Invention of Claim 1)
The semiconductor device of the present invention includes a first semiconductor region containing a first conductivity type impurity, a second semiconductor region containing a second conductivity type impurity and provided above the first semiconductor region, and a first conductivity type. A third semiconductor region which is formed on the surface of the semiconductor device in a state containing a type impurity and is separated from the first semiconductor region by the second semiconductor region, and in the second semiconductor region from the surface of the third semiconductor region , A gate insulating film formed on the inner wall of the trench, and a trench gate electrode surrounded by the gate insulating film. The depth from the surface of the semiconductor device to the surface of the gate insulating film formed at the bottom of the trench is shallower than the depth from the surface of the semiconductor device to the surface of the first semiconductor region. The semiconductor device further includes a fourth semiconductor region formed in the second semiconductor region at a position in contact with the gate insulating film formed at the bottom of the trench and the first semiconductor region, while containing a high concentration of the first conductivity type impurity. ing.
The first semiconductor region only needs to have a region containing the first conductivity type impurity, and may not contain the first conductivity type impurity over the entire region.
In this semiconductor device, the depth from the surface of the semiconductor device to the surface of the gate insulating film formed at the bottom of the trench is shallower than the depth from the surface of the semiconductor device to the surface of the first semiconductor region. In addition, the trench itself may be formed from the third semiconductor region to the first semiconductor region extending into the second semiconductor region, or may be formed partway through the second semiconductor region. That is, the first semiconductor region may or may not be reached. When the bottom of the trench reaches the first semiconductor region, the electric field tends to concentrate on the bottom of the gate insulating film when the semiconductor device is in an off state. Therefore, the gate insulating film formed on the bottom of the trench is formed thick. Is preferred. When the bottom of the trench does not reach the first semiconductor region, the gate insulating film formed on the bottom of the trench does not necessarily need to be formed thick.

Inside the gate insulating film formed on the inner wall of the trench, a conductive electrode member such as polysilicon is buried to form a trench gate electrode. In the semiconductor device of the present invention, the depth from the surface of the semiconductor device to the surface of the gate insulating film formed at the bottom of the trench is shallower than the depth from the surface of the semiconductor device to the surface of the first semiconductor region. ing. Therefore, the portion (trench gate electrode) filled with the conductive electrode member is not provided in the first semiconductor region.
Accordingly, it is possible to prevent the electric field from being concentrated on the edge portion at the bottom of the gate electrode when the semiconductor device is in the off state. Further, the off breakdown voltage of the semiconductor device, for example, the breakdown voltage between the gate and the drain when the semiconductor device is a MOS FET or the like, and the breakdown voltage between the gate and the collector when the semiconductor device is an IGBT or the like can be improved. In the semiconductor device of the present invention, since the fourth semiconductor region containing the impurity at a high concentration is provided, the channel formed in the trench side wall portion of the second semiconductor region when the semiconductor device is in the on state. The third semiconductor region and the first semiconductor region are electrically connected through the layer and the fourth semiconductor region. The on-resistance or on-voltage of the semiconductor device can be reduced.
Therefore, when the semiconductor device of the present invention is used, the on-resistance or the on-voltage can be effectively reduced and the off-breakdown voltage can be effectively improved.

(Invention of Claim 2)
The first semiconductor region of the semiconductor device includes a fifth semiconductor region containing an impurity of the first conductivity type and a sixth semiconductor region containing an impurity of the second conductivity type, and the fifth semiconductor region and the sixth semiconductor region are mutually In a state where they are paired with each other, they may be distributed on the back side of the second semiconductor region. A semiconductor device having a so-called super junction structure has the above-described configuration.
The present invention is also useful when applied to a semiconductor device having a super junction structure. In this case, generally, a trench is formed above the fifth semiconductor region to form a trench gate electrode.

(Invention of Claim 3)
In the semiconductor device having the super junction structure described above, an insulating film may be provided between the fifth semiconductor region and the sixth semiconductor region.
According to this, when the fourth semiconductor region is formed, the insulating film serves as an impurity diffusion preventing film, so that the impurity is not diffused unnecessarily into the semiconductor region where unnecessary. Therefore, a semiconductor device with good characteristics can be easily formed.

(Invention of Claim 4)
According to the method of manufacturing a semiconductor device of the present invention, a step of forming a first semiconductor region containing a first conductivity type impurity and a second semiconductor region containing a second conductivity type impurity are formed on the first semiconductor region. A step, a step of forming a third semiconductor region containing an impurity of the first conductivity type in a part of a surface of the second semiconductor region, and a step of forming a trench extending from the surface of the third semiconductor region to the second semiconductor region. An impurity diffusion source disposing step of disposing a gate insulating member including a diffusion source of the first conductivity type impurity at the bottom of the trench, and a heating step of performing thermal oxidation on the inner wall surface of the trench to form a gate insulating film. Yes. And a heating process is implemented after an impurity diffusion source arrangement | positioning process.
As the “gate insulating member including an impurity diffusion source”, a gate insulating member originally including an impurity diffusion source may be used, or after the gate insulating member is disposed, the impurity diffusion source is used as the gate insulating member. It may be injected. Further, the impurity diffusion source arrangement step may be performed before the step of forming the trench, or may be performed after the step of forming the trench.
Further, the impurity of the gate insulating member including the impurity diffusion source may be diffused into the second semiconductor region by the heating process. That is, the heating step may be performed after the impurity diffusion source arrangement step, and may be performed immediately or not immediately after.

According to the method for manufacturing a semiconductor device of the present invention, when the gate insulating film is formed on the inner surface of the trench in the heating process, the first gate insulating member is included in the gate insulating member from the gate insulating member disposed at the bottom of the trench. Conductive impurities can be diffused into the second semiconductor region in contact with the gate insulating member.
As a result, the fourth semiconductor region containing the first conductivity type impurity is formed in the second semiconductor region at a position in contact with both the gate insulating film and the first semiconductor region formed at the bottom of the trench. A gate insulating film can be formed on the inner wall surface. Therefore, the manufacturing cost of the semiconductor device can be reduced by reducing the number of steps.

  According to the present invention, the on-resistance or on-voltage of the semiconductor device is effectively reduced and the off-breakdown voltage is effectively improved.

The main features of the embodiments described below are listed.
(First Embodiment) A gate insulating member including a diffusion source of a first conductivity type impurity and a gate insulating member for preventing diffusion of impurities are disposed below the trench bottom.
(Second Embodiment) The gate insulating member for preventing diffusion is made of silicon nitride.
(Third Embodiment) A super junction structure is formed on the back side of the body region.
(Fourth Embodiment) In the super junction structure formed on the back side of the body region, an insulating film is provided between the n column and the p column. The trench gate electrode is formed in the body region located on the surface side of the n column.
(Fifth Embodiment) A step of forming a trench after performing a step of forming an insulating film between an n column and a p column, and a gate insulating member including a diffusion source of a first conductivity type impurity at the bottom of the trench. An impurity diffusion source disposing step for disposing and a heating step for forming a gate insulating film by performing thermal oxidation on the inner wall surface of the trench are sequentially performed.

(First embodiment)
The semiconductor device 1 according to the first embodiment will be described below with reference to FIGS. In the first embodiment, the present invention is applied to a power MOSFET.
FIG. 1 is a sectional view of a semiconductor device 1 according to the first embodiment. 2 to 6 show a method for manufacturing the semiconductor device 1.
As shown in FIG. 1, in the semiconductor device 1, an n ⁻ type drift region (an example of the first semiconductor region in the claims) 20 is provided on an n ⁺ type drain region 10. Further, on the surface side of drift region 20 (upper side shown in FIG. 1), a p ⁻ -type body region (example of second semiconductor region in claims) 30 is provided. In addition, n ⁺ -type source regions (examples of the third semiconductor region in claims) 40 and 40 are provided in pairs on a part of the surface side of the body region 30. A trench gate electrode 60 extending from the surface of the semiconductor device 1 toward the lower surface of the body region 30 (the surface of the drift region 20) is formed between the n ⁺ -type source regions 40 and 40. A body contact region 50 is formed on the surface of the body region 30 on the opposite side of the trench gate electrode 60 of each source region 40.

  The inner wall of the trench 61 is covered with gate insulating films 62 and 64. The gate insulating films 62 and 64 are filled with a conductive member 64 such as polysilicon to form a trench gate electrode. The gate insulating film 65 formed at the bottom of the trench 61 is formed thicker than the gate insulating film 62 formed on the sidewall of the trench 61. For example, when the depth L2 from the drift region 20 to the surface of the semiconductor device is about 6 μm, the thickness of the gate insulating film 62 on the side wall is about 0.1 μm and the thickness of the gate insulating film 65 on the bottom is about 0.2 μm. To form. That is, each gate insulating film is formed so that the ratio of the thickness of the gate insulating film 62 on the side wall to the thickness of the gate insulating film 65 on the bottom is about 1: 2. Note that the depth L1 from the surface of the semiconductor device 1 to the surface of the gate insulating film 65 formed at the bottom of the trench 61 is shallower than the depth L2 from the surface of the semiconductor device 1 to the surface of the drift region 20. Has been.

Further, in the semiconductor device 1, a semiconductor region (an embodiment of the fourth semiconductor region in the claims) 70 containing n-type impurities in the body region 30 facing the thickness portion 65 at the bottom of the gate insulating film 62. Is provided. The semiconductor region 70 is provided in the body region 30 in contact with the surface of the drift region 20.
Although only a small part of the semiconductor device 1 is shown in FIG. 1, in practice, a large number of trench gate electrodes 60 and the like are provided, and a large number of MOSFET groups are formed.

When the semiconductor device 1 is used, a positive voltage of about several hundred V to 1000 V is applied to the drain electrode (not shown) connected to the drain region 10, and the source connected to the source region 40 and the body contact region 50. An electrode (not shown) is grounded, and the gate voltage applied to the trench gate electrode 60 is on / off controlled. When a gate-on voltage is applied to the trench gate electrode 60, the body region 30 (the portion marked with x shown in FIG. 1) facing the side wall of the trench gate electrode 60 is inverted to n-type, and a channel region 60a is formed. Therefore, the source region 40 and the drift region 20 are brought into conduction through the channel region 60 a and the semiconductor region 70. Then, electrons move from the source region 40 to the drift region 20, and the semiconductor device 1 is turned on.
When the voltage applied to the trench gate electrode 60 is turned off, the channel region 60a disappears and the semiconductor device 1 is turned off.

Here, a method for manufacturing the semiconductor device 1 will be briefly described with reference to FIGS.
First, as shown in FIG. 2, an n ⁻ type drift region 20 is formed by epitaxial growth on a drain region 10 formed of an n ⁺ type silicon substrate. Next, the surface of the drift region 20 is subjected to thermal oxidation to form a silicon oxide (SiO ₂ ) gate insulating film 65.
Next, a mask that is spaced apart by a predetermined interval is formed (not shown). Then, the gate insulating film 65 exposed from the mask is removed. As a result, as shown in FIG. 3, the gate insulating film 65 exists on the drift region 20 with a predetermined interval. Then, a step of injecting an n-type impurity diffusion source from the surface of the remaining gate insulating film 65 by an ink jet method is performed.
Next, as shown in FIG. 4, ap ⁻ type body region 30 is formed on the drift region 20 by epitaxial growth.
Next, as shown in FIG. 5, a mask M is formed on the surface of the body region 30 other than the upper portion of the remaining gate insulating film 65. Then, the body region 30 exposed from the mask M is etched to form the trench 61 up to the gate insulating film 65. Next, thermal oxidation is performed on the side wall of the trench 61 to form a silicon oxide (SiO ₂ ) gate insulating film 62 on the side wall of the trench. By this heat, the diffusion source of the n-type impurity simultaneously implanted into the upper part of each gate insulating film 65 diffuses into the body region 30 in contact with each gate insulating film 65. As a result, a semiconductor region 70 containing n-type impurities is formed in the body region 30. At this point, in the step of implanting an n-type impurity diffusion source above the gate insulating film 65 so that 0.5 × 10 ¹⁸ cm ⁻³ or more of n-type impurity diffuses into the semiconductor region 70. The amount of diffusion source at the time of injection is set. The semiconductor region 70 is formed at a position in contact with both the gate insulating film 65 and the drift region 20.
Next, as shown in FIG. 6, the trench 61 is filled with a conductive electrode member 64 to form a gate electrode 60.
Thereafter, as shown in FIG. 1, a source region 40 and a body contact region 50 are formed on part of the surface of the body region 30 by ion implantation and heat treatment.

In the semiconductor device 1 of the present embodiment, the depth L1 from the surface of the semiconductor device 1 to the surface of the gate insulating film 65 at the bottom of the trench is shallower than the depth L2 from the surface of the semiconductor device 1 to the surface of the drift region 20. Is formed. Therefore, at least a portion of the trench gate electrode 60 that is filled with the conductive electrode member 64 is not disposed in the drift region 20.
Thereby, it is possible to prevent the electric field from being concentrated on the edge portion E at the bottom of the gate electrode 60 when the semiconductor device 1 is in the OFF state. Then, the off breakdown voltage of the semiconductor device 1 can be improved.
Further, in the semiconductor device 1 of the present embodiment, the semiconductor region 70 containing impurities at a high concentration is provided, so that the semiconductor device 1 is formed on the trench side wall portion of the body region 30 when the semiconductor device 1 is in the on state. The source region 40 and the drift region 20 can be brought into conduction through the channel layer 60 a and the semiconductor region 70. In addition, the on-resistance of the semiconductor device 1 can be reduced.
Therefore, when the semiconductor device 1 is used, the on-resistance can be effectively reduced and the off-breakdown voltage can be effectively improved.

  In the first embodiment, the trench 61 reaches the surface of the drift region 20 in the depth direction (vertical direction shown in FIG. 1) (dimension in the depth direction of the trench 61 = depth L2 to the surface of the drift region 20). ) The case has been described, but the portion buried in the conductive electrode member 64 may not be disposed in the drift region 20. The trench 61 itself may be formed up to the drift region 20 (dimension in the depth direction of the trench 61> depth L2 to the surface of the drift region 20). Further, when the semiconductor device 1 is turned on, if the semiconductor region 70 is part of the path and the source region 40 and the drift region 20 can be brought into conduction, the trench 61 reaches the surface of the drift region 20. Even if it does not reach (the dimension in the depth direction of the trench 61 <the depth L2 up to the surface of the drift region 20).

(Second embodiment)
A semiconductor device 1a according to the second embodiment will be described below with reference to FIGS. In the semiconductor device 1a of the second embodiment, the impurity diffusion source placement step is performed after the trench of the trench gate electrode is formed.
FIG. 7 shows a sectional view of the semiconductor device 1a of the second embodiment. 8 to 12 show a method for manufacturing the semiconductor device 1a.
In the semiconductor device 1a, a silicon nitride (Si ₃ N ₄ ) insulating member 67a is disposed at the bottom of the trench gate electrode 60a. An insulating member 66a including an impurity diffusion source in advance is disposed on the silicon nitride insulating member 67a. A gate oxide film 62a is formed on the sidewall of the trench gate electrode 60a. Further, the depth L3 from the surface of the semiconductor device 1a to the surface of the insulating member 66a is formed to be shallower than the depth L2 from the surface of the semiconductor device 1a to the surface of the drift region 20.
Other configurations are the same as those of the semiconductor device 1 shown in FIG. 1 and 7 are denoted by the same reference numerals.

Here, a method for manufacturing the semiconductor device 1a will be described with reference to FIGS.
First, as shown in FIG. 8, an n ⁻ type drift region 20 is formed by epitaxial growth on a drain region 10 formed of an n ⁺ type silicon substrate. Next, a p ⁻ type body region 30 is formed on the drift region 20 by epitaxial growth.
Next, as shown in FIG. 9, a mask M that is spaced apart by a predetermined interval is formed. Then, the body region 30 exposed from the mask M is etched to form the trench 61 a up to the drift region 20.
Next, as shown in FIG. 10, an insulating member 67a of silicon nitride (Si ₃ N ₄ ) is formed at the bottom of each trench 61a.
Next, as shown in FIG. 11, an insulating member 66a including an n-type impurity (for example, phosphorus) diffusion source is formed on the insulating member 67a.
Then, as shown in FIG. 12, the surface of the trench 61a is thermally oxidized to form a silicon oxide (SiO ₂ ) film 62a. By this heat, the diffusion source of the n-type impurity contained in the insulating member 66a diffuses into the body region 30 in contact with each insulating member 66a. As a result, a semiconductor region 70 containing n-type impurities is formed. At this time, the amount of the n-type impurity diffusion source included in the insulating member 66a is set so that the n-type impurity diffuses in the semiconductor region 70 by 0.5 × 10 ¹⁸ cm ⁻³ or more.
Thereafter, as in the first embodiment shown in FIG. 6, each trench 61 a is filled with a conductive electrode member 64 such as polysilicon to form a gate electrode 60. Then, the mask M is removed, and a source region and a body contact region are formed on part of the surface of the body region 30 by ion implantation and heat treatment.

In the semiconductor device 1a of the present embodiment, an insulating member 67a of silicon nitride (Si ₃ N ₄ ) is formed below the insulating member 66a including the n-type impurity diffusion source. As a result, the n-type impurities contained in the insulating member 66a are difficult to diffuse into the drift region 20, and the semiconductor region 70 can be formed efficiently.

(Third embodiment)
The semiconductor device 1b according to the third embodiment will be described below with reference to FIGS. The semiconductor device 1b according to the third embodiment has a super junction structure in the drift region 20b.
FIG. 13 is a sectional view of the semiconductor device 1b according to the third embodiment. 14 to 16 show a method for manufacturing the semiconductor device 1b.
As shown in FIG. 13, a repetitive structure of n-type column 23b and p-type column 21b is formed as a super junction structure of drift region 20b. The n-type column 23b and the p-type column 21b extend in the vertical direction (vertical direction in FIG. 13) between the drain region 10 and the body region 30b. Each column 21b, 23b extends in the depth direction (direction perpendicular to the paper surface of FIG. 1), and has a predetermined width in the lateral direction (left-right direction in FIG. 1). An insulating film 22b is provided between the columns 21b and 23b. That is, each column 21b, 23b is formed in a thin plate shape, and is repeatedly provided adjacent to each other via the insulating film 22b in the horizontal direction (left-right direction in FIG. 13).

Here, a method for manufacturing the semiconductor device 1b will be described with reference to FIGS.
First, an n ⁻ type semiconductor region is formed by epitaxial growth on the drain region 10 formed of an n ⁺ type silicon substrate.
Then, as shown in FIG. 14, a mask M is formed that is separated by a predetermined interval. Then, the n ⁻ -type semiconductor region exposed from the mask M is etched to form the groove 80. As a result, n ⁻ -type semiconductor regions are present apart from each other. The n ⁻ type semiconductor region remaining by this process becomes the n-type column 23b having a super junction structure. Next, the inner peripheral surface of the groove 80 is thermally oxidized to form the insulating film 22b. The oxide film (not shown) formed on the bottom of the groove 80 is removed.
Then, the mask M shown in FIG. 14 is removed, and as shown in FIG. 15, a p-type silicon crystal is buried and epitaxially grown until the n-type column 23b is surrounded in a groove 80 that is separated from the p-type column 21b. The n-type column 23b forms a super junction structure that is alternately repeated through the insulating film 22b. At this time, the p-type impurity of the p-type column 21b diffuses from the epitaxially grown p-type semiconductor region (the semiconductor region grown further upward or laterally from the p-type column 21b) to the upper surface of the n-type column 23b. Therefore, the upper surface of the n-type column 23b is counter-doped and inverted to p-type. By this step, the p-type semiconductor region formed on the n-type column 23b becomes the body region 30b of the semiconductor device 1b. In order to form the body region 30b, a p-type impurity may be ion-implanted at the position in order to positively invert the upper portion of the n-type column 23b to the p-type.
Next, as shown in FIG. 16, a mask M is formed on the surface where the trench gate electrode 60b (also see FIG. 13) is not formed. Then, the body region 30b is etched to form a trench 61b extending from the surface to the n-type column 23b.
In the subsequent steps, like the semiconductor device 1a of the second embodiment shown in FIGS. 10 to 12, the trench gate electrode 60b is formed in the trench 61b like the trench gate electrode 60a of the semiconductor device 1a. Then, the mask M is removed, and a source region and a body contact region are formed on a part of the surface of the body region 30b by ion implantation and heat treatment.

  The semiconductor device 1b of this example has a super junction structure in the drift region 20b. As a result, the off breakdown voltage can be improved and the on resistance can be reduced. Further, the insulating film 22b provided between the p-type column 21b and the n-type column 23b serves as an impurity diffusion preventing film, so that the impurity is not diffused into the body region 30 and the semiconductor region 70 is efficiently formed. can do. Therefore, a semiconductor device with good characteristics can be easily formed.

In the first to third embodiments, the first conductivity type in the claims is n-type, and the second conductivity type is p-type. There may be an embodiment in which the first conductivity type is p-type and the second conductivity type is n-type.
In the first to third embodiments, the case where the semiconductor device is a vertical MOS field effect transistor has been described. However, the present invention can also be applied to other semiconductor devices such as IGBTs.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

1 is a cross-sectional view of a semiconductor device 1. FIG. A method for manufacturing the semiconductor device 1 will be described. A method for manufacturing the semiconductor device 1 will be described. A method for manufacturing the semiconductor device 1 will be described. A method for manufacturing the semiconductor device 1 will be described. A method for manufacturing the semiconductor device 1 will be described. A sectional view of semiconductor device 1a is shown. A method for manufacturing the semiconductor device 1a will be described. A method for manufacturing the semiconductor device 1a will be described. A method for manufacturing the semiconductor device 1a will be described. A method for manufacturing the semiconductor device 1a will be described. A method for manufacturing the semiconductor device 1a will be described. A sectional view of semiconductor device 1b is shown. A method for manufacturing the semiconductor device 1b will be described. A method for manufacturing the semiconductor device 1b will be described. A method for manufacturing the semiconductor device 1b will be described. A cross-sectional view of a conventional semiconductor device 100 is shown.

Explanation of symbols

1, 1a, 1b Semiconductor device 10 Drain region 20, 20b Drift region 21b P-type column 22b Insulating film 23b N-type column 30, 30b Body region 40 Source region 50 Body contact regions 60, 60a, 60b Trench gate electrodes 61, 61a, 61b Trench 62, 62a, 62b, 65 Gate insulating film 66a, 67a Insulating member 70 n ⁺ type semiconductor region 80 groove

Claims (4)

A first semiconductor region containing an impurity of a first conductivity type;
A second semiconductor region containing an impurity of the second conductivity type and provided on the first semiconductor region;
A third semiconductor region that includes an impurity of the first conductivity type, is formed on the surface of the semiconductor device, and is separated from the first semiconductor region by the second semiconductor region;
A trench extending from the surface of the third semiconductor region into the second semiconductor region;
A gate insulating film formed on the inner wall of the trench;
It has a trench gate electrode wrapped in a gate insulating film,
The depth from the surface of the semiconductor device to the surface of the gate insulating film formed at the bottom of the trench is shallower than the depth from the surface of the semiconductor device to the surface of the first semiconductor region;
A high-concentration impurity of the first conductivity type is included, and a gate insulating film formed at the bottom of the trench and a fourth semiconductor region formed in the second semiconductor region at a position in contact with the first semiconductor region are provided. A semiconductor device characterized by comprising: The first semiconductor region includes a fifth semiconductor region containing a first conductivity type impurity and a sixth semiconductor region containing a second conductivity type impurity,
5. The semiconductor device according to claim 1, wherein the fifth semiconductor region and the sixth semiconductor region are distributed on the back side of the second semiconductor region in a state of being paired with each other.   3. The semiconductor device according to claim 2, wherein an insulating film is provided between the fifth semiconductor region and the sixth semiconductor region. Forming a first semiconductor region containing an impurity of a first conductivity type;
Forming a second semiconductor region containing impurities of a second conductivity type on top of the first semiconductor region;
Forming a third semiconductor region containing an impurity of the first conductivity type on a part of the surface of the second semiconductor region;
Forming a trench extending from the surface of the third semiconductor region to the second semiconductor region;
An impurity diffusion source arrangement step of arranging a gate insulating member including a diffusion source of an impurity of the first conductivity type at the bottom of the trench;
A heating step of forming a gate insulating film by subjecting the inner wall surface of the trench to thermal oxidation,
A method of manufacturing a semiconductor device, wherein the heating step is performed after the impurity diffusion source arrangement step.

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