JP2007173383A - Method for forming trench element separation region, method for forming silicon nitride film liner, and manufacturing method of semiconductor device - Google Patents

Method for forming trench element separation region, method for forming silicon nitride film liner, and manufacturing method of semiconductor device Download PDF

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JP2007173383A
JP2007173383A JP2005366726A JP2005366726A JP2007173383A JP 2007173383 A JP2007173383 A JP 2007173383A JP 2005366726 A JP2005366726 A JP 2005366726A JP 2005366726 A JP2005366726 A JP 2005366726A JP 2007173383 A JP2007173383 A JP 2007173383A
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silicon nitride
nitride film
forming
silicon oxide
trench
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Takahiro Kotabe
隆宏 小田部
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Sharp Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a trench element separation region capable of easily and precisely removing a nitride silicon film liner at the upper part of a trench side wall. <P>SOLUTION: The nitride silicon film liner at the upper part of the trench side wall is removed by the method including (a) a process for forming an element separation trench by etching a semiconductor substrate, (b) a process for forming a second nitride silicon film to cover the acquired substrate, (c) a process for forming a third oxide silicon film by anisotropic film forming method so that the second nitride silicon film is covered and embedding is completed at the depth in the middle of the trench, (d) a process for isotropic etching with a third oxide silicon film so that the second nitride silicon film at the upper part of the trench side wall is exposed, and (e) a process for removing the exposed second nitride silicon film by etching. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、トレンチ素子分離領域の形成方法、窒化シリコン膜ライナーの形成方法、及び半導体装置の製造方法に関する。   The present invention relates to a method for forming a trench element isolation region, a method for forming a silicon nitride film liner, and a method for manufacturing a semiconductor device.

従来、トレンチ素子分離領域の形成方法として、以下の方法が知られている（例えば、特許文献１を参照。）
（ａ）半導体基板に素子分離用トレンチ形成のための窓を有する第１窒化シリコン膜を含むパターンをマスクとして、半導体基板をエッチングして素子分離用トレンチを形成する。
（ｂ）前記トレンチ内壁を覆うように第２窒化シリコン膜を形成する。
（ｃ）第２窒化シリコン膜を覆い、かつ前記トレンチを完全に埋め込むように第１酸化シリコン膜を形成する。
（ｄ）第１酸化シリコン膜をエッチングし、前記トレンチ側壁上部の第２窒化シリコン膜が露出するまで除去する。
（ｅ）露出した第２窒化シリコン膜をエッチングして除去する。
（ｆ）前記トレンチを埋め込むように第２酸化シリコン膜を形成する。
（ｇ）第１窒化シリコン膜をストッパとして、第２酸化シリコン膜を化学機械研磨する。
（ｈ）露出した第１窒化シリコン膜をエッチングして除去する。 Conventionally, the following method is known as a method for forming a trench element isolation region (see, for example, Patent Document 1).
(A) Using a pattern including a first silicon nitride film having a window for forming an isolation trench on the semiconductor substrate as a mask, the semiconductor substrate is etched to form an isolation trench.
(B) A second silicon nitride film is formed so as to cover the inner wall of the trench.
(C) forming a first silicon oxide film so as to cover the second silicon nitride film and completely fill the trench;
(D) The first silicon oxide film is etched and removed until the second silicon nitride film on the trench sidewall is exposed.
(E) The exposed second silicon nitride film is removed by etching.
(F) A second silicon oxide film is formed so as to fill the trench.
(G) Chemical mechanical polishing of the second silicon oxide film using the first silicon nitride film as a stopper.
(H) The exposed first silicon nitride film is removed by etching.

以上の工程によって、トレンチ内壁に第２窒化シリコン膜を有するトレンチ素子分離領域が得られる。第２窒化シリコン膜は、トレンチ内の第１酸化シリコン膜が収縮して素子形成領域に加える圧縮応力を緩和する機能を有している。このような機能から、トレンチ内壁に形成された窒化シリコン膜は、窒化シリコン膜ライナーと呼ばれている。   Through the above steps, a trench element isolation region having the second silicon nitride film on the inner wall of the trench is obtained. The second silicon nitride film has a function of relieving compressive stress applied to the element formation region by contraction of the first silicon oxide film in the trench. Because of this function, the silicon nitride film formed on the inner wall of the trench is called a silicon nitride film liner.

上記方法では、トレンチ側壁上部において、第２窒化シリコン膜からなる窒化シリコン膜ライナーが除去されているが、これは、トレンチ内壁全体に窒化シリコン膜ライナーが形成されていると、基板表面の第１窒化シリコン膜を除去する際に、窒化シリコン膜ライナーも一部除去されて、凹部（ｄｅｖｏｔ）が形成されることがあるためである。
特開２００４−２０７５６４号公報 In the above method, the silicon nitride film liner made of the second silicon nitride film is removed at the upper portion of the trench side wall. This is because when the silicon nitride film liner is formed on the entire trench inner wall, the first surface on the substrate surface is removed. This is because when the silicon nitride film is removed, a part of the silicon nitride film liner is also removed to form a recess.
JP 2004-207564 A

凹部形成を避けるために、トレンチ側壁上部において窒化シリコン膜ライナーの除去を行っているが、窒化シリコン膜ライナーの除去深さ（除去された部分の基板表面からの長さ）がばらつくと、素子形成領域に加わる応力の大きさがばらつき、その結果、素子形成領域にトランジスタを形成したときのドレイン電流の大きさがばらつくことになる。従って、窒化シリコン膜ライナーの除去深さのばらつきを減少させることが望まれている。   In order to avoid the formation of recesses, the silicon nitride film liner is removed at the upper portion of the trench sidewall. However, if the removal depth of the silicon nitride film liner (the length of the removed portion from the substrate surface) varies, element formation is performed. The magnitude of the stress applied to the region varies, and as a result, the magnitude of the drain current when the transistor is formed in the element formation region varies. Therefore, it is desired to reduce the variation in the removal depth of the silicon nitride film liner.

本発明はこのような事情に鑑みてなされたものであり、簡易かつ精度よく、トレンチ側壁上部の窒化シリコン膜ライナーの除去を行うことができる、トレンチ素子分離領域の形成方法を提供するものである。   The present invention has been made in view of such circumstances, and provides a method for forming a trench element isolation region capable of easily and accurately removing a silicon nitride film liner on an upper portion of a trench sidewall. .

課題を解決するための手段及び発明の効果Means for Solving the Problems and Effects of the Invention

本発明のトレンチ素子分離領域の形成方法は、（ａ）半導体基板に素子分離用トレンチ形成のための窓を有する第１酸化シリコン膜及び第１窒化シリコン膜を含むパターンをマスクとして、半導体基板をエッチングして素子分離用トレンチを形成する工程と、（ｂ）前記トレンチ内に露出したシリコン基板表面に第２酸化シリコン膜を形成し、更に第２酸化シリコン膜及び前記パターン表面に第２窒化シリコン膜を形成する工程と、（ｃ）第２窒化シリコン膜を覆い、前記トレンチの途中の深さで埋め込みを終えるように第３酸化シリコン膜を異方性の成膜法によって形成する工程と、（ｄ）第３酸化シリコン膜を等方性エッチングし、トレンチ側壁上部の第２窒化シリコン膜が露出するまで除去する工程と、（ｅ）露出した第２窒化シリコン膜をエッチングして除去する工程と、（ｆ）前記トレンチを埋め込むように第４酸化シリコン膜を形成する工程と、（ｇ）第２又は第１窒化シリコン膜をストッパとして、第４酸化シリコン膜を平坦化する工程と、（ｈ）第２及び第１窒化シリコン膜、又は第１窒化シリコン膜をエッチングして除去してトレンチ素子分離領域を形成する工程とを含むことを特徴とする。   A method for forming a trench element isolation region according to the present invention includes: (a) using a pattern including a first silicon oxide film and a first silicon nitride film having a window for forming an element isolation trench in a semiconductor substrate as a mask; (B) forming a second silicon oxide film on the surface of the silicon substrate exposed in the trench, and further forming a second silicon nitride film on the second silicon oxide film and the pattern surface. A step of forming a film; and (c) a step of forming a third silicon oxide film by an anisotropic film formation method so as to cover the second silicon nitride film and finish filling at a depth in the middle of the trench; (D) a step of isotropically etching the third silicon oxide film to remove it until the second silicon nitride film on the trench sidewall is exposed; and (e) the exposed second silicon nitride film. Removing the film by etching; (f) forming a fourth silicon oxide film so as to fill the trench; and (g) a fourth silicon oxide film using the second or first silicon nitride film as a stopper. And (h) a step of etching and removing the second and first silicon nitride films or the first silicon nitride film to form a trench element isolation region.

本発明者らは、異方性の成膜法によって前記トレンチを途中まで第３酸化シリコン膜で埋め込み（工程（ｃ））、第３酸化シリコン膜を等方性エッチングすることによって、トレンチ側壁の第３酸化シリコン膜を除去して、トレンチ側壁上部の窒化シリコン膜を露出させる（工程（ｄ））ことができることを見出し、本発明の完成に到った。   The inventors filled the trench with a third silicon oxide film halfway by an anisotropic film formation method (step (c)), and isotropically etched the third silicon oxide film, thereby It has been found that the third silicon oxide film can be removed to expose the silicon nitride film on the trench sidewall (step (d)), and the present invention has been completed.

第３酸化シリコン膜は、トレンチの途中の深さで埋め込みを終えるため、特許文献１の方法と比較して、成膜量を減らすことができる。また、第３酸化シリコン膜のエッチング量も減少させることができる。従って、本発明によれば、成膜・エッチングに必要な材料や時間を減少させることができる。   Since the third silicon oxide film is embedded at a depth in the middle of the trench, the amount of film formation can be reduced as compared with the method of Patent Document 1. In addition, the etching amount of the third silicon oxide film can be reduced. Therefore, according to the present invention, materials and time required for film formation / etching can be reduced.

また、本発明によれば、第３酸化シリコン膜について、以下の二種類のばらつきを減少させることができる。
（１）パターン疎密によるばらつき
ＨＤＰＣＶＤ法などによる成膜では、一般に、膜の堆積速度は、密（狭い）パターンの部分で大きく、疎（広い）パターンの部分では小さい。一方、エッチングの速度は、一般に、パターン疎密による影響を受けにくい。従って、形成する膜の厚さが大きくなるほど、密パターンの部分と疎パターンの部分とで、エッチング後に残る膜の厚さの差が大きくなる。本発明では、トレンチの途中の深さで第３酸化シリコン膜の埋め込みを終えるため、特許文献１の場合よりも、成膜量が小さくなる。従って、本発明によれば、密パターンの部分と疎パターンの部分と間の、エッチング後に残る膜の厚さの差（ばらつき）を減少させることができる。
（２）面内ばらつき
基板面全体で厳密に均一に成膜やエッチングを行うことは極めて困難であり、成膜・エッチングともに、通常は、一定のばらつきが発生する。このばらつきは、成膜量・エッチング量が大きくなるほど、それぞれ大きくなる。本発明によれば、第３酸化シリコン膜の成膜量及びエッチング量の両方を、特許文献１の場合よりも、少なくすることができる。従って、本発明によれば、面内ばらつきを減少させることができる。 Further, according to the present invention, the following two types of variations can be reduced for the third silicon oxide film.
(1) Variation due to pattern density In film formation by the HDPCVD method or the like, generally, the deposition rate of a film is large in a dense (narrow) pattern portion and small in a sparse (wide) pattern portion. On the other hand, the etching rate is generally less affected by pattern density. Therefore, as the thickness of the film to be formed increases, the difference in the thickness of the film remaining after etching increases between the dense pattern portion and the sparse pattern portion. In the present invention, since the third silicon oxide film is embedded at a depth in the middle of the trench, the amount of film formation is smaller than in the case of Patent Document 1. Therefore, according to the present invention, the difference (variation) in the thickness of the film remaining after etching between the dense pattern portion and the sparse pattern portion can be reduced.
(2) In-plane variation It is extremely difficult to perform film formation and etching strictly and uniformly over the entire substrate surface, and usually a certain variation occurs in both film formation and etching. This variation increases as the film formation amount and the etching amount increase. According to the present invention, both the amount of film formation and the etching amount of the third silicon oxide film can be reduced as compared with the case of Patent Document 1. Therefore, according to the present invention, in-plane variation can be reduced.

第３酸化シリコン膜の、エッチング後の膜厚のばらつきが減少すると、第２窒化シリコン膜からなる窒化シリコン膜ライナーのトレンチ側壁上部での除去量（除去深さ）のばらつきも減少する。従って、本発明によれば、精度よく、窒化シリコン膜ライナーを形成することができる。   When the variation in the thickness of the third silicon oxide film after etching decreases, the variation in the removal amount (removal depth) of the silicon nitride liner made of the second silicon nitride film on the trench sidewall also decreases. Therefore, according to the present invention, the silicon nitride film liner can be formed with high accuracy.

本発明は、別の観点では、（ａ）半導体基板をエッチングして素子分離用トレンチを形成する工程と、（ｂ）得られた基板を覆うように第２窒化シリコン膜を形成する工程と、（ｃ）第２窒化シリコン膜を覆い、前記トレンチの途中の深さで埋め込みを終えるように第３酸化シリコン膜を異方性の成膜法によって形成する工程と、（ｄ）第３酸化シリコン膜を等方性エッチングし、トレンチ側壁上部の第２窒化シリコン膜が露出するまで除去する工程と、（ｅ）露出した第２窒化シリコン膜をエッチングして除去する工程を含む窒化シリコン膜ライナーの形成方法を提供するものである。本明細書中でのトレンチ素子分離領域の形成方法についての説明は、基本的に、この窒化シリコン膜ライナーの形成方法についても当てはまる。   According to another aspect of the present invention, (a) a step of etching a semiconductor substrate to form an element isolation trench, (b) a step of forming a second silicon nitride film so as to cover the obtained substrate, (C) a step of covering the second silicon nitride film and forming a third silicon oxide film by an anisotropic film forming method so as to finish filling at a mid-depth of the trench; and (d) a third silicon oxide film. A silicon nitride film liner comprising: isotropically etching the film and removing the second silicon nitride film on the trench sidewalls until the second silicon nitride film is exposed; and (e) etching and removing the exposed second silicon nitride film. A forming method is provided. The description of the method for forming the trench element isolation region in this specification is basically applicable to the method for forming the silicon nitride film liner.

以下、本発明の一実施形態を図面を用いて説明する。図面は、説明の便宜のために用いられるものであり、本発明の範囲は、図面に示す実施形態に限定されない。また、以下の説明中での成膜やエッチングの方法や条件、及び各種寸法は、例示であって、ここに示したものに限定されない。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are used for convenience of explanation, and the scope of the present invention is not limited to the embodiments shown in the drawings. In addition, film formation and etching methods and conditions and various dimensions in the following description are examples, and are not limited to those shown here.

１．素子分離用トレンチ形成工程（工程（ａ））
図１（ａ），（ｂ）に示すように、この工程では、半導体基板１に素子分離用トレンチ５形成のための窓を有する第１酸化シリコン膜２及び第１窒化シリコン膜３を含むパターンＰをマスクとして、半導体基板１をエッチングして素子分離用トレンチ５を形成する。この工程は、具体的には、以下のように実施することができる。
まず、半導体基板１上に第１酸化シリコン膜２及び第１窒化シリコン膜３を順次形成し、図１（ａ）に示す構造を得る。 1. Element isolation trench formation step (step (a))
As shown in FIGS. 1A and 1B, in this step, a pattern including a first silicon oxide film 2 and a first silicon nitride film 3 having a window for forming an element isolation trench 5 in a semiconductor substrate 1. Using P as a mask, the semiconductor substrate 1 is etched to form element isolation trenches 5. Specifically, this step can be performed as follows.
First, the first silicon oxide film 2 and the first silicon nitride film 3 are sequentially formed on the semiconductor substrate 1 to obtain the structure shown in FIG.

半導体基板１は、シリコン基板などからなり、本実施形態では、半導体基板１がシリコン基板である場合を例にとって、説明を進めるが、別の種類の基板を用いる場合でもエッチングガス等を適宜変更することによって、本発明は実施可能である。   The semiconductor substrate 1 is made of a silicon substrate or the like, and in the present embodiment, the description will be given by taking the case where the semiconductor substrate 1 is a silicon substrate as an example, but the etching gas or the like is appropriately changed even when another type of substrate is used. Thus, the present invention can be implemented.

第１酸化シリコン膜２は、熱酸化等により形成することができ、厚さ２〜２０ｎｍ、例えば厚さ１０ｎｍで形成することが好ましい。熱酸化は、半導体基板１を８００〜１１００℃で熱処理することによって行うことができる。第１窒化シリコン膜３は、厚さ５０ｎｍ〜１５０ｎｍ、例えば厚さ１００ｎｍで形成することが好ましい。第１窒化シリコン膜３は、ＬＰＣＶＤ（低圧化学気相堆積）法などにより形成することができ、このＬＰＣＶＤは、例えば、ソースガスとしてＳｉＨ2ＣＬ2とＮＨ3を用い、温度７５０℃で行うことができる。第１酸化シリコン膜２は、不要な場合には省略し、半導体基板１上に第１窒化シリコン膜３を形成してもよい。 The first silicon oxide film 2 can be formed by thermal oxidation or the like, and is preferably formed with a thickness of 2 to 20 nm, for example, a thickness of 10 nm. Thermal oxidation can be performed by heat-treating the semiconductor substrate 1 at 800 to 1100 ° C. The first silicon nitride film 3 is preferably formed with a thickness of 50 nm to 150 nm, for example, a thickness of 100 nm. The first silicon nitride film 3 can be formed by LPCVD (low pressure chemical vapor deposition) or the like, and this LPCVD is performed at a temperature of 750 ° C. using SiH 2 CL 2 and NH 3 as source gases, for example. Can do. The first silicon oxide film 2 may be omitted if unnecessary, and the first silicon nitride film 3 may be formed on the semiconductor substrate 1.

次に、第１窒化シリコン膜３及び第１酸化シリコン膜２を順次パターニングして、半導体基板１に素子分離用トレンチ５形成のための窓を有する第１酸化シリコン膜２及び第１窒化シリコン膜３を含むパターンＰを形成する。さらに、パターンＰをマスクとして用いて半導体基板１をエッチングして半導体基板１に素子分離用トレンチ５を形成し、図１（ｂ）に示す構造を得る。   Next, the first silicon nitride film 3 and the first silicon oxide film 2 are sequentially patterned, and the first silicon oxide film 2 and the first silicon nitride film having windows for forming the element isolation trench 5 in the semiconductor substrate 1. 3 is formed. Further, the semiconductor substrate 1 is etched using the pattern P as a mask to form element isolation trenches 5 in the semiconductor substrate 1 to obtain the structure shown in FIG.

第１窒化シリコン膜３及び第１酸化シリコン膜２のパターニングは、第１窒化シリコン膜３の上にレジストパターン４を形成し、レジストパターン４をエッチングマスクとし、第１窒化シリコン膜３、第１酸化シリコン膜２を順次エッチングすることによって行うことができる。第１酸化シリコン膜２のエッチングは、レジストパターン４をマスクとして行ってもよいし、パターニングされた第１窒化シリコン膜３をマスクとして行ってもよい。   The first silicon nitride film 3 and the first silicon oxide film 2 are patterned by forming a resist pattern 4 on the first silicon nitride film 3 and using the resist pattern 4 as an etching mask. This can be done by sequentially etching the silicon oxide film 2. The etching of the first silicon oxide film 2 may be performed using the resist pattern 4 as a mask, or may be performed using the patterned first silicon nitride film 3 as a mask.

レジストパターン４は、第１窒化シリコン膜３の上に、レジスト膜を塗布し、このレジスト膜を露光現像することにより形成することができる。レジストパターン４は、素子形成領域（活性領域）１ａ上に形成され、その窓（すなわち、開口部）が素子分離領域を画定する。   The resist pattern 4 can be formed by applying a resist film on the first silicon nitride film 3 and exposing and developing the resist film. The resist pattern 4 is formed on the element formation region (active region) 1a, and its window (that is, opening) defines an element isolation region.

第１窒化シリコン膜３及び第１酸化シリコン膜２のエッチングは、例えばＣＦ4、ＣＨＦ3、Ａｒ、Ｏ2の混合ガスをエッチングガスとして用いて行なうことができる。半導体基板１のエッチングは、例えばＣｌ2、Ｏ2の混合ガスをエッチングガスとして用いて行なうことができる。半導体基板１は、１６０〜４００ｎｍ、例えば深さ３００ｎｍエッチングされ、トレンチ５が形成される。 Etching of the first silicon nitride film 3 and the first silicon oxide film 2 can be performed using, for example, a mixed gas of CF 4 , CHF 3 , Ar, and O 2 as an etching gas. Etching of the semiconductor substrate 1 can be performed using, for example, a mixed gas of Cl 2 and O 2 as an etching gas. The semiconductor substrate 1 is etched to 160 to 400 nm, for example, a depth of 300 nm, and the trench 5 is formed.

レジストパターン４は、第１窒化シリコン膜３をエッチングした後に除去してもよく、第１酸化シリコン膜２又は半導体基板１をエッチングした後に除去してもよい。半導体基板１のエッチングの際にレジストパターン４が残っていても、半導体基板１は、パターンＰに従ってエッチングされるので、この場合も、パターンＰをマスクとして用いていることになる。   The resist pattern 4 may be removed after the first silicon nitride film 3 is etched, or may be removed after the first silicon oxide film 2 or the semiconductor substrate 1 is etched. Even if the resist pattern 4 remains when the semiconductor substrate 1 is etched, the semiconductor substrate 1 is etched according to the pattern P. In this case as well, the pattern P is used as a mask.

２．第２酸化シリコン膜、第２窒化シリコン膜形成工程（工程（ｂ））
図１（ｃ），（ｄ）に示すように、この工程では、トレンチ５内に露出したシリコン基板１表面に第２酸化シリコン膜６を形成し、更に第２酸化シリコン膜６及びパターンＰ表面に第２窒化シリコン膜７を形成する。この工程は、具体的には、以下のように実施することができる。
まず、トレンチ５内に露出したシリコン基板１表面に第２酸化シリコン膜６を形成し、図１（ｃ）に示す構造を得る。 2. Step of forming second silicon oxide film and second silicon nitride film (step (b))
As shown in FIGS. 1C and 1D, in this step, a second silicon oxide film 6 is formed on the surface of the silicon substrate 1 exposed in the trench 5, and the second silicon oxide film 6 and the surface of the pattern P are further formed. Then, a second silicon nitride film 7 is formed. Specifically, this step can be performed as follows.
First, the second silicon oxide film 6 is formed on the surface of the silicon substrate 1 exposed in the trench 5 to obtain the structure shown in FIG.

第２酸化シリコン膜６は、熱酸化などにより形成することができ、厚さ１〜２０ｎｍ、例えば厚さ１０ｎｍで形成することが好ましい。熱酸化は、半導体基板１を８００〜１１００℃で熱処理することによって行うことができる。第２酸化シリコン膜６は、不要な場合には省略することもできる。   The second silicon oxide film 6 can be formed by thermal oxidation or the like, and is preferably formed with a thickness of 1 to 20 nm, for example, a thickness of 10 nm. Thermal oxidation can be performed by heat-treating the semiconductor substrate 1 at 800 to 1100 ° C. The second silicon oxide film 6 can be omitted if unnecessary.

次に、得られた基板を覆うように第２窒化シリコン膜７を形成し、図１（ｄ）に示す構造を得る。第２窒化シリコン膜７によって、第２酸化シリコン膜６及び前記パターンＰ表面が覆われる。   Next, a second silicon nitride film 7 is formed so as to cover the obtained substrate, and the structure shown in FIG. The second silicon nitride film 7 covers the second silicon oxide film 6 and the surface of the pattern P.

第２窒化シリコン膜７は、厚さ５ｎｍ〜５０ｎｍ、例えば厚さ２０ｎｍで形成することが好ましい。第２窒化シリコン膜７は、ＬＰＣＶＤ等により形成することができ、このＬＰＣＶＤは、例えばソースガスとしてＳｉＨ2ＣＬ2とＮＨ3を用い、温度７５０℃で行うことができる。 The second silicon nitride film 7 is preferably formed with a thickness of 5 nm to 50 nm, for example, a thickness of 20 nm. The second silicon nitride film 7 can be formed by LPCVD or the like, and this LPCVD can be performed at a temperature of 750 ° C. using SiH 2 CL 2 and NH 3 as source gases, for example.

第２窒化シリコン膜７は、引張応力を有しており、後で形成する第３酸化シリコン膜８ａが熱処理によって収縮して半導体基板１の素子形成領域１ａに与える圧縮応力を緩和する。この機能を十分に発揮させるために、第２窒化シリコン膜７は、その応力値が０．５〜２ＧＰａとなるように形成することが好ましい。第２窒化シリコン膜７によって素子形成領域１ａに加わる圧縮応力が緩和され、圧縮応力によるドレイン電流の低下が抑えられる。第２窒化シリコン膜７が加工されて、窒化シリコン膜ライナーとなる。   The second silicon nitride film 7 has a tensile stress, and the third silicon oxide film 8a to be formed later contracts due to heat treatment to relieve the compressive stress applied to the element formation region 1a of the semiconductor substrate 1. In order to sufficiently exhibit this function, the second silicon nitride film 7 is preferably formed so that the stress value thereof is 0.5 to 2 GPa. The compressive stress applied to the element formation region 1a is relaxed by the second silicon nitride film 7, and a decrease in drain current due to the compressive stress is suppressed. The second silicon nitride film 7 is processed to become a silicon nitride film liner.

３．第３酸化シリコン膜形成工程（工程（ｃ））
次に、第２窒化シリコン膜７を覆い、トレンチ５の途中の深さで埋め込みを終えるように第３酸化シリコン膜８ａを異方性の成膜法によって形成し、図１（ｅ）に示す構造を得る。 3. Third silicon oxide film forming step (step (c))
Next, a third silicon oxide film 8a is formed by an anisotropic film-forming method so as to cover the second silicon nitride film 7 and finish filling at a depth in the middle of the trench 5, as shown in FIG. Get the structure.

第３酸化シリコン膜８ａは、異方性の成膜法によって形成される。異方性の成膜法を用いることにより、トレンチ５側壁上部に形成される第３酸化シリコン膜８ａの膜厚を薄くすることができ、後工程において第２窒化シリコン膜７を露出させやすいからである。   The third silicon oxide film 8a is formed by an anisotropic film forming method. By using an anisotropic film forming method, the thickness of the third silicon oxide film 8a formed on the upper side wall of the trench 5 can be reduced, and the second silicon nitride film 7 can be easily exposed in a later process. It is.

第３酸化シリコン膜８ａは、好ましくは、トレンチ５を埋め込む深さが半導体基板１表面下１ｎｍ〜１００ｎｍ（好ましくは５ｎｍ〜１５ｎｍ）となるように形成される。例えば、トレンチ深さが３００ｎｍの場合、トレンチ５内での第３酸化シリコン膜８ａの厚さは、２００〜２９９ｎｍ（好ましくは２８５ｎｍ〜２９５ｎｍ）とすることが好ましい。このとき、第３酸化シリコン膜８ａは異方性の成膜法によって形成されるので、トレンチ５側壁での厚さを薄くすることができ、成膜条件を適宜調節することにより、例えば、厚さ１ｎｍ〜６０ｎｍにすることができる。   The third silicon oxide film 8a is preferably formed so that the depth in which the trench 5 is buried is 1 nm to 100 nm (preferably 5 nm to 15 nm) below the surface of the semiconductor substrate 1. For example, when the trench depth is 300 nm, the thickness of the third silicon oxide film 8a in the trench 5 is preferably 200 to 299 nm (preferably 285 nm to 295 nm). At this time, since the third silicon oxide film 8a is formed by an anisotropic film formation method, the thickness on the sidewall of the trench 5 can be reduced, and by adjusting the film formation conditions as appropriate, for example, the thickness The thickness can be 1 nm to 60 nm.

異方性の成膜法としては、ＨＤＰ−ＣＶＤ法（高密度プラズマ化学気相成長法）や、塗布系の成膜法が挙げられる。ＨＤＰ−ＣＶＤ法は、ＩＣＰ（誘導結合プラズマ）やＥＣＲ（電子サイクロトロン共鳴）によるプラズマ等の高密度プラズマを用いた方法である（それぞれ、「ＩＣＰ−ＣＶＤ法」、「ＥＣＲ−ＣＶＤ法」と呼ぶ。）。この方法によれば、成膜と同時にＡｒ，Ｈｅ，Ｈ2等のガスによるスパッタエッチングが行われるので、異方性の成膜が可能である。 Examples of the anisotropic film formation method include an HDP-CVD method (high density plasma chemical vapor deposition method) and a coating system film formation method. The HDP-CVD method is a method using high-density plasma such as plasma by ICP (inductively coupled plasma) or ECR (electron cyclotron resonance) (referred to as “ICP-CVD method” and “ECR-CVD method”, respectively). .) According to this method, since sputter etching is performed with a gas such as Ar, He, H 2 or the like simultaneously with film formation, anisotropic film formation is possible.

ＨＤＰ−ＣＶＤ法による第３酸化シリコン膜８ａの成膜は、例えば、ソースガスとしてＳｉＨ4とＯ2とＨｅの混合ガス、又はＳｉＨ4とＯ2とＨ2の混合ガスを用いて行うことができる。一例として、ＩＣＰ−ＣＶＤ法による場合の成膜条件を以下に示す。
・ガス種／流量：ＳｉＨ4／３０〜１８０ｓｃｃｍ，Ｏ2／８０〜５００ｓｃｃｍ，Ｈｅ／０〜５００ｓｃｃｍ
・低周波プラズマ（２００〜６００Ｈｚ）［成膜する為のプラズマ］：１０００〜５０００Ｗ
・高周波プラズマ（５〜３０ＭＨｚ）［エッチングする為のプラズマ］：５００〜３０００Ｗ The third silicon oxide film 8a is formed by the HDP-CVD method, for example, using a mixed gas of SiH 4 , O 2, and He or a mixed gas of SiH 4 , O 2, and H 2 as a source gas. it can. As an example, film forming conditions in the case of ICP-CVD are shown below.
Gas species / flow rate: SiH 4 / 30~180sccm, O 2 / 80~500sccm, He / 0~500sccm
Low frequency plasma (200 to 600 Hz) [Plasma for film formation]: 1000 to 5000 W
・ High frequency plasma (5 to 30 MHz) [plasma for etching]: 500 to 3000 W

４．第２窒化シリコン膜露出工程（工程（ｄ））
次に、第３酸化シリコン膜８ａを等方性エッチングし、トレンチ５側壁上部の第２窒化シリコン膜７が露出するまで除去し、図２（ｆ）に示す構造を得る。「等方性エッチング」とは、基板表面に水平な方向にも実用的な速度で進行する性質のエッチングを意味しており、水平方向と垂直方向の進行速度が完全に一致する性質のエッチングには限定されない。 4). Second silicon nitride film exposure step (step (d))
Next, the third silicon oxide film 8a is isotropically etched and removed until the second silicon nitride film 7 on the upper side wall of the trench 5 is exposed to obtain the structure shown in FIG. “Isotropic etching” means etching with the property of proceeding at a practical speed even in the direction horizontal to the substrate surface. Etching with the property of completely matching the traveling speed in the horizontal and vertical directions. Is not limited.

工程（ｃ）でトレンチ５側壁に第３酸化シリコン膜８ａが比較的薄い膜厚で形成されており、トレンチ５下部は第３酸化シリコン膜８ａが埋め込まれているので、第３酸化シリコン膜８ａを等方性エッチングすることによって、トレンチ５側壁上部の第２窒化シリコン膜７が露出する。等方性エッチングは、例えば、半導体基板１表面から、深さ５０ｎｍ〜１５０ｎｍまでの範囲、例えば深さ５０ｎｍまでの範囲において第２窒化シリコン膜７が露出するまで行う。   In the step (c), the third silicon oxide film 8a is formed on the sidewall of the trench 5 with a relatively thin film thickness, and the third silicon oxide film 8a is buried in the lower part of the trench 5, so that the third silicon oxide film 8a Isotropically etched to expose the second silicon nitride film 7 on the upper side wall of the trench 5. The isotropic etching is performed, for example, from the surface of the semiconductor substrate 1 until the second silicon nitride film 7 is exposed in a depth range of 50 nm to 150 nm, for example, a depth range of 50 nm.

等方性エッチングは、ウエットエッチングで行っても、ドライエッチングで行ってもよいが、ウエットエッチングが好ましい。
ウエットエッチングは、一例として、以下の条件で行うことができる。
・エッチング液：希フッ酸
・エッチング時間：８０秒
ドライエッチングは、一例として、以下の条件で行うことができる。
・ＲＦ−Ｐｏｗｅｒ：３００〜１２００Ｗ
・真空度：３０〜１２０Ｐａ
・ガス種／流量：ＣＦ4／１５０〜４００ｓｃｃｍ，Ｏ2／１５０〜４００ｓｃｃｍ，Ｎ2／３０〜１５０ｓｃｃｍ The isotropic etching may be performed by wet etching or dry etching, but is preferably wet etching.
As an example, the wet etching can be performed under the following conditions.
Etching solution: Dilute hydrofluoric acid Etching time: 80 seconds As an example, dry etching can be performed under the following conditions.
・ RF-Power: 300-1200W
・ Vacuum degree: 30-120 Pa
Gas species / flow rate: CF 4 / 150~400sccm, O 2 / 150~400sccm, N 2 / 30~150sccm

本工程での第３酸化シリコン膜８ａのエッチングは、工程（ｃ）での第３酸化シリコン膜８ａの形成に用いる装置と同一の装置を用いて連続的に行うことが好ましい。例えば、ＩＣＰ−ＣＶＤ装置を工程（ｃ）で示した成膜条件で動作させることによって第３酸化シリコン膜８ａを形成し、その後、本工程の上記ドライエッチング条件で同一の装置を動作させることによって、装置から基板を取り出すことなく、連続的に、第３酸化シリコン膜８ａの形成とエッチングを行うことができる。   The etching of the third silicon oxide film 8a in this step is preferably performed continuously using the same apparatus as that used for forming the third silicon oxide film 8a in the step (c). For example, the third silicon oxide film 8a is formed by operating the ICP-CVD apparatus under the film forming conditions shown in the step (c), and then the same apparatus is operated under the dry etching conditions in this step. The third silicon oxide film 8a can be continuously formed and etched without removing the substrate from the apparatus.

５．露出した第２窒化シリコン膜の除去工程（工程（ｅ））
次に、露出した第２窒化シリコン膜７をエッチングして除去し、図２（ｇ）に示す構造を得る。第２窒化シリコン膜７が除去される範囲は、工程（ｄ）での第３酸化シリコン膜８ａの等方性エッチング量を制御することによって、制御可能である。第２窒化シリコン膜７は、好ましくは、半導体基板１表面から深さ５０ｎｍ〜１５０ｎｍまでの範囲において除去される。 5. Step of removing exposed second silicon nitride film (step (e))
Next, the exposed second silicon nitride film 7 is removed by etching to obtain the structure shown in FIG. The range in which the second silicon nitride film 7 is removed can be controlled by controlling the amount of isotropic etching of the third silicon oxide film 8a in the step (d). The second silicon nitride film 7 is preferably removed in a range from the surface of the semiconductor substrate 1 to a depth of 50 nm to 150 nm.

本工程は、通常、等方性エッチングによって行われるが、酸化シリコンと実質的に反応しないエッチングガスを用いた異方性エッチングによって行ってもよい。   This step is usually performed by isotropic etching, but may be performed by anisotropic etching using an etching gas that does not substantially react with silicon oxide.

等方性エッチングは、ウエットエッチングで行っても、ドライエッチングで行ってもよいが、ウエットエッチングが好ましい。ウエットエッチングは、加熱燐酸（Ｈ3ＰＯ4）などによって行うことができる。
ドライエッチングは、一例として、以下の条件で行うことができる。以下に示す条件では、第３酸化シリコン膜８ａと第２窒化シリコン膜７の両方のドライエッチングが可能である。
・ＲＦ−Ｐｏｗｅｒ：２０００〜５０００Ｗ
・真空度：３０〜６００Ｐａ
・ガス種／流量：ＮＦ3／５００〜２０００ｓｃｃｍ，Ｏ2／５０〜５００ｓｃｃｍ The isotropic etching may be performed by wet etching or dry etching, but is preferably wet etching. The wet etching can be performed with heated phosphoric acid (H 3 PO 4 ) or the like.
As an example, dry etching can be performed under the following conditions. Under the conditions shown below, dry etching of both the third silicon oxide film 8a and the second silicon nitride film 7 is possible.
・ RF-Power: 2000-5000W
・ Vacuum degree: 30 to 600 Pa
Gas species / flow rate: NF 3 / 500~2000sccm, O 2 / 50~500sccm

本工程での第２窒化シリコン膜７のエッチングは、工程（ｃ）での第３酸化シリコン膜８ａの形成と、工程（ｄ）での第３酸化シリコン膜８ａのエッチングに用いた装置と同一の装置を用いて連続的に行うことが好ましい。例えば、ＩＣＰ−ＣＶＤ装置を工程（ｃ）で示した成膜条件で動作させることによって第３酸化シリコン膜８ａを形成し、その後、本工程の上記ドライエッチング条件で同一の装置を動作させることによって、装置から基板を取り出すことなく、連続的に、第３酸化シリコン膜８ａの形成とエッチング、及び第２窒化シリコン膜７のエッチングを行うことができる。   The etching of the second silicon nitride film 7 in this step is the same as the apparatus used for forming the third silicon oxide film 8a in the step (c) and etching the third silicon oxide film 8a in the step (d). It is preferable to carry out continuously using the apparatus. For example, the third silicon oxide film 8a is formed by operating the ICP-CVD apparatus under the film forming conditions shown in the step (c), and then the same apparatus is operated under the dry etching conditions in this step. The third silicon oxide film 8a can be formed and etched, and the second silicon nitride film 7 can be continuously etched without removing the substrate from the apparatus.

６．第４酸化シリコン膜形成工程（工程（ｆ））
次に、トレンチ５を埋め込むように第４酸化シリコン膜８ｂを形成し、図２（ｈ）に示す構造を得る。第４酸化シリコン膜８ｂは、第３酸化シリコン膜８ａと同じ方法で、厚さ１００〜４００ｎｍ、例えば２５０ｎｍで形成することができる。別の観点では、第４酸化シリコン膜８ｂは、トレンチ５上方での第４酸化シリコン膜８ｂの表面が半導体基板１の表面よりも高い位置になるように形成され、好ましくは、第１窒化シリコン膜３上の第２窒化シリコン膜７の表面よりも高い位置になるように形成される。この場合、後工程での第４酸化シリコン膜８ｂの平坦化が行いやすいからである。 6). Fourth silicon oxide film forming step (step (f))
Next, a fourth silicon oxide film 8b is formed so as to fill the trench 5, and a structure shown in FIG. The fourth silicon oxide film 8b can be formed with a thickness of 100 to 400 nm, for example, 250 nm by the same method as the third silicon oxide film 8a. In another aspect, the fourth silicon oxide film 8b is formed such that the surface of the fourth silicon oxide film 8b above the trench 5 is higher than the surface of the semiconductor substrate 1, and preferably, the first silicon nitride film It is formed to be higher than the surface of the second silicon nitride film 7 on the film 3. In this case, it is easy to flatten the fourth silicon oxide film 8b in a later step.

７．第４酸化シリコン膜平坦化工程（工程（ｇ））
次に、第２窒化シリコン膜７又は第１窒化シリコン膜３をストッパとして、第４酸化シリコン膜を平坦化させ、図２（ｉ）に示す構造を得る。通常は、第２窒化シリコン膜７がストッパとなるが、本工程の前に第２窒化シリコン膜７を別工程によって除去している場合や、本工程で平坦化を過剰に行って第２窒化シリコン膜７が除去される場合などには、第１窒化シリコン膜３がストッパとなる。 7). Fourth silicon oxide film planarization step (step (g))
Next, using the second silicon nitride film 7 or the first silicon nitride film 3 as a stopper, the fourth silicon oxide film is planarized to obtain the structure shown in FIG. Normally, the second silicon nitride film 7 serves as a stopper. However, when the second silicon nitride film 7 is removed by another process before this process, or when the second silicon nitride film 7 is excessively planarized in this process. When the silicon film 7 is removed, the first silicon nitride film 3 serves as a stopper.

平坦化は、ＣＭＰ（化学的機械研磨）によって行うことができる。ＣＭＰは、酸化シリコン膜に対する研磨速度（研磨による膜厚減少速度）が、窒化シリコン膜に対する研磨速度よりも大きくなる条件で行う。ＣＭＰは、例えば、酸化シリコンまたは酸化セリウムを砥粒とする研磨剤を用いて行うことができる。
平坦化は、ＣＭＰ以外の方法、例えば、ＲＩＥエッチングによるエッチバックにより、行ってもよい。 Planarization can be performed by CMP (Chemical Mechanical Polishing). CMP is performed under the condition that the polishing rate for the silicon oxide film (the film thickness reduction rate due to polishing) is higher than the polishing rate for the silicon nitride film. CMP can be performed using, for example, a polishing agent having silicon oxide or cerium oxide as abrasive grains.
The planarization may be performed by a method other than CMP, for example, etch back by RIE etching.

本工程の前又は後に、９００〜１１００℃例えば１０００℃、３０分のアニールを行い、第３及び第４酸化シリコン膜８ａ，８ｂを緻密化する工程を備えてもよい。   Before or after this step, annealing may be performed at 900 to 1100 ° C., for example, 1000 ° C. for 30 minutes, to densify the third and fourth silicon oxide films 8a and 8b.

８．第２及び第１窒化シリコン膜除去工程（工程（ｈ））
次に、第２及び第１窒化シリコン膜７，３、又は第１窒化シリコン膜３をエッチングして除去し、図２（ｊ）に示す構造を得る。本工程では、通常は、第２及び第１窒化シリコン膜７，３を除去するが、本工程以前の工程で第２窒化シリコン膜７を既に除去している場合には、第１窒化シリコン膜３を除去する。 8). Second and first silicon nitride film removing step (step (h))
Next, the second and first silicon nitride films 7 and 3 or the first silicon nitride film 3 are removed by etching to obtain the structure shown in FIG. In this step, the second and first silicon nitride films 7 and 3 are usually removed. However, if the second silicon nitride film 7 has already been removed in the step before this step, the first silicon nitride film is removed. 3 is removed.

エッチングは、加熱燐酸（Ｈ3ＰＯ4）を用いて行うことができる。なお、トレンチ５の側壁下部に形成された第２窒化シリコン膜７は、第４酸化シリコン膜８ｂで覆われているのでエッチングされない。従って、第２窒化シリコン膜７がエッチングされることによる凹部の発生は防止される。 Etching can be performed using heated phosphoric acid (H 3 PO 4 ). Note that the second silicon nitride film 7 formed under the sidewall of the trench 5 is not etched because it is covered with the fourth silicon oxide film 8b. Therefore, the formation of a recess due to the etching of the second silicon nitride film 7 is prevented.

以上で、本実施形態のトレンチ素子分離領域の形成を完了する。この後、半導体基板上に種々の半導体素子を形成することによって、半導体装置を製造することができる。
上記実施形態から１又は複数個の特徴を適宜抜き出して、単独で又は組み合わせて、本発明に採用することができる。 Thus, the formation of the trench element isolation region of this embodiment is completed. Thereafter, a semiconductor device can be manufactured by forming various semiconductor elements on the semiconductor substrate.
One or more features can be appropriately extracted from the above-described embodiment, and can be used alone or in combination in the present invention.

実際に本発明の方法、背景技術に示した方法を用いてトレンチ素子分離領域を形成した。第２窒化シリコン膜７の厚さは、２０ｎｍとした。
幅１μｍの素子分離領域及び幅０．１８μｍの素子分離領域の、トレンチ５側壁上部での第２窒化シリコン膜７の除去深さは、それぞれ、表１のようになった。

Figure 2007173383
表１により、本発明によれば、素子分離領域の幅の違いによる除去深さのばらつきを減少させることができることが分かる。 Actually, the trench element isolation region was formed by using the method of the present invention and the method shown in the background art. The thickness of the second silicon nitride film 7 was 20 nm.
Table 1 shows the removal depth of the second silicon nitride film 7 in the upper portion of the sidewall of the trench 5 in the element isolation region having a width of 1 μm and the element isolation region having a width of 0.18 μm.
Figure 2007173383
 From Table 1, it can be seen that according to the present invention, the variation in the removal depth due to the difference in the width of the element isolation region can be reduced.

（ａ）〜（ｅ）は、本発明の一実施形態のトレンチ素子分離領域の形成工程を示す断面図である。(A)-(e) is sectional drawing which shows the formation process of the trench element isolation region of one Embodiment of this invention. （ｆ）〜（ｊ）は、本発明の一実施形態のトレンチ素子分離領域の形成工程を示す断面図である。(F)-(j) is sectional drawing which shows the formation process of the trench element isolation region of one Embodiment of this invention.

符号の説明Explanation of symbols

１：半導体基板 １ａ：素子形成領域 ２：第１酸化シリコン膜 ３：第１窒化シリコン膜 ４：レジストパターン ５：素子分離用トレンチ ６：第２酸化シリコン膜 ７：第２窒化シリコン膜 ８ａ：第３酸化シリコン膜 ８ｂ：第４酸化シリコン膜 Ｐ：素子分離用トレンチ形成用パターン 1: Semiconductor substrate 1a: Element formation region 2: First silicon oxide film 3: First silicon nitride film 4: Resist pattern 5: Element isolation trench 6: Second silicon oxide film 7: Second silicon nitride film 8a: First Silicon oxide film 8b: Fourth silicon oxide film P: Element isolation trench formation pattern

Claims (10)

（ａ）半導体基板に素子分離用トレンチ形成のための窓を有する第１酸化シリコン膜及び第１窒化シリコン膜を含むパターンをマスクとして、半導体基板をエッチングして素子分離用トレンチを形成する工程と、
（ｂ）前記トレンチ内に露出したシリコン基板表面に第２酸化シリコン膜を形成し、更に第２酸化シリコン膜及び前記パターン表面に第２窒化シリコン膜を形成する工程と、
（ｃ）第２窒化シリコン膜を覆い、前記トレンチの途中の深さで埋め込みを終えるように第３酸化シリコン膜を異方性の成膜法によって形成する工程と、
（ｄ）第３酸化シリコン膜を等方性エッチングし、トレンチ側壁上部の第２窒化シリコン膜が露出するまで除去する工程と、
（ｅ）露出した第２窒化シリコン膜をエッチングして除去する工程と、
（ｆ）前記トレンチを埋め込むように第４酸化シリコン膜を形成する工程と、
（ｇ）第２又は第１窒化シリコン膜をストッパとして、第４酸化シリコン膜を平坦化する工程と、
（ｈ）第２及び第１窒化シリコン膜、又は第１窒化シリコン膜をエッチングして除去してトレンチ素子分離領域を形成する工程とを含むことを特徴とするトレンチ素子分離領域の形成方法。 (A) forming a trench for element isolation by etching the semiconductor substrate using a pattern including a first silicon oxide film and a first silicon nitride film having a window for forming a trench for element isolation in the semiconductor substrate as a mask; ,
(B) forming a second silicon oxide film on the silicon substrate surface exposed in the trench, and further forming a second silicon oxide film and a second silicon nitride film on the pattern surface;
(C) covering the second silicon nitride film and forming a third silicon oxide film by an anisotropic film-forming method so as to finish filling at a middle depth of the trench;
(D) a step of isotropically etching the third silicon oxide film and removing the second silicon nitride film on the upper side wall of the trench until the second silicon nitride film is exposed;
(E) etching and removing the exposed second silicon nitride film;
(F) forming a fourth silicon oxide film so as to fill the trench;
(G) planarizing the fourth silicon oxide film using the second or first silicon nitride film as a stopper;
(H) forming a trench element isolation region by etching and removing the second and first silicon nitride films or the first silicon nitride film, and forming a trench element isolation region. 工程（ｃ）において、第３酸化シリコン膜は、前記トレンチを埋め込む深さが半導体基板表面下１ｎｍ〜１００ｎｍとなるように形成される請求項１に記載の方法。 2. The method according to claim 1, wherein in step (c), the third silicon oxide film is formed so that a depth of embedding the trench is 1 nm to 100 nm below the surface of the semiconductor substrate. 工程（ｃ）において、第３酸化シリコン膜は、トレンチ側壁での厚さが１ｎｍ〜６０ｎｍになるように形成される請求項１に記載の方法。 2. The method according to claim 1, wherein in step (c), the third silicon oxide film is formed to have a thickness of 1 nm to 60 nm on a trench side wall. 工程（ｅ）において、第２窒化シリコン膜は、半導体基板表面から深さ５０ｎｍ〜１５０ｎｍまでの範囲において除去される請求項１に記載の方法。 2. The method according to claim 1, wherein in step (e), the second silicon nitride film is removed in a range from a surface of the semiconductor substrate to a depth of 50 nm to 150 nm. 工程（ｃ）において、異方性の成膜法は、ＨＤＰ−ＣＶＤ法である請求項１に記載の方法。 The method according to claim 1, wherein in step (c), the anisotropic film formation method is an HDP-CVD method. 工程（ｇ）において、第４酸化シリコン膜の平坦化は、化学的機械的研磨によって行われる請求項１に記載の方法。 The method according to claim 1, wherein in step (g), the planarization of the fourth silicon oxide film is performed by chemical mechanical polishing. 工程（ｄ）での第３酸化シリコン膜のエッチングは、工程（ｃ）での第３酸化シリコン膜の形成に用いる装置と同一の装置を用いて連続的に行う請求項１に記載の方法。 2. The method according to claim 1, wherein the etching of the third silicon oxide film in the step (d) is continuously performed using the same apparatus as that used for forming the third silicon oxide film in the step (c). 工程（ｅ）での第２窒化シリコン膜のエッチングは、工程（ｃ）での第３酸化シリコン膜の形成と、工程（ｄ）での第３酸化シリコン膜のエッチングに用いた装置と同一の装置を用いて連続的に行う請求項１に記載の方法。 The etching of the second silicon nitride film in the step (e) is the same as the apparatus used for forming the third silicon oxide film in the step (c) and etching the third silicon oxide film in the step (d). The method according to claim 1, which is carried out continuously using an apparatus. （ａ）半導体基板をエッチングして素子分離用トレンチを形成する工程と、
（ｂ）得られた基板を覆うように第２窒化シリコン膜を形成する工程と、
（ｃ）第２窒化シリコン膜を覆い、前記トレンチの途中の深さで埋め込みを終えるように第３酸化シリコン膜を異方性の成膜法によって形成する工程と、
（ｄ）第３酸化シリコン膜を等方性エッチングし、トレンチ側壁上部の第２窒化シリコン膜が露出するまで除去する工程と、
（ｅ）露出した第２窒化シリコン膜をエッチングして除去する工程を含むことを特徴とする窒化シリコン膜ライナーの形成方法。 (A) etching the semiconductor substrate to form element isolation trenches;
(B) forming a second silicon nitride film so as to cover the obtained substrate;
(C) covering the second silicon nitride film and forming a third silicon oxide film by an anisotropic film-forming method so as to finish filling at a middle depth of the trench;
(D) a step of isotropically etching the third silicon oxide film and removing the second silicon nitride film on the upper side wall of the trench until the second silicon nitride film is exposed;
(E) A method of forming a silicon nitride film liner, including a step of removing the exposed second silicon nitride film by etching. 請求項１〜９に記載の方法を用いた半導体装置の製造方法。 A method for manufacturing a semiconductor device using the method according to claim 1.
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Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012506149A (en) * 2008-10-16 2012-03-08 アプライド マテリアルズ インコーポレイテッド Improved gap filling using low etch rate dielectric liners.
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8741778B2 (en) 2010-12-14 2014-06-03 Applied Materials, Inc. Uniform dry etch in two stages
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US8771536B2 (en) 2011-08-01 2014-07-08 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299582B2 (en) 2013-11-12 2016-03-29 Applied Materials, Inc. Selective etch for metal-containing materials
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139858A (en) * 1989-10-25 1991-06-14 Sony Corp Manufacture of semiconductor device and bias ecrcvd apparatus therefor
JP2002203895A (en) * 2000-12-08 2002-07-19 Samsung Electronics Co Ltd Method for forming trench element isolation film
JP2005251973A (en) * 2004-03-04 2005-09-15 Fujitsu Ltd Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139858A (en) * 1989-10-25 1991-06-14 Sony Corp Manufacture of semiconductor device and bias ecrcvd apparatus therefor
JP2002203895A (en) * 2000-12-08 2002-07-19 Samsung Electronics Co Ltd Method for forming trench element isolation film
JP2005251973A (en) * 2004-03-04 2005-09-15 Fujitsu Ltd Semiconductor device and manufacturing method thereof

Cited By (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012506149A (en) * 2008-10-16 2012-03-08 アプライド マテリアルズ インコーポレイテッド Improved gap filling using low etch rate dielectric liners.
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US8741778B2 (en) 2010-12-14 2014-06-03 Applied Materials, Inc. Uniform dry etch in two stages
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US8771536B2 (en) 2011-08-01 2014-07-08 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US9012302B2 (en) 2011-09-26 2015-04-21 Applied Materials, Inc. Intrench profile
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9093390B2 (en) 2013-03-07 2015-07-28 Applied Materials, Inc. Conformal oxide dry etch
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US9184055B2 (en) 2013-03-15 2015-11-10 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9153442B2 (en) 2013-03-15 2015-10-06 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9093371B2 (en) 2013-03-15 2015-07-28 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9991134B2 (en) 2013-03-15 2018-06-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9209012B2 (en) 2013-09-16 2015-12-08 Applied Materials, Inc. Selective etch of silicon nitride
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9299582B2 (en) 2013-11-12 2016-03-29 Applied Materials, Inc. Selective etch for metal-containing materials
US9711366B2 (en) 2013-11-12 2017-07-18 Applied Materials, Inc. Selective etch for metal-containing materials
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch

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