JP2007173383A - Method for forming trench element separation region, method for forming silicon nitride film liner, and manufacturing method of semiconductor device - Google Patents

Method for forming trench element separation region, method for forming silicon nitride film liner, and manufacturing method of semiconductor device Download PDF

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JP2007173383A
JP2007173383A JP2005366726A JP2005366726A JP2007173383A JP 2007173383 A JP2007173383 A JP 2007173383A JP 2005366726 A JP2005366726 A JP 2005366726A JP 2005366726 A JP2005366726 A JP 2005366726A JP 2007173383 A JP2007173383 A JP 2007173383A
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silicon nitride
forming
nitride film
trench
silicon oxide
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Takahiro Kotabe
隆宏 小田部
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Sharp Corp
シャープ株式会社
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<P>PROBLEM TO BE SOLVED: To provide a method of forming a trench element separation region capable of easily and precisely removing a nitride silicon film liner at the upper part of a trench side wall. <P>SOLUTION: The nitride silicon film liner at the upper part of the trench side wall is removed by the method including (a) a process for forming an element separation trench by etching a semiconductor substrate, (b) a process for forming a second nitride silicon film to cover the acquired substrate, (c) a process for forming a third oxide silicon film by anisotropic film forming method so that the second nitride silicon film is covered and embedding is completed at the depth in the middle of the trench, (d) a process for isotropic etching with a third oxide silicon film so that the second nitride silicon film at the upper part of the trench side wall is exposed, and (e) a process for removing the exposed second nitride silicon film by etching. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for forming a trench element isolation region, a method for forming a silicon nitride film liner, and a method for manufacturing a semiconductor device.

Conventionally, the following method is known as a method for forming a trench element isolation region (see, for example, Patent Document 1).
(A) Using a pattern including a first silicon nitride film having a window for forming an isolation trench on the semiconductor substrate as a mask, the semiconductor substrate is etched to form an isolation trench.
(B) A second silicon nitride film is formed so as to cover the inner wall of the trench.
(C) forming a first silicon oxide film so as to cover the second silicon nitride film and completely fill the trench;
(D) The first silicon oxide film is etched and removed until the second silicon nitride film on the trench sidewall is exposed.
(E) The exposed second silicon nitride film is removed by etching.
(F) A second silicon oxide film is formed so as to fill the trench.
(G) Chemical mechanical polishing of the second silicon oxide film using the first silicon nitride film as a stopper.
(H) The exposed first silicon nitride film is removed by etching.

  Through the above steps, a trench element isolation region having the second silicon nitride film on the inner wall of the trench is obtained. The second silicon nitride film has a function of relieving compressive stress applied to the element formation region by contraction of the first silicon oxide film in the trench. Because of this function, the silicon nitride film formed on the inner wall of the trench is called a silicon nitride film liner.

In the above method, the silicon nitride film liner made of the second silicon nitride film is removed at the upper portion of the trench side wall. This is because when the silicon nitride film liner is formed on the entire trench inner wall, the first surface on the substrate surface is removed. This is because when the silicon nitride film is removed, a part of the silicon nitride film liner is also removed to form a recess.
JP 2004-207564 A

  In order to avoid the formation of recesses, the silicon nitride film liner is removed at the upper portion of the trench sidewall. However, if the removal depth of the silicon nitride film liner (the length of the removed portion from the substrate surface) varies, element formation is performed. The magnitude of the stress applied to the region varies, and as a result, the magnitude of the drain current when the transistor is formed in the element formation region varies. Therefore, it is desired to reduce the variation in the removal depth of the silicon nitride film liner.

  The present invention has been made in view of such circumstances, and provides a method for forming a trench element isolation region capable of easily and accurately removing a silicon nitride film liner on an upper portion of a trench sidewall. .

Means for Solving the Problems and Effects of the Invention

  A method for forming a trench element isolation region according to the present invention includes: (a) using a pattern including a first silicon oxide film and a first silicon nitride film having a window for forming an element isolation trench in a semiconductor substrate as a mask; (B) forming a second silicon oxide film on the surface of the silicon substrate exposed in the trench, and further forming a second silicon nitride film on the second silicon oxide film and the pattern surface. A step of forming a film; and (c) a step of forming a third silicon oxide film by an anisotropic film formation method so as to cover the second silicon nitride film and finish filling at a depth in the middle of the trench; (D) a step of isotropically etching the third silicon oxide film to remove it until the second silicon nitride film on the trench sidewall is exposed; and (e) the exposed second silicon nitride film. Removing the film by etching; (f) forming a fourth silicon oxide film so as to fill the trench; and (g) a fourth silicon oxide film using the second or first silicon nitride film as a stopper. And (h) a step of etching and removing the second and first silicon nitride films or the first silicon nitride film to form a trench element isolation region.

  The inventors filled the trench with a third silicon oxide film halfway by an anisotropic film formation method (step (c)), and isotropically etched the third silicon oxide film, thereby It has been found that the third silicon oxide film can be removed to expose the silicon nitride film on the trench sidewall (step (d)), and the present invention has been completed.

  Since the third silicon oxide film is embedded at a depth in the middle of the trench, the amount of film formation can be reduced as compared with the method of Patent Document 1. In addition, the etching amount of the third silicon oxide film can be reduced. Therefore, according to the present invention, materials and time required for film formation / etching can be reduced.

Further, according to the present invention, the following two types of variations can be reduced for the third silicon oxide film.
(1) Variation due to pattern density In film formation by the HDPCVD method or the like, generally, the deposition rate of a film is large in a dense (narrow) pattern portion and small in a sparse (wide) pattern portion. On the other hand, the etching rate is generally less affected by pattern density. Therefore, as the thickness of the film to be formed increases, the difference in the thickness of the film remaining after etching increases between the dense pattern portion and the sparse pattern portion. In the present invention, since the third silicon oxide film is embedded at a depth in the middle of the trench, the amount of film formation is smaller than in the case of Patent Document 1. Therefore, according to the present invention, the difference (variation) in the thickness of the film remaining after etching between the dense pattern portion and the sparse pattern portion can be reduced.
(2) In-plane variation It is extremely difficult to perform film formation and etching strictly and uniformly over the entire substrate surface, and usually a certain variation occurs in both film formation and etching. This variation increases as the film formation amount and the etching amount increase. According to the present invention, both the amount of film formation and the etching amount of the third silicon oxide film can be reduced as compared with the case of Patent Document 1. Therefore, according to the present invention, in-plane variation can be reduced.

  When the variation in the thickness of the third silicon oxide film after etching decreases, the variation in the removal amount (removal depth) of the silicon nitride liner made of the second silicon nitride film on the trench sidewall also decreases. Therefore, according to the present invention, the silicon nitride film liner can be formed with high accuracy.

  According to another aspect of the present invention, (a) a step of etching a semiconductor substrate to form an element isolation trench, (b) a step of forming a second silicon nitride film so as to cover the obtained substrate, (C) a step of covering the second silicon nitride film and forming a third silicon oxide film by an anisotropic film forming method so as to finish filling at a mid-depth of the trench; and (d) a third silicon oxide film. A silicon nitride film liner comprising: isotropically etching the film and removing the second silicon nitride film on the trench sidewalls until the second silicon nitride film is exposed; and (e) etching and removing the exposed second silicon nitride film. A forming method is provided. The description of the method for forming the trench element isolation region in this specification is basically applicable to the method for forming the silicon nitride film liner.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are used for convenience of explanation, and the scope of the present invention is not limited to the embodiments shown in the drawings. In addition, film formation and etching methods and conditions and various dimensions in the following description are examples, and are not limited to those shown here.

1. Element isolation trench formation step (step (a))
As shown in FIGS. 1A and 1B, in this step, a pattern including a first silicon oxide film 2 and a first silicon nitride film 3 having a window for forming an element isolation trench 5 in a semiconductor substrate 1. Using P as a mask, the semiconductor substrate 1 is etched to form element isolation trenches 5. Specifically, this step can be performed as follows.
First, the first silicon oxide film 2 and the first silicon nitride film 3 are sequentially formed on the semiconductor substrate 1 to obtain the structure shown in FIG.

  The semiconductor substrate 1 is made of a silicon substrate or the like, and in the present embodiment, the description will be given by taking the case where the semiconductor substrate 1 is a silicon substrate as an example, but the etching gas or the like is appropriately changed even when another type of substrate is used. Thus, the present invention can be implemented.

The first silicon oxide film 2 can be formed by thermal oxidation or the like, and is preferably formed with a thickness of 2 to 20 nm, for example, a thickness of 10 nm. Thermal oxidation can be performed by heat-treating the semiconductor substrate 1 at 800 to 1100 ° C. The first silicon nitride film 3 is preferably formed with a thickness of 50 nm to 150 nm, for example, a thickness of 100 nm. The first silicon nitride film 3 can be formed by LPCVD (low pressure chemical vapor deposition) or the like, and this LPCVD is performed at a temperature of 750 ° C. using SiH 2 CL 2 and NH 3 as source gases, for example. Can do. The first silicon oxide film 2 may be omitted if unnecessary, and the first silicon nitride film 3 may be formed on the semiconductor substrate 1.

  Next, the first silicon nitride film 3 and the first silicon oxide film 2 are sequentially patterned, and the first silicon oxide film 2 and the first silicon nitride film having windows for forming the element isolation trench 5 in the semiconductor substrate 1. 3 is formed. Further, the semiconductor substrate 1 is etched using the pattern P as a mask to form element isolation trenches 5 in the semiconductor substrate 1 to obtain the structure shown in FIG.

  The first silicon nitride film 3 and the first silicon oxide film 2 are patterned by forming a resist pattern 4 on the first silicon nitride film 3 and using the resist pattern 4 as an etching mask. This can be done by sequentially etching the silicon oxide film 2. The etching of the first silicon oxide film 2 may be performed using the resist pattern 4 as a mask, or may be performed using the patterned first silicon nitride film 3 as a mask.

  The resist pattern 4 can be formed by applying a resist film on the first silicon nitride film 3 and exposing and developing the resist film. The resist pattern 4 is formed on the element formation region (active region) 1a, and its window (that is, opening) defines an element isolation region.

Etching of the first silicon nitride film 3 and the first silicon oxide film 2 can be performed using, for example, a mixed gas of CF 4 , CHF 3 , Ar, and O 2 as an etching gas. Etching of the semiconductor substrate 1 can be performed using, for example, a mixed gas of Cl 2 and O 2 as an etching gas. The semiconductor substrate 1 is etched to 160 to 400 nm, for example, a depth of 300 nm, and the trench 5 is formed.

  The resist pattern 4 may be removed after the first silicon nitride film 3 is etched, or may be removed after the first silicon oxide film 2 or the semiconductor substrate 1 is etched. Even if the resist pattern 4 remains when the semiconductor substrate 1 is etched, the semiconductor substrate 1 is etched according to the pattern P. In this case as well, the pattern P is used as a mask.

2. Step of forming second silicon oxide film and second silicon nitride film (step (b))
As shown in FIGS. 1C and 1D, in this step, a second silicon oxide film 6 is formed on the surface of the silicon substrate 1 exposed in the trench 5, and the second silicon oxide film 6 and the surface of the pattern P are further formed. Then, a second silicon nitride film 7 is formed. Specifically, this step can be performed as follows.
First, the second silicon oxide film 6 is formed on the surface of the silicon substrate 1 exposed in the trench 5 to obtain the structure shown in FIG.

  The second silicon oxide film 6 can be formed by thermal oxidation or the like, and is preferably formed with a thickness of 1 to 20 nm, for example, a thickness of 10 nm. Thermal oxidation can be performed by heat-treating the semiconductor substrate 1 at 800 to 1100 ° C. The second silicon oxide film 6 can be omitted if unnecessary.

  Next, a second silicon nitride film 7 is formed so as to cover the obtained substrate, and the structure shown in FIG. The second silicon nitride film 7 covers the second silicon oxide film 6 and the surface of the pattern P.

The second silicon nitride film 7 is preferably formed with a thickness of 5 nm to 50 nm, for example, a thickness of 20 nm. The second silicon nitride film 7 can be formed by LPCVD or the like, and this LPCVD can be performed at a temperature of 750 ° C. using SiH 2 CL 2 and NH 3 as source gases, for example.

  The second silicon nitride film 7 has a tensile stress, and the third silicon oxide film 8a to be formed later contracts due to heat treatment to relieve the compressive stress applied to the element formation region 1a of the semiconductor substrate 1. In order to sufficiently exhibit this function, the second silicon nitride film 7 is preferably formed so that the stress value thereof is 0.5 to 2 GPa. The compressive stress applied to the element formation region 1a is relaxed by the second silicon nitride film 7, and a decrease in drain current due to the compressive stress is suppressed. The second silicon nitride film 7 is processed to become a silicon nitride film liner.

3. Third silicon oxide film forming step (step (c))
Next, a third silicon oxide film 8a is formed by an anisotropic film-forming method so as to cover the second silicon nitride film 7 and finish filling at a depth in the middle of the trench 5, as shown in FIG. Get the structure.

  The third silicon oxide film 8a is formed by an anisotropic film forming method. By using an anisotropic film forming method, the thickness of the third silicon oxide film 8a formed on the upper side wall of the trench 5 can be reduced, and the second silicon nitride film 7 can be easily exposed in a later process. It is.

  The third silicon oxide film 8a is preferably formed so that the depth in which the trench 5 is buried is 1 nm to 100 nm (preferably 5 nm to 15 nm) below the surface of the semiconductor substrate 1. For example, when the trench depth is 300 nm, the thickness of the third silicon oxide film 8a in the trench 5 is preferably 200 to 299 nm (preferably 285 nm to 295 nm). At this time, since the third silicon oxide film 8a is formed by an anisotropic film formation method, the thickness on the sidewall of the trench 5 can be reduced, and by adjusting the film formation conditions as appropriate, for example, the thickness The thickness can be 1 nm to 60 nm.

Examples of the anisotropic film formation method include an HDP-CVD method (high density plasma chemical vapor deposition method) and a coating system film formation method. The HDP-CVD method is a method using high-density plasma such as plasma by ICP (inductively coupled plasma) or ECR (electron cyclotron resonance) (referred to as “ICP-CVD method” and “ECR-CVD method”, respectively). .) According to this method, since sputter etching is performed with a gas such as Ar, He, H 2 or the like simultaneously with film formation, anisotropic film formation is possible.

The third silicon oxide film 8a is formed by the HDP-CVD method, for example, using a mixed gas of SiH 4 , O 2, and He or a mixed gas of SiH 4 , O 2, and H 2 as a source gas. it can. As an example, film forming conditions in the case of ICP-CVD are shown below.
Gas species / flow rate: SiH 4 / 30~180sccm, O 2 / 80~500sccm, He / 0~500sccm
Low frequency plasma (200 to 600 Hz) [Plasma for film formation]: 1000 to 5000 W
・ High frequency plasma (5 to 30 MHz) [plasma for etching]: 500 to 3000 W

4). Second silicon nitride film exposure step (step (d))
Next, the third silicon oxide film 8a is isotropically etched and removed until the second silicon nitride film 7 on the upper side wall of the trench 5 is exposed to obtain the structure shown in FIG. “Isotropic etching” means etching with the property of proceeding at a practical speed even in the direction horizontal to the substrate surface. Etching with the property of completely matching the traveling speed in the horizontal and vertical directions. Is not limited.

  In the step (c), the third silicon oxide film 8a is formed on the sidewall of the trench 5 with a relatively thin film thickness, and the third silicon oxide film 8a is buried in the lower part of the trench 5, so that the third silicon oxide film 8a Isotropically etched to expose the second silicon nitride film 7 on the upper side wall of the trench 5. The isotropic etching is performed, for example, from the surface of the semiconductor substrate 1 until the second silicon nitride film 7 is exposed in a depth range of 50 nm to 150 nm, for example, a depth range of 50 nm.

The isotropic etching may be performed by wet etching or dry etching, but is preferably wet etching.
As an example, the wet etching can be performed under the following conditions.
Etching solution: Dilute hydrofluoric acid Etching time: 80 seconds As an example, dry etching can be performed under the following conditions.
・ RF-Power: 300-1200W
・ Vacuum degree: 30-120 Pa
Gas species / flow rate: CF 4 / 150~400sccm, O 2 / 150~400sccm, N 2 / 30~150sccm

  The etching of the third silicon oxide film 8a in this step is preferably performed continuously using the same apparatus as that used for forming the third silicon oxide film 8a in the step (c). For example, the third silicon oxide film 8a is formed by operating the ICP-CVD apparatus under the film forming conditions shown in the step (c), and then the same apparatus is operated under the dry etching conditions in this step. The third silicon oxide film 8a can be continuously formed and etched without removing the substrate from the apparatus.

5. Step of removing exposed second silicon nitride film (step (e))
Next, the exposed second silicon nitride film 7 is removed by etching to obtain the structure shown in FIG. The range in which the second silicon nitride film 7 is removed can be controlled by controlling the amount of isotropic etching of the third silicon oxide film 8a in the step (d). The second silicon nitride film 7 is preferably removed in a range from the surface of the semiconductor substrate 1 to a depth of 50 nm to 150 nm.

  This step is usually performed by isotropic etching, but may be performed by anisotropic etching using an etching gas that does not substantially react with silicon oxide.

The isotropic etching may be performed by wet etching or dry etching, but is preferably wet etching. The wet etching can be performed with heated phosphoric acid (H 3 PO 4 ) or the like.
As an example, dry etching can be performed under the following conditions. Under the conditions shown below, dry etching of both the third silicon oxide film 8a and the second silicon nitride film 7 is possible.
・ RF-Power: 2000-5000W
・ Vacuum degree: 30 to 600 Pa
Gas species / flow rate: NF 3 / 500~2000sccm, O 2 / 50~500sccm

  The etching of the second silicon nitride film 7 in this step is the same as the apparatus used for forming the third silicon oxide film 8a in the step (c) and etching the third silicon oxide film 8a in the step (d). It is preferable to carry out continuously using the apparatus. For example, the third silicon oxide film 8a is formed by operating the ICP-CVD apparatus under the film forming conditions shown in the step (c), and then the same apparatus is operated under the dry etching conditions in this step. The third silicon oxide film 8a can be formed and etched, and the second silicon nitride film 7 can be continuously etched without removing the substrate from the apparatus.

6). Fourth silicon oxide film forming step (step (f))
Next, a fourth silicon oxide film 8b is formed so as to fill the trench 5, and a structure shown in FIG. The fourth silicon oxide film 8b can be formed with a thickness of 100 to 400 nm, for example, 250 nm by the same method as the third silicon oxide film 8a. In another aspect, the fourth silicon oxide film 8b is formed such that the surface of the fourth silicon oxide film 8b above the trench 5 is higher than the surface of the semiconductor substrate 1, and preferably, the first silicon nitride film It is formed to be higher than the surface of the second silicon nitride film 7 on the film 3. In this case, it is easy to flatten the fourth silicon oxide film 8b in a later step.

7). Fourth silicon oxide film planarization step (step (g))
Next, using the second silicon nitride film 7 or the first silicon nitride film 3 as a stopper, the fourth silicon oxide film is planarized to obtain the structure shown in FIG. Normally, the second silicon nitride film 7 serves as a stopper. However, when the second silicon nitride film 7 is removed by another process before this process, or when the second silicon nitride film 7 is excessively planarized in this process. When the silicon film 7 is removed, the first silicon nitride film 3 serves as a stopper.

Planarization can be performed by CMP (Chemical Mechanical Polishing). CMP is performed under the condition that the polishing rate for the silicon oxide film (the film thickness reduction rate due to polishing) is higher than the polishing rate for the silicon nitride film. CMP can be performed using, for example, a polishing agent having silicon oxide or cerium oxide as abrasive grains.
The planarization may be performed by a method other than CMP, for example, etch back by RIE etching.

  Before or after this step, annealing may be performed at 900 to 1100 ° C., for example, 1000 ° C. for 30 minutes, to densify the third and fourth silicon oxide films 8a and 8b.

8). Second and first silicon nitride film removing step (step (h))
Next, the second and first silicon nitride films 7 and 3 or the first silicon nitride film 3 are removed by etching to obtain the structure shown in FIG. In this step, the second and first silicon nitride films 7 and 3 are usually removed. However, if the second silicon nitride film 7 has already been removed in the step before this step, the first silicon nitride film is removed. 3 is removed.

Etching can be performed using heated phosphoric acid (H 3 PO 4 ). Note that the second silicon nitride film 7 formed under the sidewall of the trench 5 is not etched because it is covered with the fourth silicon oxide film 8b. Therefore, the formation of a recess due to the etching of the second silicon nitride film 7 is prevented.

Thus, the formation of the trench element isolation region of this embodiment is completed. Thereafter, a semiconductor device can be manufactured by forming various semiconductor elements on the semiconductor substrate.
One or more features can be appropriately extracted from the above-described embodiment, and can be used alone or in combination in the present invention.

Actually, the trench element isolation region was formed by using the method of the present invention and the method shown in the background art. The thickness of the second silicon nitride film 7 was 20 nm.
Table 1 shows the removal depth of the second silicon nitride film 7 in the upper portion of the sidewall of the trench 5 in the element isolation region having a width of 1 μm and the element isolation region having a width of 0.18 μm.
From Table 1, it can be seen that according to the present invention, the variation in the removal depth due to the difference in the width of the element isolation region can be reduced.

(A)-(e) is sectional drawing which shows the formation process of the trench element isolation region of one Embodiment of this invention. (F)-(j) is sectional drawing which shows the formation process of the trench element isolation region of one Embodiment of this invention.

Explanation of symbols

1: Semiconductor substrate 1a: Element formation region 2: First silicon oxide film 3: First silicon nitride film 4: Resist pattern 5: Element isolation trench 6: Second silicon oxide film 7: Second silicon nitride film 8a: First Silicon oxide film 8b: Fourth silicon oxide film P: Element isolation trench formation pattern

Claims (10)

  1. (A) forming a trench for element isolation by etching the semiconductor substrate using a pattern including a first silicon oxide film and a first silicon nitride film having a window for forming a trench for element isolation in the semiconductor substrate as a mask; ,
    (B) forming a second silicon oxide film on the silicon substrate surface exposed in the trench, and further forming a second silicon oxide film and a second silicon nitride film on the pattern surface;
    (C) covering the second silicon nitride film and forming a third silicon oxide film by an anisotropic film-forming method so as to finish filling at a middle depth of the trench;
    (D) a step of isotropically etching the third silicon oxide film and removing the second silicon nitride film on the upper side wall of the trench until the second silicon nitride film is exposed;
    (E) etching and removing the exposed second silicon nitride film;
    (F) forming a fourth silicon oxide film so as to fill the trench;
    (G) planarizing the fourth silicon oxide film using the second or first silicon nitride film as a stopper;
    (H) forming a trench element isolation region by etching and removing the second and first silicon nitride films or the first silicon nitride film, and forming a trench element isolation region.
  2. 2. The method according to claim 1, wherein in step (c), the third silicon oxide film is formed so that a depth of embedding the trench is 1 nm to 100 nm below the surface of the semiconductor substrate.
  3. 2. The method according to claim 1, wherein in step (c), the third silicon oxide film is formed to have a thickness of 1 nm to 60 nm on a trench side wall.
  4. 2. The method according to claim 1, wherein in step (e), the second silicon nitride film is removed in a range from a surface of the semiconductor substrate to a depth of 50 nm to 150 nm.
  5. The method according to claim 1, wherein in step (c), the anisotropic film formation method is an HDP-CVD method.
  6. The method according to claim 1, wherein in step (g), the planarization of the fourth silicon oxide film is performed by chemical mechanical polishing.
  7. 2. The method according to claim 1, wherein the etching of the third silicon oxide film in the step (d) is continuously performed using the same apparatus as that used for forming the third silicon oxide film in the step (c).
  8. The etching of the second silicon nitride film in the step (e) is the same as the apparatus used for forming the third silicon oxide film in the step (c) and etching the third silicon oxide film in the step (d). The method according to claim 1, which is carried out continuously using an apparatus.
  9. (A) etching the semiconductor substrate to form element isolation trenches;
    (B) forming a second silicon nitride film so as to cover the obtained substrate;
    (C) covering the second silicon nitride film and forming a third silicon oxide film by an anisotropic film-forming method so as to finish filling at a middle depth of the trench;
    (D) a step of isotropically etching the third silicon oxide film and removing the second silicon nitride film on the upper side wall of the trench until the second silicon nitride film is exposed;
    (E) A method of forming a silicon nitride film liner, including a step of removing the exposed second silicon nitride film by etching.
  10. A method for manufacturing a semiconductor device using the method according to claim 1.
JP2005366726A 2005-12-20 2005-12-20 Method for forming trench element separation region, method for forming silicon nitride film liner, and manufacturing method of semiconductor device Pending JP2007173383A (en)

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