JP2007170822A - Flip-flop and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure that all functional blocks and analog IPs possessed by an LSI continue to be operated during burn-in, without lowering the fault detection rate at shipment test of the LSI. <P>SOLUTION: The flip-flop comprises an input data selection means 118 which selects a data signal or a scan signal as a selection signal; data holding means 124, 130 which hold a reset value, when a reset signal to be input in order to restore the flip-flop 100 to an initial state is active and hold an output signal from the input data selection means in sync with a clock signal, when the reset signal is inactive; and an output data selection means 134 which performs control to output the output signal of the data holding means from a data output terminal 132 during normal operation, and to allow a preset fixed value to be output from the data output terminal and to allow the scan signal to be directly output from a scan output terminal 140 during a scan test. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a flip-flop and a semiconductor integrated circuit including the flip-flop, and more particularly to a flip-flop with a scan function.

  Usually, when shipping LSI (large scale integrated circuit, semiconductor integrated circuit), in addition to ATPG (automatic test pattern generator), function test, DC, AC test, etc. In the test, a burn-in test is performed to improve the reliability level by screening a device including an initial failure that cannot be detected. This burn-in test is one of the screening methods for removing the initial failure of a semiconductor device. The burn-in test imposes severer conditions on the semiconductor device than the conditions normally used for the device (voltage, temperature, time, etc.) to determine the cause of failure. This is a method of removing a faulty product as a defective product by accelerating and emphasizing it. The burn-in test is divided into static burn-in that does not input a clock and dynamic burn-in that activates the inside of an LSI by inputting a clock, but dynamic burn-in is generally performed because it has a higher screening effect. Is done. Hereinafter, the term burn-in refers to dynamic burn-in.

  When burn-in is performed, the activation rate of the internal circuit is an important condition in addition to the burn-in conditions (voltage, temperature, time, etc.) described above. Therefore, when performing burn-in, generally, the activation rate of the internal flip-flop is increased by using the scan chain of the scan test. The circuit structure realized on the LSI employs a synchronous circuit that operates according to a finite number of clocks, except for some special examples. The synchronization circuit is composed of a flip-flop that temporarily holds data in synchronization with the clock edge and a combinational circuit that constitutes logic.

  The most basic flip-flop is composed of a pair of input / output terminals and a clock terminal, and outputs a digital signal input from an input terminal at the rising edge of a digital signal called a clock signal applied to the clock terminal. It has a function of copying to a terminal and holding the digital value until the next rising edge of the clock signal. Currently, in order to support a test facilitating method called scan test, in addition to the above terminals, input from the scan input terminal and the scan enable terminal for inputting the scan input signal that is the test input signal in the scan test Generally, a multiplexer having a function of selecting an input signal to be latched from a data input terminal or a scan input terminal according to a selection signal is added (see, for example, Patent Documents 1 and 2). Here, the scan test is designed so that flip-flops in the circuit can be connected in a chain to operate as a shift register so that large-scale circuits can be tested efficiently and easily. Sometimes this shift function is used to allow the value of each flip-flop to be arbitrarily controlled and observed from the outside.

  FIG. 4 shows an example of the configuration of a conventional flip-flop with a scan function. As shown in FIG. 4, the conventional flip-flop 10 with a scan function scans and enables the data signal D input from the data input terminal 12 or the scan input signal SI input from the scan input terminal 14 as the multiplexer. An input data selection unit 18 that selects and outputs based on the selection signal SE input from the terminal 16 is provided.

  The input data selector 18 is connected to an output terminal SE_n of the inverter INV1 that inverts the selection signal SE input from the scan enable terminal 16 and an output terminal SE_p of the inverter INV2 that inverts the output signal of the inverter INV1. Further, in the input data selection unit 18, the output of the transfer gate TG1 having the data signal D as an input signal and the output of the transfer gate TG2 having the scan input signal SI as an input signal are connected, and control terminals of the transfer gates TG1 and TG2 are connected. Are connected to the output terminal SE_n of the inverter INV1 and the output terminal SE_p of the inverter INV2. With this configuration, the input data selection unit 18 has a function of selecting the data signal D or the scan input signal SI based on the selection signal SE.

  The output signal from the input data selection unit 18 is then synchronized with the clock signal CLK by the first clock control unit 20. The first clock control unit 20 includes an inverter INV5 that inverts an output signal from the input data selection unit 18, a transfer gate TG3 that switches ON / OFF transfer of the output signal of the inverter INV5 in synchronization with the clock signal CLK, It is the structure which has. The transfer gate TG3 is connected to the output terminal CLK_n of the inverter INV3 that inverts the clock signal CLK input from the clock input terminal 22, and the output terminal CLK_p of the inverter INV4 that inverts the output of the inverter INV3. By adopting such a configuration, the first clock control unit 20 outputs the output signal from the input data selection unit 18 in synchronization with the clock signal CLK.

  The output signal of the first clock control unit 20 is then input to the master latch unit 24. The master latch unit 24 forcibly holds the reset value when the reset signal RN input from the reset input terminal 26 is active to return the flip-flop 10 to the initial state, and when the reset signal RN is not active. The output signal from the first clock controller 20 has a function of temporarily holding the output signal in synchronization with the clock signal CLK. The master latch unit 24 includes a NOR circuit NOR1, an inverter INV7 that inverts the output signal of the NOR circuit NOR1, and an output signal of the inverter INV7 that is inserted in series between the output of the inverter INV7 and the input of the NOR NOR1 as a clock signal CLK. And a transfer gate TG4 that switches ON / OFF transfer after synchronization. One input of the NOR circuit NOR1 is connected to the output signal of the inverter INV6 that is an inverted signal of the reset signal RN. The transfer gate TG4 is connected to the output terminal CLK_n of the inverter INV3 that inverts the clock signal CLK, and the inverter INV3. The output terminal CLK_p of the inverter INV4 that inverts the output is connected.

  Thereafter, the output signal of the master latch unit 24 is synchronized with the clock signal CLK by the second clock control unit 28. The second clock control unit 28 includes an inverter INV8 that inverts the output signal of the master latch unit 24 and a transfer gate TG5 that switches the transfer ON / OFF in synchronization with the clock signal CLK. The output terminal CLK_n of the inverter INV3 that inverts the transfer gate master latch lock CLK and the output terminal CLK_p of the inverter INV4 that inverts the output of the inverter INV3 are connected. With this configuration, the second clock control unit 28 outputs the output signal from the master latch unit 24 in synchronization with the clock signal CLK.

  The output signal of the second clock control unit 28 is then input to the slave latch unit 30. The slave latch unit 30 forcibly holds the reset value when the reset signal RN is active, and outputs the output signal from the second clock control unit 28 to the clock signal CLK when the reset signal RN is not active. It has a function of temporarily holding in synchronization. The slave latch unit 30 has a configuration including an inverter INV9 that inverts an output signal of the NOR NOR2 and the NOR NOR2, and a transfer gate TG6 inserted in series between the output of the inverter INV9 and the input of the NOR NOR2. One input of the NOR circuit NOR2 is connected to the output signal of the inverter INV6 that is the inversion of the reset signal RN. The transfer gate TG6 is connected to the output terminal CLK_n of the inverter INV3 that inverts the clock signal CLK and the output of the inverter INV3. Is connected to the output terminal CLK_p of the inverter INV4. The signal output from the slave latch unit 30 is output as output data Q from the output terminal 32.

  Each of the transfer gates TG1 to TG6 has a configuration in which the sources and drains of the PMOS transistor and the NMOS transistor are connected in common, and an inversion control signal is applied to the gate of the PMOS transistor and the gate of the NMOS transistor. Therefore, it operates as a switch.

  Next, the operation of the flip-flop with scan function 10 shown in FIG. 4 will be described. First, when the reset signal RN input from the reset input terminal 26 is input as a low level (hereinafter referred to as L level) signal, the output of the inverter INV6 is set to a high level (hereinafter referred to as H level). The output of the inverter INV6 is fixed, and one input of the NOR circuits NOR1 and NOR2 provided in the master latch unit 24 and the slave latch unit 30 is fixed to the H level. As a result, the outputs of the NOR circuit NOR1 and the NOR circuit NOR2 are fixed to the L level without depending on the values of the clock signal CLK and the data signal D, and output as output data Q via the data output terminal 32. This operation is held until an H level signal is input to the reset signal RN.

  On the other hand, when the reset signal RN input from the reset input terminal 26 is input as an H level (normal operation) signal, the clock signal CLK is first held at the L level. Accordingly, the transfer gate TG3 of the first clock control unit 20 and the transfer gate TG6 of the slave latch unit 30 are held in the ON state, respectively, the transfer gate TG4 of the master latch unit 24, and the transfer gate of the second clock control unit 28. Each TG5 is held in an OFF state.

  In this state, according to the value of the selection signal SE input from the scan enable terminal, if the selection signal SE is at the L level, the transfer gate TG1 of the input data selection unit 18 is in the ON state, the transfer gate Since TG2 is in the OFF state, the data signal D input from the data input terminal 12 becomes the output of the input data selection unit 18 and is input to the first clock control unit 20. In the first clock control unit 20, since the transfer gate TG3 is in the ON state, a level obtained by inverting the input from the input data selection unit 18 by the inverter INV5 is output to the master latch unit 24. The master latch unit 24 outputs the signal input from the first clock control unit 20 to the second clock control unit 28 through the NOR circuit NOR1 in which one input is fixed at the L level. At this time, as described above, since the transfer gate TG4 is in the OFF state, nothing is output. In the second clock control unit 28, nothing is output to the slave latch unit 30 because the transfer gate TG5 is in the OFF state.

  Next, when the clock signal CLK rises, the first clock control unit 20 stops outputting data to the master latch unit 24 because the transfer gate TG3 is turned off. In the master latch unit 24, the transfer gate TG4 is turned on in synchronization with the rising edge of the clock signal CLK, and the output signal of the inverter INV7 is input to the NOR circuit NOR1 whose one input is fixed to the L level via the transfer gate TG4. Therefore, the output signal while the clock signal CLK is at the H level is held.

  On the other hand, the second clock control unit 28 inverts the signal received from the master latch unit 24 and outputs it to the slave latch unit 30 because the transfer gate TG5 is turned ON when the clock signal CLK rises. The slave latch unit 30 inverts the signal received from the second clock control unit 28 by the NOR circuit NOR2 whose one is fixed at the L level and outputs the inverted signal from the output terminal 32.

  Subsequently, when the clock signal CLK falls again, the second clock control unit 28 stops outputting data to the slave latch unit 30 because the transfer gate TG5 is turned off again. In the slave latch unit 30, since the transfer gate TG6 is turned ON and the output of the inverter INV9 is fed back to the input of the NOR circuit NOR2 in which one is fixed at L level, the output signal while the clock signal CLK is at L level is output. Retained.

特開２００５−１６４４３７号公報 特開２００４−０１２３９９号公報 The above-described operation of the conventional flip-flop with a scan function is summarized as a truth table shown in Table 1 below. Here, “X” shown in Table 1 indicates “Don't Care”, and “↑” indicates the rising edge of the clock. Further, “NORMAL” indicates a normal operation time and “SCAN SHIFT” indicates a scan operation.

JP 2005-164437 A JP 2004-012399 A

  In order to eliminate early defective LSIs by the burn-in test, it is necessary to set the above-described burn-in conditions appropriately and to have a high circuit activation rate. However, in recent LSI circuits, in order to reduce power consumption, an enable terminal for inputting a selection signal SE for selecting ON / OFF of the circuit operation is often provided for each functional block provided in the LSI circuit. This enable terminal is provided not only in the functional block but also in an analog IP or the like that is generally an analog circuit that consumes more power than a digital logic circuit, and when such a functional block or analog IP does not need to operate. The power consumption is reduced by preventing the propagation of the clock inside and separating the transistors constituting the logic from the power supply itself.

  At the time of burn-in, in order to increase the activity rate of the internal flip-flop, a random pattern generated outside or inside the LSI is input to the scan chain of the scan test, but the flip-flop that holds the value of the selection signal input to the enable terminal Therefore, the time during which the functional block with the enable terminal or the analog IP is operating is expected to be about half of the total operation time. In other words, there is no guarantee that the functional block and the analog IP block are always operating during the burn-in period. For this reason, there is a possibility that the failure in the initial stage in the functional block and analog IP controlled by the selection signal serving as the enable signal cannot be accelerated and the probability that the initial failure remains in these functional block and analog IP may increase. .

  In order to avoid the above problem, each block is enabled in the burn-in mode in addition to the logic circuit during normal operation, in addition to the logic circuit during normal operation, in each logic block and each flip-flop logic circuit holding an analog IP enable signal. In addition to adding a logic circuit for outputting a value, it is necessary to remove each flip-flop from the scan chain so that the value for enabling each block is not updated in the shift mode of the scan test. In addition, a circuit that does not scan the flip-flop that holds the enable signal, adds a terminal for burn-in, and uses the terminal to hold a value corresponding to the polarity of the enable signal of each block. In addition, the operation of each functional block and analog IP during the burn-in period was guaranteed. However, removing the flip-flop from the scan chain should not be performed because there is a risk of reducing the failure detection rate of the gates before and after the flip-flop. In addition, since it becomes impossible to easily detect a failure after a flip-flop that is not canceled, there is a problem that the failure detection rate is lowered.

  Therefore, the present invention has been made in view of the above-mentioned problems of conventional flip-flops, and the object of the present invention is to provide a data output terminal without providing a new input terminal or logic circuit during a scan test. Can be held at a fixed value of H level or L level, and can operate as a flip-flop with a normal scan function during a scan test, so that it does not affect the failure detection rate of LSI It is another object of the present invention to provide a new and improved flip-flop, and a semiconductor integrated circuit including such a flip-flop.

  In order to solve the above problems, according to an embodiment of the present invention, a data signal from the data input terminal is fetched and latched during normal operation, and a scan signal from the scan input terminal is latched during a scan test. In the flip-flop, when the input data selection means for selecting the data signal or the scan signal based on the selection signal input from the scan enable terminal and the reset signal input to return the flip-flop to the initial state are active Data that holds the reset value forcibly in response to the reset signal and holds the output signal from the input data selection means in synchronization with the clock signal input from the clock input terminal when the reset signal is inactive The holding means and the data signal latched by the data holding means are output. Data output terminal, a scan output terminal that directly outputs the scan signal from the scan input terminal during the scan test, and a data holding means output signal from the data output terminal during normal operation, and a fixed value that is set during the scan test. And a data output terminal, and output data selection means for controlling the scan signal to be directly output from the scan output terminal. A flip-flop is provided.

  With this configuration, control is performed so that a fixed value is output from the data output terminal of the flip-flop during a scan test during burn-in. It is not necessary to add a logic circuit for outputting each functional block or a value for enabling the analog IP to the logic circuit of each flip-flop that holds the enable signal for the analog IP. The trouble of removing each flip-flop from the scan chain can be reduced so that the value for enabling the analog IP is not updated. In other words, the burn-in performed at the time of the shipping test can be efficiently executed, and the shipping of the LSI device including the initial failure can be efficiently prevented.

  At this time, in the above-described embodiment, the output data selection means may be controlled by a data selection signal formed by latching a selection signal input from the scan enable terminal with a reset signal.

  With such a configuration, output data from the data output terminal during normal operation and scan test of the flip-flop can be controlled, so that burn-in performed during LSI shipping test can be performed efficiently.

  In the above-described embodiment, the output data selection unit includes two transfer gates that switch ON / OFF the transfer of the output signal from the data holding unit according to the data selection signal, and one of the transfer gates The transfer gate is provided with a source terminal on the output stage side of the data holding means, and the other transfer gate is provided with a drain terminal so as to be connected between the output stage of one transfer gate and the data output terminal, The fixed value may be set by connecting the source terminal of the other transfer gate to either the ground plane or the power supply voltage.

  By adopting such a configuration, it becomes possible to input a fixed level data signal of either high level or low level to each functional block or analog IP included in the LSI during a scan test. Functional block and analog IP operations can be guaranteed.

  Furthermore, in the above embodiment, the data holding means may use either the rising edge or the falling edge of the clock signal as a trigger.

  By adopting such a configuration, it is possible to perform burn-in performed at the time of LSI shipping test more widely.

  In order to solve the above-described problems, according to another embodiment of the present invention, there is provided a semiconductor integrated circuit characterized in that a synchronous circuit is configured by using the flip-flop of each embodiment described above.

  With such a configuration, it is possible to ensure that all functional blocks and analog IP included in the synchronous circuit continue to operate during burn-in without lowering the failure detection rate of the LSI including the flip-flop.

  At this time, in the above embodiment, the fixed value is set to a high level or a low level during a scan test depending on the polarity of the functional block included in the synchronization circuit operated by the flip-flop and the enable terminal that controls the operation state of the analog IP. A flip-flop that outputs any one of the fixed values may be arranged.

  With such a configuration, the activation rate of the flip-flop included in the synchronous circuit at the time of burn-in can be increased, so that the failure detection rate of the LSI can be prevented from being lowered.

  As described above, according to the present invention, when performing a scan test during burn-in, the output is held at a fixed value of H level or L level without providing a new input terminal, and a normal scan flip-flop is used during the scan test. Even if it operates as a device, it does not affect the failure detection rate at the time of burn-in, so that the burn-in performed at the time of the shipping test can be performed efficiently, and the shipment of the LSI device including the initial failure can be efficiently prevented.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

  First, the configuration of the flip-flop with scan function for burn-in according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a flip-flop with a scan function for burn-in according to the first embodiment of the present invention, in which an L level fixed value is output as output data Q during a scan test. 2 is a circuit diagram showing the configuration of the flip-flop as in FIG. 1, and shows an example in which a fixed value of H level is output as the output data Q during the scan test.

  As shown in FIG. 1, the flip-flop 100 according to the present embodiment includes a signal output from the slave latch unit 130 between the output stage of the slave latch unit 130 and the data output terminal 132, as shown in FIG. The output data selection unit 134 is provided as means for selecting the output signal and the output signal having a fixed value (here, L level is output). Accordingly, the flip-flop 100 according to the present embodiment propagates the selection signal SE input from the scan enable terminal into the flip-flop 100 according to the reset signal RN that latches the selection signal of the output data selection unit 134. A reset control unit 136 that performs output, an output data selection signal latch unit 138 that latches an output data selection signal in accordance with an output signal from the reset control unit 136, and an output signal that is output from the slave latch unit 130 as a scan output signal SO. And a scan output terminal 140.

  Thus, the conventional flip-flop 10 with a scan function shown in FIG. 4 is provided in that an output data selection unit 134, a reset control unit 136, an output data selection signal latch unit 138, and a scan output terminal 140 are additionally provided. And the structure is different. It should be noted that each input terminal 112, 114, 116, 122, 126, data signal D or scan input signal SI is selected based on a selection signal SE input from the scan enable terminal 116. 118, when the reset signal RN inputted to return the flip-flop 100 to the initial state is active, the reset value is forcibly held in response to the reset signal RN, and when the reset signal RN is inactive The first clock control unit 120, the master latch unit 124, the second control clock unit 128 serving as data holding means for holding the output signal of the input data selection unit 118 in synchronization with the clock signal CLK input from the clock input terminal 122, The configuration and operation of the slave latch unit 130 are shown in FIG. Each of the input terminals 12, 14, 16, 22, 26, the data selection unit 18, the first clock control unit 20, the master latch unit 24, the second control clock unit 28, and the slave latch included in the conventional flip-flop 10 with a scanning function. Since it is substantially the same as the part 30, the description is abbreviate | omitted. In other words, the operation of each of the above constituent elements provided in the conventional flip-flop 10 shown in FIG. 4 naturally functions as the basic operation also in the flip-flop 100 according to the present embodiment.

  The output data selection unit 134 includes transfer gates TG17 and TG18 that switch ON / OFF the transfer of the output signal from the slave latch unit 130 according to the output of the reset control unit 136 and the output of the output data selection signal latch unit 138. Among them, the transfer gate TG17 has a source terminal on the output stage side of the slave latch unit 130, and an output signal from the slave latch unit 130 according to the output of the reset control unit 136 and the output of the output data selection signal latch unit 138. Switch the transfer to ON / OFF. On the other hand, the transfer gate TG18 is provided such that the source terminal is grounded (GND) and the drain terminal is connected between the output stage of the transfer gate TG17 and the data output terminal 132. By providing the transfer gate TG18 in this way, the output data Q from the data output terminal 132 when outputting a fixed value is controlled so that the fixed value becomes L level.

  The reset control unit 136 includes a transfer gate TG19 that transfers a selection signal input from the scan enable terminal to the inside of the flip-flop 100 in accordance with the reset signal RN. Therefore, the selection signal SE input from the scan enable terminal according to the reset signal RN that latches the selection signal of the output data selection unit 134 is propagated into the flip-flop 100.

  The output data selection signal latch unit 138 includes an inverter INV20 that inverts the output signal of the reset control unit 136, an inverter INV21 that inverts the output signal of the inverter INV20, and an output between the inverter INV21 and the input stage of the inverter INV20. And a transfer gate TG20 that is inserted in series and switches ON / OFF the transfer of the output signal of the inverter INV21 to the inverter INV20 in response to the reset signal RN. With such a configuration, the output data selection signal to be transmitted to the output data selection unit 134 is latched according to the output signal from the reset control unit 136.

  Next, the operation of the burn-in flip-flop 100 according to this embodiment will be described.

  First, an operation when both the reset signal RN and the selection signal SE are fixed to the L level will be described. At this time, the master latch unit 124 and the slave latch unit 130 hold the input signal at the L level as in the conventional flip-flop 10. In the reset control unit 136, the transfer gate TG19 is turned on, and the selection signal SE input from the scan enable terminal 116 is input to the output data selection signal latch unit 138 while maintaining the L level. Then, the inverter INV20 provided in the output data selection signal latch unit 138 inverts the input L level signal, so that the output is held at the H level. As a result, since the transfer gate TG17 included in the output data selection unit 134 is turned on and the transfer gate TG18 is turned off, an L level signal input from the slave latch unit 130 to the output data selection unit 134 is output from the data output terminal 132. Output as signal Q. In addition, after the reset signal RN is released, the output data selection signal latch unit 138 holds the H level, so that when the clock signal CLK is input, the output data selection signal latch unit 138 becomes a flip-flop that operates as normal.

  Next, an operation when the reset signal RN is fixed at the L level and the selection signal SE is fixed at the H level will be described. At this time, the master latch unit 124 and the slave latch unit 130 hold the input signal at the L level as in the conventional flip-flop. Similar to the operation in the case where both the reset signal RN and the selection signal SE are fixed at the L level, the transfer gate TG19 of the reset control unit 136 is turned on, so that the output data selection signal latch unit 138 includes Since the selection signal SE is input in a state of H level and the selection signal SE is inverted by the inverter INV20, the output of the inverter INV20 maintains the L level. As a result, since the transfer gate TG17 included in the output data selection unit 134 is turned off and the transfer gate TG18 is turned on, the source terminal of the transfer gate TG18 is connected to GND, and the data output terminal is output as the output signal Q whose fixed value is L level. It is output to 132. As the transfer gate TG17 is turned off, the output signal from the slave latch unit 130 is output from the scan output terminal 140 as the scan output signal SO.

  After the reset signal RN is canceled, even if the clock signal CLK is input, the output data selection signal latch unit 138 holds the output data selection signal at the L level, so that the transfer gate TG17 provided in the output data selection unit 134 The transfer gate TG18 is turned on and the output signal Q continues to be output as a fixed value of L level to the data output terminal 132. In other words, by grounding the source terminal of the transfer gate TG18 included in the output data selection unit 134 to GND, the output data Q output from the data output terminal 132 becomes a fixed value of L level.

  On the other hand, as shown in FIG. 2, by connecting the source terminal of the transfer gate TG18 included in the output data selection unit 134 to the power supply voltage (VDD), the output data Q output from the data output terminal 132 is H level. Fixed value. Hereinafter, the operation of the flip-flop 100 according to the present embodiment when the source terminal of the transfer gate TG18 provided in the output data selection unit 134 is connected to the power supply voltage (VDD) will be described with reference to FIG.

  The flip-flop 100 according to the present embodiment has a fixed value that is output when a fixed value is output depending on whether the connection destination of the source terminal of the transfer gate TG18 provided in the output data selection unit 134 is connected to VDD or GND. Is determined to be H level or L level. That is, when outputting a fixed value of H level when outputting a fixed value, the source terminal of the transfer gate TG18 is connected to VDD, and the drain terminal of the transfer gate TG18 is connected between the output stage of the transfer gate TG17 and the data output terminal 132. It is provided so as to be connected between them. By providing the transfer gate TG18 in this way, the output data Q from the data output terminal 132 when outputting a fixed value is controlled so that the fixed value becomes H level.

  Note that the basic operation of the flip-flop 100 shown in FIG. 2 is substantially the same as that of the flip-flop 100 shown in FIG. That is, when both the reset signal RN and the selection signal SE are fixed at the L level, the master latch unit 124 and the slave latch unit 130 hold the input signal at the L level. In the reset control unit 136, the transfer gate TG19 is turned on, and the selection signal SE input from the scan enable terminal 116 is input to the output data selection signal latch unit 138 while maintaining the L level. Then, the inverter INV20 provided in the output data selection signal latch unit 138 inverts the input L level signal, so that the output is held at the H level. As a result, since the transfer gate TG17 included in the output data selection unit 134 is turned on and the transfer gate TG18 is turned off, an L level signal output from the slave latch unit 130 is output as the output signal Q from the data output terminal 132. . In addition, after the reset signal RN is released, the output data selection signal latch unit 138 holds the H level, so that when the clock signal CLK is input, the output data selection signal latch unit 138 becomes a flip-flop that operates as normal.

  Next, when reset signal RN is fixed at L level and selection signal SE is fixed at H level, master latch unit 124 and slave latch unit 130 hold the input signal at L level. Similar to the operation in the case where both the reset signal RN and the selection signal SE are fixed at the L level, the transfer gate TG19 of the reset control unit 136 is turned on, so that the output data selection signal latch unit 138 includes Since the selection signal SE is input in a state of H level and the selection signal SE is inverted by the inverter INV20, the output of the inverter INV20 maintains the L level. As a result, since the transfer gate TG17 included in the output data selection unit 134 is turned off and the transfer gate TG18 is turned on, the source terminal of the transfer gate TG18 is connected to VDD, and the output signal Q having a fixed value of H level is used as the data. Output to the output terminal 132.

  As the transfer gate TG17 is turned off, the output signal from the slave latch unit 130 is output from the scan output terminal 140 as the scan output signal SO. After the reset signal RN is canceled, even if the clock signal CLK is input, the output data selection signal latch unit 138 holds the output data selection signal at the L level, so that the transfer gate TG17 provided in the output data selection unit 134 The transfer gate TG18 is turned on and the output signal Q continues to be output as a fixed value of H level to the data output terminal 132.

  Next, a configuration of a semiconductor integrated circuit using the flip-flop 100 of this embodiment will be described with reference to the drawings. FIG. 3 shows a configuration of a synchronous circuit 200 which is an example of a semiconductor integrated circuit using the flip-flop 100 shown in FIGS. 1 and 2. Here, reference numerals FF_10, FF_11, and FF_14 denote the conventional flip-flop 10 with a scan function shown in FIG. 4, and reference numeral FF_13 denotes the burn-in flip-flop 100 according to the present embodiment at the time of burn-in shown in FIG. In this example, a fixed value of L level is output from the data output terminal 132, and the symbols FF_12 and FF_15 are also the burn-in flip-flop 100 according to the present embodiment, similar to the symbol FF_13, and the burn-in shown in FIG. In this example, a fixed value of H level is sometimes output from the data output terminal 132. The configuration of the semiconductor integrated circuit using the flip-flop 100 of this embodiment is such that the enable terminals ENA1 and ENA2 of the functional blocks 201 and 202 held by the flip-flop included in the circuit and the enable terminal ENA3 of the analog IP 203 are used. It is determined according to the polarity.

  The first functional block 201 is a synchronous circuit in which a clock signal is input to the clock terminal CK1, and includes a Low active enable terminal ENA1. The second functional block 202 is a synchronous circuit in which a clock signal is input to the clock terminal CK2, and includes a high active enable terminal ENA2. The analog IP 203 is an IP block that is not scanned, and includes a high active enable terminal ENA3.

  In FIG. 3, the scan output terminal 140 (SO) is used in connection with the scan chains chain 1 and chain 2 to the next stage of the signs FF_12, FF_13, and FF_15 which are the flip-flops 100 for burn-in according to the present embodiment. Except for this, it is substantially the same as the conventional synchronous circuit. Further, the scan chains chain1 and chain2 constitute separate scan chains, and each flip-flop FF_10, via external flip-flops in the same scan chain from an external scan input terminal (not shown), It is assumed that it is connected to the scan input terminal 114 (SI) of FF_13.

  Assume that the outputs of the flip-flops FF_12 and FF_15 shown in FIG. 3 are connected to the scan input terminal 114 (SI) of the next flip-flop included in the same scan chain chain1 and chain2, respectively. In FIG. 3, the flip-flops FF_10, FF_11, and FF_12 are assigned to the scan chain chain 1 and the flip-flops FF_13, FF_14, and FF_15 are assigned to the scan chain chain 2 for simplification. The assignment is not fixed, and it only needs to belong to one of the chain groups. Further, each flip-flop FF_10, FF_11, FF_12, FF_13, FF_14, FF_15, in addition to the connection by the scan chain chain1 and chain2, is in the control block 204 including these flip-flops FF_10, FF_11, FF_12, FF_13, FF_14, FF_15. Are connected via a combinational circuit COMB1 included in the.

  Next, an operation when the flip-flop 100 according to the present embodiment is applied to the semiconductor integrated circuit 200 will be described. When the burn-in test is performed on the synchronization circuit 200 shown in FIG. 3, first, the selection signal SE, which is a scan enable signal, is set to a high level, and the data input terminal provided in the data selection unit 118 of each flip-flop 100 with a scan function. 112 (D) and the input signal from the scan input terminal 114 (SI) are selected. Thereafter, a clock signal is input to the clock terminal 122 (CK), and a random binary value is input from an external scan input terminal (not shown) (or from an internal random generation circuit), and the scan chains chain 1 and chain 2 All the flip-flops 100 above are operated for a certain period of time. Note that all such operations are performed under the burn-in conditions described above.

  After all the flip-flops 100 on the scan chains chain 1 and chain 2 are operated for a certain period of time, first, the selection signal SE input from the scan enable terminal 116 is made active (H level). The selection signal SE is assumed to hold the active state thereafter. After the selection signal SE is activated, the reset signal RN is activated (L level), and the reset control unit 136 and the output data selection signal latch unit 138 that control the selection signal SE input to the output data selection unit 134 are operated. Let

  After that, even if the reset signal RN is canceled (H level) and the clock signal CLK is input, the output data selection signal latch unit 138 holds the output data selection signal at the L level. And the transfer gate TG18 is turned on, and the output signal Q continues to be output to the data output terminal 132 as a fixed value of H level or L level. In other words, the output data Q output from the data output terminal 132 becomes a fixed value of H level or L level according to the potential of the connection destination of the source terminal of the transfer gate TG18 provided in the output data selection unit 134. As a result, the output data Q of the flip-flops FF_12 and FF_15 that output a fixed value of H level from the data output terminal 132 at the time of burn-in becomes H level, and the analog IP block 203 and the second functional block 202 are always operating. It becomes. Further, the output of the flip-flop FF_13 that outputs a fixed value of L level from the data output terminal 132 at the time of burn-in becomes L level, and the first functional block 201 is in an operating state in the same manner as the other blocks 202 and 203.

  When the scan test is performed, the reset signal RN is not active when the selection signal SE input from the scan enable terminal SE is active, that is, in the scan shift mode. 100 does not affect the performance of the LSI scan test.

  As described above, in the flip-flop 100 according to the present embodiment, the scan output terminal 140 (SO) is received by the reset signal RN input from the reset input terminal 126 and the selection signal SE input from the scan enable terminal 116 during the scan test. The data of the scan input signal SI input to the scan input terminal 114 is directly output, and the output data Q of the data output terminal 132 is output to a fixed value set by the output data selection unit 134.

  Therefore, unlike the conventional flip-flop 10 with a scan function, it is possible to prevent random updating of each functional block included in the semiconductor integrated circuit and the flip-flop holding the analog IP enable signal. Such functional blocks and analog IPs maintain their operating state even during the burn-in period. As a result, it is possible to prevent shipment of LSIs having such defects without accelerating the defects at the initial stage in each functional block and analog IP block as in the prior art. That is, it is possible to ensure that each functional block included in the LSI or the analog IP is operating at the time of burn-in without separately providing a burn-in terminal or circuit and without reducing the failure detection rate of the LSI.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, in the first embodiment described above, a flip-flop in which an output signal is updated using a rising edge of a clock signal as a trigger is described as an example, but the present invention is not limited to such a flip-flop. Naturally, it can be realized by a flip-flop triggered by the falling edge of the clock signal.

  The present invention can be applied to a flip-flop and a semiconductor integrated circuit using the flip-flop, and in particular, can be applied to a flip-flop with a scan function used at the time of burn-in and a semiconductor integrated circuit using the flip-flop.

FIG. 3 is a circuit diagram showing a configuration of a flip-flop with a scan function for burn-in according to the first embodiment of the present invention (Low level output during a scan test). FIG. 2 is a circuit diagram showing a configuration of a flip-flop with a scan function for burn-in (high level output during a scan test) according to the first embodiment of the present invention. 3 is a configuration example of a synchronous circuit using the flip-flop shown in FIGS. 1 and 2. It is a circuit diagram which shows the structure of the flip-flop with a scan function regarding a prior art.

Explanation of symbols

100 Flip-flop 112 Data input terminal 114 Scan input terminal 116 Scan enable terminal 118 Input data selection unit 120 First clock control unit 122 Clock input terminal 124 Master latch unit 126 Reset input terminal 128 Second clock control unit 130 Slave latch unit 132 Data Output terminal 134 Output data selection unit 136 Reset control unit 138 Output data selection signal latch unit 140 Scan output terminal

Claims (6)

In the flip-flop that fetches and latches the data signal from the data input terminal during normal operation, and latches the scan signal from the scan input terminal during the scan test,
Input data selection means for selecting the data signal or the scan signal based on a selection signal input from a scan enable terminal;
When a reset signal input to return the flip-flop to an initial state is active, a reset value is forcibly held in response to the reset signal, and when the reset signal is inactive, the input data Data holding means for holding the output signal from the selection means in synchronization with the clock signal input from the clock input terminal;
A data output terminal for outputting a data signal latched by the data holding means;
A scan output terminal directly outputting the scan signal from the scan input terminal during the scan test;
The output signal of the data holding means is output from the data output terminal during the normal operation, the set fixed value is output from the data output terminal during the scan test, and the scan signal is output directly from the scan output terminal. Output data selection means for controlling so that,
A flip-flop comprising:   2. The flip-flop according to claim 1, wherein the output data selection means is controlled by a data selection signal formed by latching the selection signal input from the scan enable terminal with the reset signal. . The output data selection means includes two transfer gates for switching ON / OFF the transfer of the output signal from the data holding means according to the data selection signal,
One of the transfer gates is provided with a source terminal on the output stage side of the data holding means, and the other transfer gate is provided between the output stage of the one transfer gate and the data output terminal. A drain terminal is provided to be connected,
3. The flip-flop according to claim 1, wherein the fixed value is set by connecting a source terminal provided to the other transfer gate to either a ground plane or a power supply voltage.   The flip-flop according to any one of claims 1 to 3, wherein the data holding means uses a rising edge or a falling edge of the clock signal as a trigger.   A semiconductor integrated circuit comprising a synchronous circuit using the flip-flop according to claim 1. The fixed value is fixed to either a high level or a low level during the scan test according to the polarity of the function block included in the synchronization circuit operated by the flip-flop and the enable terminal that controls the operation state of the analog IP. 6. The semiconductor integrated circuit according to claim 5, wherein the flip-flop that outputs a value is arranged.

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