JP2007166377A - Reconfigurable arithmetic operation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reconfigurable arithmetic operation circuit which consumes low power regardless of arithmetic operations and has suppressed scale of a circuit consuming power. <P>SOLUTION: The reconfigurable arithmetic operation circuit is equipped with a reconfigurable logic circuit 1 including a plurality of PEs 11, a reconfiguration data memory 2, a clock generating section 3, a scheduler 4, and a reconfigurable order circuit 5, wherein the reconfigurable order circuit 5 includes an order circuit 52 and a reconfiguration data memory 51 for the order circuit, and each of the PEs 11 includes a combination circuit 111 and a register 112. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a digital circuit, and more particularly to a reconfigurable arithmetic processing circuit that realizes power saving.

In a reconfigurable logic circuit (reconfigurable logic) in which a circuit can be reconfigured by data from the outside, speeding up and power saving have been studied together with the ease of circuit change, which is the original function.
FIG. 5 is a configuration diagram of a reconfigurable arithmetic processing circuit of the first conventional example.
The reconfigurable arithmetic processing circuit includes a reconfigurable logic circuit 1, a reconfigurable data memory 2, and a clock generation unit 3. The reconfigurable logic circuit 1 includes a plurality of processor elements (hereinafter referred to as PE) 10. It consists of
The clock generation unit 3 supplies a different clock S1 to each PE.
The reconfiguration data memory 2 supplies different reconfiguration data S2 for each PE.
Each PE forms a different circuit based on the reconfiguration data S2.
The clock generation unit 3 is configured to determine and supply a clock frequency suitable for the reconfiguration circuit of each PE when each PE reconfigures the circuit. (For example, refer to Patent Document 1).
In this way, power consumption can be reduced by operating each PE at an optimal clock frequency.

FIG. 6 is a configuration diagram of a reconfigurable arithmetic processing circuit of the second conventional example.
The reconfigurable arithmetic processing circuit includes a reconfigurable logic circuit 1, a reconfigurable data memory 2, a circuit development control unit 30, and a power supply voltage control unit 31.
The reconfigurable logic circuit 1 includes a high threshold voltage transistor region 16 and a low threshold voltage transistor region 15. The high threshold voltage transistor region 16 is used when high speed operation is required, and the low threshold voltage transistor region 15 is used when it is desired to suppress power consumption because the leakage current is small.
Here, when the reconfiguration data S2 is input from the reconfiguration data memory 2, the circuit development control unit 30 determines whether to operate in the low threshold voltage transistor region 15 or the high threshold voltage transistor region 16.
The power supply voltage control unit 31 applies the power supply voltage only to the transistor region to be used in accordance with a command from the circuit development control unit 30.
Specifically, when realizing a high-performance circuit, the circuit is developed in the low threshold voltage transistor region, and the power supply to the high threshold voltage transistor region is shut off. Conversely, when realizing a circuit with reduced power consumption, the circuit is developed in the high threshold voltage transistor region, and the power supply to the low threshold voltage transistor region is shut off. (For example, refer to Patent Document 2).
In this way, the power consumption is reduced by shutting off the power supply in the unused area, and high performance according to the application is realized.
Special table 2004-538675 (page 59, FIG. 1) Japanese Patent Laid-Open No. 2005-5611 (page 14, FIG. 1)

In the conventional example, the power consumption is reduced by operating each PE at an optimal clock frequency or by shutting off the power to a circuit not using the reconfigurable logic circuit. However, there is a problem that power consumption cannot be partially reduced in the corresponding reconfigurable logic circuit.
In the conventional example, a continuous clock is supplied to the reconfigurable logic circuit, and there is a problem that clock gating cannot be optimally controlled. There is also a problem that the scale of the circuit portion that consumes power in the reconfigurable logic circuit cannot be reduced.
The present invention has been made in view of such problems, and can be reconfigured to reduce power consumption not only when the reconfigurable logic circuit is performing arithmetic processing but also when it is not performing arithmetic processing. It is an object to provide a simple arithmetic processing circuit. Furthermore, another object of the present invention is to provide a reconfigurable arithmetic processing circuit capable of suppressing the scale of a circuit portion that consumes power.

In order to solve the above problems, the present invention is configured as follows.
The invention described in claim 1 includes a reconfigurable logic circuit (1) configured by a plurality of processor elements (PE), and a reconfigurable data memory for supplying reconfigurable data to the reconfigurable logic circuit. In a reconfigurable arithmetic processing circuit, an external activation factor is input, a scheduler that generates a clock control signal and a sequential circuit activation signal, and a clock that generates a gated clock by inputting the clock and the clock control signal A reconfigurable sequential circuit that receives the gated clock and the sequential circuit start signal as input and generates a start signal and a selection signal. The reconfigurable sequential circuit includes a sequential circuit and the sequential circuit. A sequential circuit reconfiguration data memory for supplying sequential circuit reconfiguration data, wherein the PE is a combinational circuit and the combination A register for storing the output of the circuit, and the reconfigurable sequential circuit reconfigures the state transition order of the sequential circuit with the reconfiguration data for the sequential circuit and updates a selection signal for each state transition. The reconfigurable logic circuit is activated by the activation signal, reconfigures the connection between the combinational circuit and the PE based on the reconfiguration data selected by the selection signal, and the combinational circuit reconfigures the reconfiguration. When there is no data, the logic output of the combinational circuit is fixed, and the register operates only for a necessary period by the gated clock.
According to a second aspect of the present invention, the combinational circuit determines an input / output association with the reconfiguration data, processes a plurality of input signals according to the association, and outputs when there is no reconfiguration data. A first switch that fixes the logic of the first ALU, an arithmetic circuit is determined based on the content of the reconfiguration data, and the first ALU that performs arithmetic processing using the output of the first switch and the plurality of input signals as inputs, A second switch for determining an input / output association based on the reconfiguration data, processing an output of the first ALU according to the association, and fixing an output logic when there is no reconfiguration data; and the reconfiguration A second ALU that determines an arithmetic circuit based on data contents, receives the output of the first ALU, and outputs a calculation result to the register.
According to a third aspect of the present invention, the switch includes a plurality of output selection units, and the output selection unit performs a logical product operation between the input and the contents of the reconstructed data, and the re-selection unit. A logic unit that determines logic based on the contents of the configuration data, and includes a bit operation element that performs bit operations with the plurality of AND outputs as inputs.
Further, in the invention according to claim 4, the scheduler generates a factor signal according to the activation factor with a plurality of activation factors as inputs, and the clock generator and the reconfigurable sequential circuit include the factor signal. The selected operation is performed.
Further, in the invention according to claim 5, the clock generation unit receives the factor signal to change a clock frequency, the reconfigurable sequential circuit includes a plurality of sequential circuit reconfiguration data memories, The sequential circuit reconfiguration data memory is used as a cause signal to reconfigure the state transition of the sequential circuit and generate a selection signal.

According to the first aspect of the present invention, by fixing the logic output of the combinational circuit of the reconfigurable logic circuit, power consumption due to unnecessary switching operation can be reduced.
Further, since the reconfigurable logic circuit and the reconfigurable sequential circuit can be operated only for a necessary period using the gated clock, power consumption in this circuit can be reduced.
In addition, by controlling the reconfiguration of the reconfigurable logic circuit with the reconfigurable sequential circuit and continuously executing different processes on the same circuit, a large process can be performed with a small circuit, thereby reducing the operating circuit scale. Can do. In addition, the power consumption can be reduced because the portion that consumes power wastefully can be suppressed as compared with the case of executing with a large-scale circuit.
According to the second aspect of the present invention, in the combinational circuit, whether or not the switching operation of the combinational circuit can be performed can be controlled by providing a switch in front of the ALU and fixing the output logic of the switch.
According to a third aspect of the present invention, the switch can be operated or not, which is a request of the third aspect, by enabling the switch to control the switching with the reconfiguration data using AND. In addition, since the AND operation can be masked by the bit arithmetic element, there is an effect equivalent to increasing the number of ALUs.
According to the fourth aspect of the present invention, the scheduler has a plurality of activation factor inputs and a new factor signal output, and can generate different factor signals depending on the types of activation factors. The circuit can be made to perform different operations according to this factor signal.
According to the fifth aspect of the present invention, the clock generator changes the clock frequency according to the contents of the factor signal, the reconfigurable sequential circuit selects the sequential circuit reconfiguration data memory, and the state transition of the sequential circuit is changed. Operations can be performed by generating reconfiguration and selection signals. Therefore, processing suitable for the factor can be executed at a suitable clock frequency, so that optimum power consumption for the system can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a reconfigurable arithmetic processing circuit showing a first embodiment of the present invention.
In FIG. 1, a reconfigurable arithmetic processing circuit includes a reconfigurable logic circuit 1, a reconfigurable data memory 2, a clock generation unit 3, a scheduler 4, a reconfigurable sequential circuit 5, and a CPU 6. The function of each part will be described below.
The reconfigurable logic circuit 1 includes a plurality of PEs 11, and each PE includes a combinational circuit 111 and a register 112. The reconfigurable logic circuit 1 has four PEs in FIG. 1, but may be different from that in FIG.
In the reconfiguration data memory 2, a reconfiguration data area is provided for each PE. In addition, the reconstruction data area for each PE has a plurality of reconstruction data, which are switched and output by a selection signal described later.
The reconfigurable sequential circuit 5 includes a sequential circuit 52 and a sequential circuit reconfiguration data memory 51. The sequential circuit 52 reads the sequential circuit reconfiguration data from the sequential circuit reconfiguration data memory 51 and reconfigures the state transition sequence.
The present invention is different from Patent Documents 1 and 2 in that the switching operation of the clock generator 3, the scheduler 4, the part including the reconfigurable sequential circuit 5, and the combinational circuit in the reconfigurable logic circuit described later is performed. This is the part controlled by the reconstruction data.
The operation of each part will be described below.
The scheduler 4 has a function of managing activation of the reconfigurable sequential circuit 5 and activation of the CPU 6. The scheduler 4 is activated by the activation factor S8. The activation factor S8 is a signal commanded from an output device or the like controlled by the CPU, and serves as a trigger for the entire reconfigurable arithmetic processing circuit. Here, the clock is activated by the activation factor S8 to generate the clock control signal S3 and the sequential circuit activation signal S4.
The clock generation unit 3 generates a gated clock S11 by gating a clock S1 from a clock generator (not shown) with a clock control signal S3.
The reconfigurable sequential circuit 5 receives the sequential circuit activation signal S4 in synchronization with the gated clock S11 and starts operation. First, the sequential circuit 52 reads the data stored in the sequential circuit reconfiguration data memory 51 and reconfigures the state transition order. Subsequently, the sequential circuit 52 performs processing for the first state, outputs selection signals S18a, S6b, S6c, and S6d corresponding to this state, and simultaneously outputs a start signal S6.
Next, the operation of the reconfigurable logic circuit 1 will be described.
The reconfigurable logic circuit 1 first receives the reconfigurable sequential circuit 5 activation signal S6, reads the reconfiguration data S2 selected by the selection signal S18, and reconfigures the circuit of the combinational circuit 111. In this reconfiguration, the connection between the PEs is determined together with the reconfiguration of the combinational circuit 111. Subsequently, arithmetic processing is performed in the reconfigured combinational circuit 111, and the result is stored in the register 112. The reconfigurable logic circuit 1 outputs a response signal S7 when this arithmetic processing is completed.
When receiving the response signal S7, the reconfigurable sequential circuit 5 outputs the sequential circuit response signal S5.
When the scheduler 4 receives the sequential circuit response signal S5, the scheduler 4 determines that one arithmetic processing is completed, and generates a CPU interrupt S10.
When the CPU 6 receives the CPU interrupt S10, the CPU 6 reads the operation result in the reconfigurable logic circuit 1 through the data bus S9. The data bus S9 is also used for accessing the data memory with respect to the reconfigurable sequential circuit 5 and the reconfigurable data memory 2.
The reconfigurable sequential circuit 5 performs processing according to the state transition order after the processing of the first state is completed, and outputs the selection signals S18a, S6b, S6c, S6d updated for each state, and at the same time, the start signal S6. Is output. Here, every time the contents of the selection signals S6a, S6b, S6c, and S6d are changed, the reconfiguration data S2 is switched, and the combinational circuit 111 is reconfigured with the updated reconfiguration data, and the reconfigured circuit is changed. Are processed. In this way, in accordance with an instruction from the reconfigurable sequential circuit 5, the reconfiguration and arithmetic processing of the combinational circuit 111 are repeatedly performed. By continuously executing different processes in the same circuit in this way, a large process can be performed with a small circuit, which has the effect of reducing the operating circuit scale.
On the other hand, by supplying the gated clock S11 from the clock generation unit 3 to the register 112, the operation is performed for a necessary period, so that power consumption can be greatly reduced. Similarly, the power consumption can be reduced by operating the reconfigurable sequential circuit with a gated clock only for a necessary period.

  In the reconfigurable logic circuit 1, when the combinational circuit 111 is not reconfigured, that is, when there is no reconfiguration data S2, the logic output of the combinational circuit 111 is fixed to a certain logic (for example, 0). In the combinational circuit 111, when the input data changes, the output data changes with a delay of the circuit delay. That is, when the input data changes, switching of the transistor elements constituting the circuit occurs, and power is consumed here. Therefore, by fixing the logic output of the combinational circuit 111, power consumption due to unnecessary switching can be suppressed.

FIG. 2 is a block diagram of a combinational circuit showing a second embodiment of the present invention. The combinational circuit shown here is a specific example of PE11 shown in FIG.
In the figure, the combinational circuit includes two switches 1111 and four ALUs 1112, and the register 112 includes two FFs 1113. Here, ALU is an arithmetic logic unit, and FF is an abbreviation for flip-flop. These numbers may be different from those in FIG. Also, the number of inputs and outputs may be different from that in FIG.
The difference between the present invention and Patent Document 1 and Patent Document 2 is that a switch is provided in the previous stage of the ALU and the input / output of this switch is associated using the reconfiguration data, and there is no reconfiguration data. Is to fix the output logic.

The operation of each part will be described below with reference to the drawings.
The switch 1111a performs input / output association according to the reconstruction data S2, and gates four inputs (input 1 to input 4) in accordance with this to generate four outputs. This output is input to ALU 1112a and ALU 1112b.
A switch 1111b is disposed downstream of the ALU 1112a and ALU 1112b, and an ALU 1112c and ALU 1112d are disposed downstream of the switch 1111b. In this way, in the configuration in which the switch and the ALU are continuously arranged, the switch 1111b receives the output of the previous ALU and the inputs 1 to 4 as inputs, and performs input / output association using the reconfiguration data S2. Together, it produces four outputs. This output is input to ALU 1112c and ALU 1112d.
The outputs of ALU 1112c and ALU 1112d are input to FF 1113a and FF 1113b and stored therein.
When there is no reconfiguration data S2, the logical output of both the switch 1111a and the switch 1111b is fixed. Thus, by fixing the logic output, power consumption in this circuit can be suppressed.

FIG. 3 is a block diagram of a switch showing a third embodiment of the present invention. The switch shown here is a specific example of PE11 shown in FIG.
In the figure, the switch 1111 includes a plurality of output selection units 100.
The output selection unit 100 includes a plurality of ANDs 105 (AND operation elements) and bit operation elements 109. The number of inputs to the output selection unit 100 is four, but the number of these may be different from that in FIG.
The present invention differs from Patent Document 1 and Patent Document 2 in that the switch is ANDed and a bit arithmetic element is arranged at the subsequent stage, and the AND output can be fixed according to the contents of the reconfiguration data S2.
Here, the operation will be described below as a representative of the output selection unit 100a.
First, in each AND 105, inputs 1 to 4 are input to one input, reconfiguration data S 2 is input to the other input, and the logical product is output to the bit arithmetic element 109.
Here, when there is no reconstruction data S2, that is, when the input is not used, the output of the AND 105 is fixed to 0. Thereby, power consumption in this circuit can be suppressed.
The bit operation element 109 is configured to take a logical product or a logical sum depending on the contents of the reconfiguration data S2, and the AND output of the previous stage is an input, and the output of the bit operation element 109 is one input of the ALU.
In the bit operation element 109, a function is set by the reconfiguration data and bit operation is performed. Here, it has a mask processing function for a specific bit. Since such processing is a part of the function performed by the ALU, there is an effect equivalent to increasing the ALU by this bit arithmetic element. Also, the overall calculation time can be shortened as compared with the case of using ALU.

  In this way, since the logic output can be fixed according to the contents of the reconfiguration data S2, the switching of the transistors of the combinational circuit 111 can be controlled by applying the switch 1111 to the combinational circuit 111.

FIG. 4 is a configuration diagram of a reconfigurable arithmetic processing circuit according to the fourth embodiment.
4 differs from FIG. 1 as follows. That is, the scheduler 4 processes a plurality of activation factors as inputs, and generates an added factor signal S31. The factor signal S31 is supplied to the clock generation unit 3 and the reconfigurable sequential circuit 5. The reconfigurable sequential circuit 5 includes a plurality of sequential circuit reconfiguration data memories 51, and is selected by the factor signal S31.
In FIG. 4, the number of activation factors is three, but the number of inputs may be different. In FIG. 4, the sequential circuit reconfiguration data memory 51 is four, but it may be different from this.
The part where the present invention is different from Patent Documents 1 and 2 is a part including a scheduler that receives a plurality of activation factors.
The operation of each part will be described below.
When any activation factor is input, the scheduler 4 performs processing according to this and generates a factor signal S31.
The clock generation unit 3 performs control to change the clock frequency according to the content of the factor signal S31. In this variable control of the clock frequency, for example, in the case of an activation factor for executing an arithmetic process that may take a processing time, the gated clock S11 is generated using a clock obtained by ^dividing the clock S1 by 1 / ^2n. To do.
The reconfigurable sequential circuit selects the sequential circuit reconfigurable data memory according to the content of the factor signal S31. Subsequent operations are the same as those in the first embodiment.

  Thus, since the scheduler 4 can control the factor signal by a plurality of activation factors, the clock generation unit controls the clock, or the reconfigurable sequential circuit reconfigures the sequential circuit to change the state transition order, etc. can do. Further, the processing contents can be freely set for each activation factor.

The block diagram of the reconfigurable arithmetic processing circuit which shows 1st Example of this invention The block diagram of the combinational circuit which shows 2nd Example of this invention Configuration diagram of a switch showing a third embodiment of the present invention The block diagram of the reconfigurable arithmetic processing circuit which shows 4th Example of this invention Configuration diagram of reconfigurable arithmetic processing circuit of first conventional example Configuration diagram of reconfigurable arithmetic processing circuit of second conventional example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reconfigurable logic circuit 2 Reconfigurable data memory 3 Clock generation part 4 Scheduler 5 Reconfigurable sequential circuit 51 Reconfigurable data memory for sequential circuits (51a, 51b, 51c)
52 Sequential Circuit 6 CPU
11 Processor Element (PE) (11a, 11b, 11c, 11d)
111 combinational circuits (111a, 111b, 111c, 111d)
112 registers (112a, 112b, 112c, 112d)
1111 switch (1111a, 1111b)
1112 ALU (1112a, 1112b, 1112c, 1112d, 1112e, 1112f)
1113 FF (1113a, 1113b)
100 output selector (100a, 100b)
105 AND (105a, 105b, 105c, 105d)
109 bit arithmetic element 15 low threshold voltage transistor region 16 high threshold voltage transistor region 30 circuit development control unit 31 power supply voltage control unit S1 clock S2 reconfiguration data (S2a, S2b, S2c, S2d)
S3 clock control signal S4 sequential circuit activation signal S5 sequential circuit response signal S6 activation signal S7 response signal S8 activation factor S9 data bus S10 CPU interrupt S11 gated clock S12 input 1
S13 input 2
S14 input 3
S15 input 4
S16 output 1
S17 Output 2
S18 selection signal (S18a, S18b, S18c, S18d)
S31 Factor signal S81 Activation factor 1
S82 Activation factor 2
S83 Activation factor 3

Claims (5)

A reconfigurable logic circuit composed of a plurality of processor elements (hereinafter referred to as PE);
In a reconfigurable arithmetic processing circuit comprising a reconfigurable data memory for supplying reconfigurable data to the reconfigurable logic circuit,
A scheduler that receives an external activation factor as input and generates a clock control signal and a sequential circuit activation signal;
A clock generation unit that receives the clock and the clock control signal and generates a gated clock;
The gated clock and the sequential circuit start signal as inputs, and a reconfigurable sequential circuit that generates a start signal and a selection signal,
The reconfigurable sequential circuit includes a sequential circuit, and a sequential circuit reconfiguration data memory for supplying sequential circuit reconfiguration data to the sequential circuit,
The PE includes a combinational circuit and a register that stores an output of the combinational circuit,
The reconfigurable sequential circuit reconfigures the state transition order of the sequential circuit based on the sequential circuit reconfiguration data, and determines a selection signal to be updated for each state transition,
The reconfigurable logic circuit is activated by the activation signal, and reconfigures the connection between the combinational circuit and the PE by the reconfiguration data selected by the selection signal;
When the combinational circuit has no reconfiguration data, the logic output of the combinational circuit is fixed,
A reconfigurable arithmetic processing circuit, wherein the register operates only for a necessary period by the gated clock. The combinational circuit is
A first switch that determines an input / output association with the reconfiguration data, processes a plurality of input signals according to the association, and fixes an output logic in the absence of the reconfiguration data;
A first ALU that determines an arithmetic circuit based on the contents of the reconstructed data, and performs arithmetic processing using the output of the first switch and the plurality of input signals as inputs;
A second switch for determining an input / output association with the reconfiguration data, processing an output of the first ALU according to the association, and fixing an output logic when there is no reconfiguration data;
A second ALU that determines an arithmetic circuit based on the content of the reconstructed data and performs arithmetic processing using the output of the second switch as an input;
The reconfigurable arithmetic processing circuit according to claim 1, comprising: The switch includes a plurality of output selection units,
The output selection unit is
A plurality of ANDs for performing an AND operation between the input and the contents of the reconstructed data; and
A bit operation element that performs a bit operation using the output of the plurality of ANDs as input, the logic being determined by the content of the reconstructed data;
The reconfigurable arithmetic processing circuit according to claim 3, further comprising:   The scheduler generates a factor signal according to the activation factor with a plurality of activation factors as inputs, and the clock generator and the reconfigurable sequential circuit perform an operation selected by the factor signal. The reconfigurable arithmetic processing circuit according to claim 1.   The clock generation unit receives the factor signal and changes a clock frequency, and the reconfigurable sequential circuit includes a plurality of sequential circuit reconfiguration data memories, and the sequential signal reconfiguration data memory includes the factor signal. 5. The reconfigurable arithmetic processing circuit according to claim 4, wherein the state transition is reconfigured in the sequential circuit and a selection signal is generated.

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