JP2004062281A - Pipeline processor and pipeline operation control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To vary the number of pipeline stages without increasing a circuit scale and dropping a highest operation frequency in a high speed clock. <P>SOLUTION: A pipeline processor is provided with pipeline stages 1, 2, 3, 4, 5 and 6 constituting a variable length pipeline operation circuit which is switched to six stages and three stages by the high speed and low speed clocks and with a control part 7 outputting a control signal SEL switching a system to correspond to an operation mode corresponding to a clock frequency in response to supply of a clock mode signal CM. The pipeline stages 1, 3 and 5 are provided with pipeline registers R1, R2 and R3 switched to a valid or invalid state in response to levels L/H of the control signal SEL. When the control signal SEL is in the L level, the registers R1, R2 and R3 are validated and the processor is operated as the pipeline processor of six stages. When it is in the H level, the registers R1, R2 and R3 are invalidated and the processor is operated as the pipeline processor of three stages. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pipeline arithmetic processing device and a pipeline arithmetic control method, and more particularly, to a pipeline arithmetic processing device and a pipeline arithmetic control method in which the number of pipeline stages is made variable to operate with a high-speed clock and a low-speed clock.
[0002]
[Prior art]
In general, a pipeline arithmetic processing device that operates with a high-speed clock and a low-speed clock is configured to increase the number of pipeline stages in a high-speed clock operation so as to reduce processing for each stage of the pipeline. . However, such an increase in the number of pipeline stages causes a decrease in execution efficiency due to a penalty caused by stopping or initializing the pipeline due to a branch instruction or the like, and in order to suppress this, prediction tables such as branch prediction and preceding execution are required. A high-speed register is required to hold an execution instruction, and a technique that consumes large power and has a complicated circuit is generally indispensable.
[0003]
However, in recent years, when the clock frequency is varied at a low speed in order to reduce power consumption when the load on the processor is reduced, it is necessary to maintain the performance by suppressing a decrease in execution efficiency without using branch prediction or preceding execution. Is required.
[0004]
In order to respond to this demand, for example, the first conventional pipeline arithmetic processing device described in Japanese Patent Application Laid-Open No. 6-83583 is capable of changing the number of pipeline stages according to the variation of the operating clock frequency, and The operation of the high-speed clock by the configuration and the efficiency of instruction execution of the low-speed clock by the short pipeline configuration are compatible.
[0005]
Referring to FIG. 18, which shows a block diagram of a conventional first pipeline arithmetic processing device, this conventional first pipeline arithmetic processing device includes an input-side latch circuit 512-1 and an output circuit of an arithmetic circuit 510-A. , A latch circuit 512-3 for latching the output of the arithmetic circuit 510-B, arithmetic circuits 510-A and 510-B configuring each stage of the pipeline, and supply of a select signal. And a select generation circuit 518 for generating a select signal.
[0006]
Next, the operation of the first conventional pipeline arithmetic processing device will be described with reference to FIG. 18. The select generation circuit 518 outputs an L level select signal when the clock speed is high and an H level select signal when the clock speed is low. Occurs. When the select signal is at the L level, selector 514 connects the output of latch circuit 512-2 to arithmetic circuit 510-B, and latch circuit 512-2 intervenes between arithmetic circuits 510-A and 510-B. It becomes. When the select signal is at the H level, the selector 514 resets the latch circuit 512-2, connects the output of the arithmetic circuit 510-A to the arithmetic circuit 510-B, and sets the latch circuit 512-2 to the through state. When the clock speed is low and the processing of both operations of the arithmetic circuits 510-A and 510-B can be completed within one cycle, the latch circuit 512-2 can be automatically passed through to improve the processing speed.
[0007]
Referring to FIG. 19, which shows a block diagram of a conventional second pipeline arithmetic processing device described in Japanese Patent Application Laid-Open No. 8-147163, this second conventional pipeline arithmetic processing device has an instruction at each stage of the pipeline. Data processing units 613, 614 for performing predetermined data processing on the data processing unit, a plurality of registers 615, 617, 619 for holding processing contents output to each stage of the data processing units 613, 614, and the registers 615, 617, 619 And multiplexers 616, 618, and 620 that constitute bypass paths for bypassing the registers 615, 617, and 619, respectively.
[0008]
Next, the operation of the second conventional pipeline arithmetic processing device will be described with reference to FIG. 19. When the operation clock frequency is in the low clock frequency mode, or when the data processing unit 613 , 614 are monitored, and when the contents held in the register at that time are stably held in the next unit processing time as in the execution of a branch instruction, this is determined and the multiplexer 616, 618, and 620 are controlled, and the corresponding register in the registers 615, 617, and 619 is bypassed by the bypass path.
[0009]
With this configuration, it is possible to reduce the power that is wasted by the processor without lowering the processing performance, and to improve the processing speed by the setup time of the bypassed register.
[0010]
Further, referring to FIG. 20 which shows a block diagram of a third conventional pipeline arithmetic processing device described in Japanese Patent Application Laid-Open No. 9-319578, data processing 71 which is the third conventional pipeline arithmetic processing device includes an instruction fetch processor. A circuit 711, an instruction decoding circuit 712, an instruction execution circuit 713, and a high-speed pitch flag 714 are provided, and the number of stages of pipeline processing is variable to three or four in this example. The pipeline control circuit 7121 of the instruction decoding circuit 712 switches the number of pipeline stages of the instruction execution circuit 713. With this configuration, the upper limit of the operation clock can be improved in the four-stage pipeline processing, so that the processing speed can be increased. On the other hand, in applications where a low-speed clock is sufficient, a three-stage pipeline process with less penalty due to branch interlock can be used.
[0011]
As described above, the conventional first to third pipeline arithmetic processing devices switch pipelines by providing pipelines by the number of operation modes in which the number of pipeline stages is varied, or by providing a bypass circuit in a pipeline register. Is provided, and the multiplexer selects the output of the pipeline register and the output of the bypass circuit and selects the output.
[0012]
As a result, it is necessary to provide the same number of pipelines as the number of variable operation modes, or to provide a bypass circuit in the pipeline register, which increases the circuit scale.
[0013]
Further, when a bypass circuit is provided in a pipeline register, a multiplexer is required for each pipeline register, so that the circuit scale increases as compared with a case where the number of pipeline stages is not variable (fixed). There is also a problem that the number of gates of the pipeline stage increases due to the multiplexer, and the maximum operating frequency with a high-speed clock decreases.
[0014]
[Problems to be solved by the invention]
In the above-described conventional pipeline arithmetic processing device and pipeline arithmetic control method, pipelines are switched by the number of operation modes in which the number of pipeline stages is changed, or pipelines are switched, or a bypass circuit is provided in a pipeline register. Since the output of the pipeline register and the output of the bypass circuit are received by the multiplexer and the output is selected, the pipeline is provided for the number of variable operation modes or the bypass circuit is provided in the pipeline register. Since it needs to be provided, there is a disadvantage that the circuit scale increases.
[0015]
Further, when a bypass circuit is provided in a pipeline register, a multiplexer is required for each pipeline register, so that the circuit scale increases as compared with a case where the number of pipeline stages is not variable (fixed). The multiplexer increases the number of gates of the pipeline stage, and has a disadvantage that the maximum operating frequency with a high-speed clock decreases.
[0016]
An object of the present invention is to provide a pipeline arithmetic processing device and a pipeline arithmetic control method that can change the number of pipeline stages without increasing the circuit scale or lowering the maximum operating frequency with a high-speed clock.
.
[0017]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a pipeline arithmetic processing device having a first stage number having an arithmetic unit each executing a predetermined arithmetic process, and a pipeline register for temporarily storing arithmetic data output by the arithmetic unit. The pipeline stages are cascade-connected, and the number of the pipeline stages is set to the high-speed so that the high-speed (high-speed) high-speed clock signal and the low-frequency low-speed clock signal operate optimally according to the control of the clock mode signal. In a pipeline arithmetic processing device which is variable by switching between the first number of stages corresponding to a clock signal and the second number of stages corresponding to the low-speed clock signal,
In the case of the high-speed clock signal, all of the pipeline registers of each of the first number of pipeline stages are made effective by performing the operation of storing the operation data, and the pipeline operation processing device of the first number of stages is enabled. And when the low-speed clock signal is used, the operation is performed in a pipeline register of a third stage number other than the pipeline register of the pipeline stage of the second stage number among the pipeline stages of the first stage number. The data storage operation is stopped to invalidate the operation and operate as the second stage number of pipeline operation devices.
[0018]
The invention according to claim 2 is the pipeline arithmetic processing device according to claim 1, wherein the first stage number is twice the second stage number, and the third stage number is the second stage number. It is characterized by being equal to
[0019]
According to a third aspect of the present invention, there is provided a pipeline arithmetic processing device having a first stage number having an arithmetic unit for executing a predetermined arithmetic process and a pipeline register for temporarily storing arithmetic data output from the arithmetic unit. The pipeline stages are cascade-connected, and the number of the pipeline stages is set to the high-speed so that the high-speed (high-speed) high-speed clock signal and the low-frequency low-speed clock signal operate optimally according to the control of the clock mode signal. In a pipeline arithmetic processing device which is variable by switching between the first number of stages corresponding to a clock signal and the second number of stages corresponding to the low-speed clock signal,
The second pipeline register having the first pipeline register having a switching function of switching to one of an execution state and a stop state of the operation of storing the operation data in response to the supply of the switching control signal corresponding to the clock mode signal; A first number of pipeline stages;
A second pipeline stage having the second number of stages including the second pipeline register without the switching function;
A control unit that outputs the switching control signal in response to control of the clock mode signal,
Cascading a set of pipeline stages formed by cascading the first and second pipeline stages;
When the clock mode signal designates the high-speed clock signal, the storage operation of the first pipeline register is performed to be effective by performing the storage operation, and the number of times of the second stage is doubled together with the second pipeline stage. Operating as a pipeline arithmetic processing device of the first stage number corresponding to
When the clock mode signal specifies the low-speed clock signal, the storage operation of the first pipeline register is stopped to invalidate the first pipeline register to operate as the second-stage pipeline arithmetic processing device. Is what you do.
[0020]
According to a fourth aspect of the present invention, in the pipeline arithmetic processing device of the third aspect, the first pipeline register holds input data in accordance with a first level of the switching control signal. And a D flip-flop with a through operation mode for performing a through operation in which the input data is passed without being held in accordance with the second level of the switching control signal.
[0021]
According to a fifth aspect of the present invention, in the pipeline operation processing device according to the third aspect, the first pipeline register is cascaded, and a clock having an opposite phase is input to one clock input terminal. And a second D-latch,
A control circuit, wherein the control unit outputs a switching control signal in response to control of the clock mode signal;
An inverter that inverts the clock signal and outputs an inverted clock signal;
A first OR circuit which takes an OR logic of the switching control signal and the inverted clock signal and supplies a mask inverted clock signal to a clock input terminal of the first D latch; A second OR circuit that takes an OR logic and supplies a mask clock signal to a clock input terminal of the second D latch.
The first and second D latches operate as D flip-flops that hold input data in accordance with a first level of the switching control signal, and the input data in response to a second level of the switching control signal. , And operates as a D flip-flop with a through operation mode for performing a through operation of passing through without holding.
[0022]
According to a sixth aspect of the present invention, in the pipeline operation processing device of the fourth aspect, the D flip-flop with the through operation mode is cascaded, and a clock having an opposite phase is input to one clock input terminal. First and second D latches;
An inverter that inverts the clock signal and outputs an inverted clock signal;
A first OR circuit which takes an OR logic of the switching control signal and the inverted clock signal and supplies a mask inverted clock signal to a clock input terminal of the first D latch; And a second OR circuit that takes an OR logic and supplies a mask clock signal to a clock input terminal of the second D latch.
[0023]
A first aspect of the present invention is a pipeline arithmetic processing device having a first stage number having an arithmetic unit each executing a predetermined arithmetic process, and a pipeline register for temporarily storing arithmetic data output by the arithmetic unit. The pipeline stages are cascade-connected, and the number of the pipeline stages is set to the high-speed so that the high-speed (high-speed) high-speed clock signal and the low-frequency low-speed clock signal operate optimally according to the control of the clock mode signal. In a pipeline arithmetic processing device which is variable by switching between the first number of stages corresponding to a clock signal and the second number of stages corresponding to the low-speed clock signal,
A switching control unit that outputs independent switching control signals for the first number of stages that independently control the pipeline registers of each of the first number of pipeline stages in response to control of the clock mode signal; ,
The pipeline register having a switching function in which each of the first number of pipeline stages is switched to one of an execution state and a stop state of a storage operation of the operation data in response to the supply of the independent switching control signal With
When the clock mode signal designates the high-speed clock signal, the storage operation of the pipeline register is performed to be effective by operating the pipeline operation device of the first stage number,
When the clock mode signal specifies the low-speed clock signal, the storage operation of the pipeline registers of the pipeline stages other than the pipeline stages of the second predetermined number of stages is invalidated by stopping the storage operation. It is characterized by being operated as a pipeline arithmetic processing device of a second stage number.
[0024]
The invention according to claim 8 is the pipeline arithmetic processing device according to claim 7, wherein the pipeline registers of the first number of pipeline stages are independent of each other in response to supply of a system clock signal. And a clock control unit for supplying the clock signal.
[0025]
According to a ninth aspect of the present invention, there is provided the pipeline operation control method, wherein each of the first and second stages includes an operation unit for executing a predetermined operation process and a pipeline register for temporarily storing operation data output from the operation unit. The number of the pipeline stages is set to be the first stage number corresponding to the high-speed clock signal so that the pipeline stages are cascade-connected, and the number of the pipeline stages is adjusted to the optimum operation at each of the high-frequency (speed) first and low-frequency low-speed clock signals. And the second stage number corresponding to the low-speed clock signal, the pipeline operation control method comprising:
In the high-speed clock mode that is the high-speed clock signal, all of the pipeline registers of the first number of pipeline stages are made effective by performing the operation of storing the operation data, and the first number of pipeline stages is made effective. Operate as a pipeline arithmetic processing unit,
In the low-speed clock mode, which is the low-speed clock signal, in the third stage pipeline registers other than the pipeline registers of the second stage pipeline stages of the first stage pipeline stages. The storage operation of the operation data is stopped so that the operation is invalidated and the operation is performed as the second-stage pipeline operation device.
[0026]
According to a tenth aspect of the present invention, in the pipeline operation control method according to the ninth aspect, when changing from the high-speed clock mode to the low-speed clock mode at a first time, the first time immediately before the first time is changed. Operating in the high-speed clock mode until time 0, operating as the pipeline arithmetic processing device of the first number of stages,
Switching the clock frequency supplied to the pipeline register to the low-speed clock at the first time, stopping fetching of a new instruction,
The remaining instructions at the time of stopping the instruction fetching are executed in the low-speed mode, the operation in the low-speed clock mode is started from the second time following the completion of all the instructions, and the new instruction is fetched. Characterized by operating as a pipeline arithmetic processing device.
[0027]
The invention according to claim 11 is the pipeline operation control method according to claim 9, wherein when the clock mode is changed during the first time, the clock frequency is not switched to the low-speed clock and the remaining clock frequency is not changed to the low-speed clock. Executing the instruction in the high-speed clock mode, and switching the clock frequency to the low-speed clock at a third time after completion of all the instructions to start the operation in the low-speed clock mode. is there.
[0028]
According to a twelfth aspect of the present invention, in the pipeline operation control method according to the ninth aspect, the pipeline operation processing device operates in the high-speed clock mode until the zeroth time and operates as the first stage number of pipeline operation processing devices. ,
Switching the clock frequency supplied to the pipeline register to the low-speed clock at the first time, interrupting the fetch of a new instruction,
Resume fetching new instructions at a third time following the first time;
Interrupting the fetch of a new instruction at a fourth time following the third time;
Restart fetching new instructions at a fifth time following the fourth time;
At a sixth time following the fifth time, the clock frequency is switched to the low-speed clock to start the operation in the low-speed clock mode.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0030]
A pipeline operation processing device and a pipeline operation control method according to the present embodiment each include an operation unit that executes a predetermined operation process, and a pipeline register that temporarily stores operation data output by the operation unit. One pipeline stage is connected in cascade, and the pipeline stage is configured to operate optimally with each of a high-frequency (speed) high-speed clock signal and a low-frequency low-speed clock signal according to control of a clock mode signal. In the pipeline arithmetic processing device, the number of stages is variable by switching between the first number of stages corresponding to the high-speed clock signal and the second number of stages corresponding to the low-speed clock signal, All of the pipeline registers of each of the number of pipeline stages are stored in the operation data storage operation. In this case, the first stage number of pipeline stages is operated effectively as the first stage number of pipeline operation processing devices, and the second stage number of pipeline stages among the first stage number of pipeline stages is operated at the time of the low-speed clock signal. By stopping the operation of storing the operation data in the pipeline registers of the third stage other than the pipeline registers, the operation is invalidated and the pipeline operation device of the second stage is operated.
[0031]
Next, referring to FIG. 1 showing a block diagram of an embodiment of the present invention, the pipeline arithmetic processing device of this embodiment shown in FIG. And a configuration corresponding to an operation mode corresponding to a clock frequency in response to the supply of a clock mode signal CM (configuration And a control unit 7 that outputs a control signal SEL for switching to (1).
[0032]
The pipeline stage 1 includes an operation unit S1 and a pipeline register R1 having a bit width processed by the pipeline.
[0033]
The pipeline stage 2 includes an operation unit S2 and a pipeline register R2 having a bit width to be processed by the pipeline.
[0034]
The pipeline stage 3 includes an operation unit S3 and a pipeline register R3 having a bit width processed by the pipeline.
[0035]
The pipeline stage 4 includes an operation unit S4 and a pipeline register R4 having a bit width processed by the pipeline.
[0036]
The pipeline stage 5 includes an operation unit S5 and a pipeline register R5 having a bit width processed by the pipeline.
[0037]
The pipeline stage 6 includes an operation unit S6 and a pipeline register R6 having a bit width processed by the pipeline.
[0038]
The control unit 7 supplies a control signal SEL to each of the pipeline registers R1, R3, and R5 of the pipeline stages 1, 3, and 5. Each of the pipeline registers R1, R3, and R5 supplies the control signal SEL. To switch to the valid or invalid (through) state.
[0039]
In the present embodiment, as will be described later, when the clock mode signal CM is a high-frequency (hereinafter, high-speed) clock corresponding to the L level, the control signal SEL is set to the L level, and in response to the L level of the control signal SEL, Each of the pipeline registers R1, R3, and R5 becomes valid, forming a six-stage pipeline operation processing circuit including pipeline stages 1, 2, 3, 4, 5, and 6. On the other hand, if the clock mode signal CM is a low frequency (hereinafter, low speed) clock corresponding to the H level, the control signal SEL is set to the H level, and the pipeline registers R1, R3, R5 are responded to the H level of the control signal SEL. Are invalid, that is, invalid, and each of the pipeline stages 1 and 2, 3 and 4, 5 and 6 constitutes a three-stage pipeline operation processing circuit which operates as one pipeline stage.
[0040]
Each of the pipeline registers R1, R3, and R5 includes a D flip-flop having a through operation mode for performing the above operation. Referring to FIG. 2 which shows the details of the pipeline register R1 as a block on behalf of the pipeline registers R1, R3, and R5, FIG. 2 shows a configuration for one bit for convenience of description, and shows one clock input terminal connected in cascade. , Two inverters N1 that invert the clock signal CLK and output an inverted clock signal, and a control signal SEL and an inverted clock signal supplied from the control unit 7. An OR circuit O1 that takes an OR logic and supplies a mask inverted clock signal MCB to a clock input terminal of a D latch L1, and an OR logic of a control signal SEL and a clock signal CLK and takes a mask clock signal MC and supplies a mask input signal of a D latch L2 to a D latch L2. And an OR circuit O2 for supplying the OR circuit O.
[0041]
Each of the pipeline registers R2, R4, and R6 is composed of a known ordinary D flip-flop.
[0042]
Next, the operation of the present embodiment will be described with reference to FIGS. 1 and 2. Data input to each of the pipeline stages 1, 2, 3, 4, 5, and 6 is Each of the operation units S1, S2, S3, S4, S5, and S6 of the stage is supplied with each other to perform an operation process, and is stored in each of the pipeline registers R1, R2, R3, R4, R5, and R6 of each stage and the next data is stored. Wait for.
[0043]
The general operation itself of such a pipeline operation device is well known to those skilled in the art, and a detailed description thereof will be omitted.
[0044]
As described above, the control unit 7 switches the number of pipeline stages according to the level of the control signal SEL corresponding to the clock mode signal CM set according to the clock frequency (speed) to be used. That is, the control signal SEL is supplied to each of the pipeline registers R1, R3, R5 of the pipeline stages 1, 3, 5, and each of the pipeline registers R1, R3, R5 controls the level L / H of the control signal SEL. To switch to the valid or invalid (through) state.
[0045]
First, in the case of a high-speed clock, the level of the clock mode signal CM is L level, and the level of the corresponding control signal SEL is also L level. In response to the L level of the control signal SEL, each of the pipeline registers R1, R3, and R5 is enabled, and a six-stage pipeline operation processing circuit including pipeline stages 1, 2, 3, 4, 5, and 6 is provided. Constitute.
[0046]
Next, in the case of a low-speed clock, the level of the clock mode signal CM is at the H level, and the level of the corresponding control signal SEL is also at the H level. In response to the H level of the control signal SEL, each of the pipeline registers R1, R3, and R5 becomes invalid, that is, enters a through state. Thus, each of the pipeline stages 1, 2, 3, 4, 5, and 6 constitutes one pipeline stage 1 + 2, 3 + 4, 5 + 6.
[0047]
In this way, in the case of the high-speed clock, the input data DI is processed by the six-stage pipeline operation processing circuit including the pipeline stages 1, 2, 3, 4, 5, and 6, and is output as the output data DO. I do. On the other hand, in the case of a low-speed clock, each is processed by a three-stage pipeline operation processing circuit including pipeline stages 1 + 2, 3 + 4, and 5 + 6, and output as output data DO.
[0048]
Next, the operation of the pipeline register R1 will be described with reference to FIG. 2 as a representative of the pipeline registers R1, R3, and R5 (the operation for one bit will be described for convenience). , Control signal SEL is set to L level. The control signal SEL is supplied to one input terminal of the OR circuit O1 connected to the clock input terminal of the D latch L1, and an inverted clock signal obtained by inverting the clock signal CLK by the inverter N1 is supplied to the other input terminal. , And receives a supply of a mask inverted clock signal MCB which is an OR logic of the two. Therefore, the D latch L1 captures the input D signal at the transition timing of the clock signal CLK from the H level to the L level, that is, at the falling front edge, and outputs the output Q signal at the falling front edge of the next clock signal CLK. On the other hand, the D latch L2 is supplied with the control signal SEL at one input terminal of the OR circuit O2 connected to the clock input terminal, and is supplied with the clock signal CLK at the other input terminal. The supply of the mask inversion clock signal MC is received. Therefore, the D latch L2 takes in the input D signal which is the output Q signal of the D latch L1 at the leading edge of the clock signal CLK and outputs the output Q signal at the leading edge of the next clock signal CLK. That is, normal D flip-flop operation is performed by the D latches L1 and L2. That is, it becomes effective as a pipeline register and holds input data.
[0049]
Next, in the case of the low-speed clock operation, the control signal SEL is set to the H level. The control signal SEL at one input terminal of the OR circuit O1 is at the H level, and therefore, the mask inverted clock signal MCBD at the H level is supplied to the latch L1 regardless of the level of the inverted clock signal at the other input terminal. Therefore, the D latch L1 does not operate as the D latch, and outputs the input data as it is as output data, that is, enters a through state. The control signal SEL at one input terminal of the OR circuit O2 is also at the H level, so that the mask clock signal MC at the H level is supplied to the latch L2 regardless of the level of the clock signal CLK at the other input terminal. Supply. Therefore, the D latch L2 also does not operate as a D latch and enters a through state. As a result, the pipeline register R1 constituted by the D latches L1 and L2 is invalidated, that is, passed without performing the data storing operation.
[0050]
Next, the details of the high-speed clock operation of the present embodiment will be described with reference to FIG. 3, which is a time chart showing clocks, instructions, and processing states of each stage when the clock mode of the present embodiment is a high-speed clock. In this case, since the operation in this case is a six-stage pipeline configuration, as described above, by setting the clock mode signal CM to the L level and thus the control signal SEL to the L level, the pipeline registers R1, R3, R5 Are effective, and a six-stage pipeline operation processing circuit including pipeline stages 1, 2, 3, 4, 5, and 6 is configured. As shown, the pipeline stages 1, 2, 3, 4, 5, and 6 are assigned to the respective pipeline stages in accordance with instructions 1 to 6 for each clock cycle as time T progresses (in parentheses). Each process of IF1, IF2, ID1, ID2, EX1 and EX2 is sequentially executed. The processing IF indicates an instruction fetch, the processing ID indicates an instruction decode, and the processing EX indicates an instruction execution.
[0051]
That is, at time T1, the pipeline stage 1 executes the processing IF1 according to the instruction 1, and the pipeline stages 2 to 6 are in a standby state. At time T2, the pipeline stage 1 executes the processing IF1 according to the instruction 2, the pipeline stage 2 executes the processing IF2 according to the instruction 1, and the pipeline stages 3 to 6 are in a standby state. Thereafter, at time T3... T6, the pipeline stages 3 to 6 sequentially execute the processing ID1, ID2, EX1, and EX2 according to the instruction 1. For the instruction 2, the processing IF1 of the pipeline stage 1 is executed from time T2, and the processing EX2 of the pipeline stage 6 is executed at time T7.
[0052]
Similarly, for the instructions 3 to 6, the processing IF1 of the pipeline stage 1 is executed at times T3 to T6, and the processing EX2 of the pipeline stage 6 is executed at times T8 to T11. In this example, at time T6, processes IF1, IF2, ID1, ID2, EX1, and EX2 of all the pipeline stages 1 to 6 for the instructions 6 to 1 are being executed.
[0053]
Next, details of the low-speed clock operation of the present embodiment will be described with reference to FIG. 4 which is a time chart showing clocks, instructions, and processing states of each stage when the clock mode of the present embodiment is a low-speed clock. To explain, in this case, for convenience of explanation, since the operation is of a three-stage pipeline configuration in which the clock frequency is set to 高速 of the high-speed clock, the clock mode signal CM is set at the H level, and thus the control signal SEL, as described above. Is set to the H level to make each of the pipeline registers R1, R3, and R5 through (invalid), thereby configuring a three-stage pipeline operation processing circuit including pipeline stages 1 + 2, 3 + 4, and 5 + 6. Each of these pipeline stages 1 + 2, 3 + 4, and 5 + 6 sequentially executes the processing of processing IF1 + IF2, ID1 + ID2, and EX1 + EX2 as time T progresses, respectively.
[0054]
That is, at time T1 + T2, pipeline stage 1 + 2 executes processing IF1 + IF2 according to instruction 1, and pipeline stages 3 + 4, 5 + 6 are in a standby state. At time T3 + T4, pipeline stage 1 + 2 executes processing IF1 + IF2 according to instruction 2, pipeline stage 3 + 4 executes processing ID1 + ID2 according to instruction 1, and pipeline stage 5 + 6 is in a standby state. Next, at time T5 + T6, the pipeline stages 1 + 2 execute the processing IF1 + IF2 according to the instruction 3, the pipeline stages 3 + 4 execute the processing ID1 + ID2 according to the instruction 2, and the pipeline stages 5 + 6 execute the processing EX1 + EX2 according to the instruction 1. Hereinafter, the above operations are repeated in instructions 4 to 6.
[0055]
Next, referring to FIG. 5 which is a time chart showing the clock, the command, and the processing state of each stage during switching of the clock mode from the high-speed clock to the low-speed clock, the high-speed clock to the low-speed clock according to the present embodiment will be described. The operation of the first pipeline operation control method, which is the first switching method, will be described. Here, for convenience of description, the clock mode is changed at time T7. First, until the time T6, similarly to the high-speed operation shown in FIG. Next, at time T7, the clock mode is changed, the clock input to the pipeline register is switched from the high-speed clock to the low-speed clock, and the acquisition of a new instruction is stopped. The fetched instruction is processed with a new low-speed clock in which one clock is 2 hours and T, with the pipeline configuration of six stages. Therefore, in this example, five clocks, that is, 10T, are required for instruction processing for the remaining five stages of pipeline, and it takes up to time T16.
[0056]
At time T16, all the instructions being processed in the pipeline are completed.
[0057]
From time T17, the operation is performed in a three-stage pipeline configuration as in the case of the low-speed clock operation shown in FIG.
[0058]
Also, a time chart shows an operation during the change from the high-speed clock to the low-speed clock in the second pipeline operation control method, which is the second switching method from the high-speed clock to the low-speed clock in the pipeline operation device of the present embodiment. Referring to FIG. 6, when the clock mode is changed at time T7, the clock frequency input to the register is not simultaneously switched as in the above-described pipeline operation control method, and the number of pipeline stages is actually switched. By delaying the switching of the clock frequency input to the register until T12, the required switching time can be reduced.
[0059]
Further, a time chart shows the operation during the change from the high-speed clock to the low-speed clock in the third pipeline operation control method, which is the third switching method from the high-speed clock to the low-speed clock in the pipeline operation device of the present embodiment. Referring to FIG. 7 shown here, the following operation is performed by devising the timing at which a new instruction is fetched.
[0060]
Until time T6, the operation is performed in a six-stage pipeline configuration as in the high-speed operation. Next, at time T7, the clock mode is changed, and fetching of a new instruction is interrupted. At time T8, fetching of a new instruction is resumed. At time T9, fetching of a new instruction is interrupted. At time T10, fetching of a new instruction is restarted.
[0061]
From time T12, as in the low-speed clock operation, the clock frequency input to the register is switched, and the operation is performed in a three-stage pipeline configuration.
[0062]
In other words, stop fetching of new instructions until all the instructions being processed in the pipeline are completed, and after the instruction being processed is completed, switch to clock mode instead of enabling or disabling the register that switches the number of stages. Accordingly, a method of interrupting the fetching of a new instruction is used.
[0063]
Next, referring to FIG. 8 which shows a clock, an instruction, and a processing state of each stage while the clock mode is changing from the low-speed clock to the high-speed clock with reference to FIG. The operation during the change will be described. Here, for convenience of description, the clock mode is changed at time T14. First, the operation is performed in a three-stage pipeline configuration until time T12, as in the low-speed operation. Next, at time T14, the clock mode is changed, the clock frequency input to the register is switched, and the acquisition of a new instruction is stopped.
[0064]
At time T19, all the instructions being processed in the pipeline are completed.
[0065]
From time T20, as in the case of the high-speed clock operation, the operation is performed with a six-stage pipeline configuration, and fetching of a new instruction is restarted.
[0066]
As described above, in the present embodiment, when changing from the high-speed clock to the low-speed clock, the number of pipeline stages can be switched without waiting for all instructions being processed in the pipeline to end.
[0067]
As described above, unlike the technology using the conventional bypass circuit, data is processed on the same path regardless of the number of stages in the pipeline configuration, so that there is no need for a multiplexer for selecting the output of the bypass circuit and the output of the pipeline register. Become.
[0068]
Accordingly, since the number of gate stages of the stages for switching the number of pipeline stages does not increase, a decrease in the maximum operating frequency in high-speed clock operation can be avoided.
[0069]
Furthermore, while the conventional technology using a bypass circuit requires a multiplexer for each pipeline register, it is configured to control only the clock input of the pipeline register, so that the circuit scale is reduced. be able to.
[0070]
Next, a second embodiment of the present invention will be described with reference to FIG. 9, in which constituent elements common to FIG. The difference between the first embodiment and the first embodiment is that each of the pipeline stages 2A, 4A, and 6A in place of the pipeline stages 2, 4, and 6 includes a pipeline instead of the pipeline registers R2, R4, and R6. Pipeline registers R2A, R4A, R6A having the same through operation mode as the registers R1, R3, R5 are provided. Instead of the control unit 7, the pipeline stages 1, 2, 3, 3 respond to the supply of the clock mode signal CM. , 4,5,6, independent control signals SEL1, which individually control each pipeline stage of each of pipeline registers R1, R2A, R3, R4A, R5, R6A. EL2, SEL3, SEL4, SEL5, is to include a control section 7A for supplying each SEL6.
[0071]
FIG. 10 is a time chart showing an operation during a change from the high-speed clock to the low-speed clock in the fourth pipeline operation control method which is the first switching method from the high-speed clock to the low-speed clock according to the present embodiment. First, assuming that the clock mode is changed at time T7 as in the first embodiment, the circuit operates in a six-stage pipeline configuration until time T6, as in the high-speed operation of the first embodiment. Next, at time T7, the clock mode is changed, the clock frequency input to the pipeline register is switched, and fetching of a new instruction is stopped.
[0072]
At time T13, fetching of a new instruction is resumed, and the instruction of the high-speed clock operation that is already being executed operates in a six-stage pipeline configuration, but the newly fetched instruction operates in a three-stage pipeline configuration. From time T17, the operation is performed with a three-stage pipeline configuration, similarly to the low-speed clock operation of the first embodiment.
[0073]
That is, among the pipeline stages in which the number of stages is switched, the pipeline registers for switching the number of stages are enabled or disabled from the pipeline stage for which processing has been completed.
[0074]
As described above, in the present embodiment, all the pipeline stages are constituted by the D flip-flops having the through operation mode, and it is determined whether each of them is valid as a pipeline register. The number of pipeline stages can be switched sequentially from the stage.
[0075]
Further, in the fifth pipeline operation control method which is a second switching method which is a modification of the switching method of the number of pipeline stages during the change from the high-speed clock to the low-speed clock according to the present embodiment, the high-speed clock is switched to the low-speed clock. Referring to FIG. 11 which is a time chart showing the operation during the change of the clock signal, a control signal SEL for switching the clock frequency supplied to the pipeline register corresponding to the clock mode signal CM is actually set to the number of pipeline stages. The time required for switching can be reduced by delaying the switching.
[0076]
Referring to FIG. 12 showing a time chart of the operation during the change from the low-speed clock to the high-speed clock according to the present embodiment, first, a three-stage pipe until the time T14 as in the low-speed clock operation of the first embodiment. Operates in line configuration. At time T16, the clock mode is changed. At time T18, the instruction already being executed operates in a three-stage pipeline configuration, but the newly fetched instruction operates in a six-stage pipeline configuration. From time T22, similarly to the high-speed clock operation of the first embodiment, the clock frequency input to the pipeline register is switched, and the operation is performed with a six-stage pipeline configuration.
[0077]
As described above, in the present embodiment, the number of pipeline stages can be switched while continuously taking in the next instruction without waiting for all instructions being processed in the pipeline to end.
[0078]
Furthermore, even when the clock mode has a large number of clock frequency operations, the number of pipeline stages can be changed to an arbitrary number of stages, so that in any clock mode, a synergistic effect that wasteful instruction execution efficiency can be obtained. Play.
[0079]
Next, a third embodiment of the present invention will be described with reference to FIG. 13 which shows the same components as those in FIG. This embodiment differs from the second embodiment in that each of the pipeline stages 1, 2A, 3, 4A, 5, 6A responds to the supply of the system clock CLK in addition to the control unit 7A. A control unit 8 that supplies independent clock signals CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6 to the line registers R1, R2A, R3, R4A, R5, and R6A is provided.
[0080]
In the first and second embodiments described above, the effect of shortening the time required for switching the pipeline for the change of the clock mode is achieved by using a common input clock for the pipeline register of each pipeline stage. Although it is obtained from the determination of the fetch of the next instruction and the switching timing of the number of pipeline stages, in the present embodiment, it can be achieved by inputting clocks at individual timings.
[0081]
FIG. 14 is a time chart showing an operation during a change from the high-speed clock to the low-speed clock in the sixth pipeline operation control method which is a method for switching from the high-speed clock to the low-speed clock according to the present embodiment. Assuming that the clock mode is changed at time T7 in the same manner as in the first and second embodiments, a pipeline of six stages with the same high-speed clock frequency and the same high-speed operation as in the first embodiment until time T6 is used. Works with configuration. Next, at time T7, the clock mode is changed, the clock frequency input to the pipeline register is switched, and fetching of a new instruction is stopped.
[0082]
At time T8, fetching of a new instruction is resumed, and the already executed high-speed clock operation instruction operates in a six-stage pipeline configuration without switching the clock frequency supplied to the pipeline register. Operates in a three-stage pipeline configuration by switching the supplied clock frequency.
[0083]
From time T12, as in the case of the low-speed clock operation of the first embodiment, the circuit operates with the same low-speed clock frequency in a three-stage pipeline configuration.
[0084]
Next, referring to FIG. 15, which is a time chart showing the operation during the change from the low-speed clock to the high-speed clock, the circuit operates in a three-stage pipeline configuration at the same low-speed clock frequency until time T12. At time T14, the clock mode is changed. At time T16, the instruction already being executed operates in a three-stage pipeline configuration without switching the clock frequency supplied to the pipeline register, but the newly fetched instruction switches the supplied clock frequency to switch the clock frequency supplied to the pipeline register to six stages. Operates in a pipeline configuration. From time T20, the circuit operates with the same high-speed clock frequency in a six-stage pipeline configuration.
[0085]
That is, in the present embodiment, an operation of switching the number of pipeline stages while simultaneously performing pipeline processing with clock signals of different frequencies is obtained, and the object of the present invention is achieved.
[0086]
Next, a fourth embodiment of the present invention will be described with reference to FIG. 16 which shows the same components as those in FIG. The difference between the first embodiment and the first embodiment is that pipeline stages 1B, 3B, and 5B are provided instead of pipeline stages 1, 3, and 5, and each of these pipeline stages 1B, 3B, and 5B is provided. Instead of each of the pipeline registers R1, R3, and R5 configured with D flip-flops having a through operation mode, there are provided pipeline registers R1B, R3B, and R5B configured with only D latches. Is provided with a control unit 7B having a clock mask function.
[0087]
FIG. 17 is a block diagram showing the configuration of the pipeline register R1B and the control unit 7B as a representative of the pipeline registers R1B, R3B, and R5B. Referring to FIG. Has two D-latches L1 and L2 cascade-connected to each other and having one clock input terminal to which a clock having an opposite phase is input. The control unit 7B has the same function as the control unit 7 of the first embodiment, that is, A control circuit 71 that outputs a control signal SEL in response to the supply of the clock mode signal CM, an inverter N1 that inverts the clock signal CLK and outputs an inverted clock signal, and ORs the control signal SEL and the inverted clock signal. An OR circuit O1 for supplying the mask inverted clock signal MCB to the clock input terminal of the D latch L1, a control signal SEL and a clock signal; A mask clock signal MC takes the OR logic of the click signal CLK and a OR circuit O2 is supplied to the clock input of D latch L2.
[0088]
Therefore, the two D-latches L1 and L2 of the pipeline register R1B of this embodiment, the OR circuits O1 and O2 of the control unit 7B, and the inverter N1 are substantially the same as the pipeline register R1 of the first embodiment. Construct a D flip-flop. Therefore, the operation of the present embodiment is the same as the operation of the first embodiment.
[0089]
In the present embodiment, as described above, a configuration is possible in which the control unit 7B is provided with a mask circuit for clocks supplied to the D latches of the pipeline registers R1B, R3B, and R5B as one unit. This has the effect of further reducing the circuit scale.
[0090]
【The invention's effect】
As described above, the pipeline operation processing device and the pipeline operation control method of the present invention store all of the pipeline registers of the first number of pipeline stages when the high-speed clock signal is stored in the pipeline data. When the low-speed clock signal is applied, the pipeline stage of the second stage among the pipeline stages of the first stage is activated when the operation is performed. The storage operation of the operation data in the pipeline registers of the third stage other than the line register is stopped to invalidate the operation, and the operation is performed as the pipeline operation device of the second stage, whereby the operation is the same regardless of the number of stages in the pipeline configuration. Since the data is processed in the path, the output of the bypass circuit and the pipeline Multiplexer for selecting the output of the register has the effect of suppressing an increase in circuit scale becomes unnecessary.
[0091]
Further, since the number of gate stages of the stages for switching the number of pipeline stages does not increase, there is an effect that a decrease in the maximum operating frequency in high-speed clock operation can be avoided.
[0092]
Further, since only the clock input of the pipeline register is controlled, the circuit size can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a pipeline arithmetic processing device according to the present invention.
FIG. 2 is a block diagram showing a configuration of a pipeline register R1 of FIG.
FIG. 3 is a time chart of a high clock speed operation showing an example of an operation in the pipeline arithmetic processing device of the present embodiment.
FIG. 4 is a time chart of a low clock speed operation showing an example of an operation in the pipeline arithmetic processing device of the present embodiment.
FIG. 5 is a time chart showing a first pipeline operation control method which is a method of switching from a high clock speed operation to a low clock operation in the pipeline operation processing device of the present embodiment.
FIG. 6 is a time chart showing a second pipeline operation control method which is a second switching method from the high clock speed operation to the low clock operation in the pipeline operation processing device of the present embodiment.
FIG. 7 is a time chart showing a third pipeline operation control method which is a third switching method from the high clock speed operation to the low clock operation in the pipeline operation processing device of the present embodiment.
FIG. 8 is a time chart showing a method of switching from a low clock speed operation to a high clock operation in the pipeline arithmetic processing device of the present embodiment.
FIG. 9 is a block diagram showing a second embodiment of the pipeline arithmetic processing device of the present invention.
FIG. 10 is a time chart showing a fourth pipeline operation control method which is a first switching method from the high clock speed operation to the low clock operation in the pipeline operation processing device of the present embodiment.
FIG. 11 is a time chart showing a fifth pipeline operation control method which is a second switching method from the high clock speed operation to the low clock operation in the pipeline operation processing device of the present embodiment.
FIG. 12 is a time chart showing a method for switching from a low clock speed operation to a high clock operation in the pipeline arithmetic processing device of the present embodiment.
FIG. 13 is a block diagram showing a third embodiment of the pipeline operation processing device of the present invention.
FIG. 14 is a time chart illustrating a sixth pipeline operation control method which is a method of switching from a high clock speed operation to a low clock operation in the pipeline operation processing device of the present embodiment.
FIG. 15 is a time chart showing a method of switching from a low clock speed operation to a high clock operation in the pipeline arithmetic processing device of the present embodiment.
FIG. 16 is a block diagram showing a fourth embodiment of the pipeline operation processing device of the present invention.
FIG. 17 is a block diagram showing a configuration of a pipeline register R1 of FIG.
FIG. 18 is a block diagram illustrating an example of a first conventional pipeline arithmetic processing device.
FIG. 19 is a block diagram illustrating an example of a second conventional pipeline operation processing device.
FIG. 20 is a block diagram showing an example of a third conventional pipeline operation processing device.
[Explanation of symbols]
1,2,3,4,5,6,2A, 4A, 6A, 1B, 2B, 3B, 4B, 5B, 6B pipeline stage
7, 7A, 7B control unit
71 Control circuit
S1, S2, S3, S4, S5, S6 arithmetic unit
R1, R2, R3, R4, R5, R6, R2A, R4A, R6A, R1B, R3B, R5B pipeline registers

Claims (12)

A clock mode signal of a clock mode signal is formed by cascade-connecting a first number of pipeline stages each having an operation unit for executing a predetermined operation process and a pipeline register for temporarily storing operation data output by the operation unit. The number of stages of the pipeline stage is adjusted to the first stage number corresponding to the high-speed clock signal and the low-speed clock signal so that the high-speed clock signal and the low-frequency clock signal operate optimally under control. In a pipeline arithmetic processing device which is made variable by switching to a corresponding second stage number,
In the case of the high-speed clock signal, all of the pipeline registers of each of the first number of pipeline stages are made effective by performing the operation of storing the operation data, and the pipeline operation processing device of the first number of stages is enabled. And when the low-speed clock signal is used, the operation is performed in a pipeline register of a third stage number other than the pipeline register of the pipeline stage of the second stage number among the pipeline stages of the first stage number. A pipeline arithmetic processing device wherein the data storage operation is stopped to invalidate the operation and operate as the pipeline arithmetic device of the second stage number. 2. The pipeline arithmetic processing device according to claim 1, wherein the first stage number is twice as large as the second stage number, and the third stage number is equal to the second stage number. A clock mode signal of a clock mode signal is formed by cascade-connecting a first number of pipeline stages each having an operation unit for executing a predetermined operation process and a pipeline register for temporarily storing operation data output by the operation unit. The number of stages of the pipeline stage is adjusted to the first stage number corresponding to the high-speed clock signal and the low-speed clock signal so that the high-speed clock signal and the low-frequency clock signal operate optimally under control. In a pipeline arithmetic processing device which is made variable by switching to a corresponding second stage number,
The second pipeline register having the first pipeline register having a switching function of switching to one of an execution state and a stop state of the operation of storing the operation data in response to the supply of the switching control signal corresponding to the clock mode signal; A first number of pipeline stages;
A second pipeline stage having the second number of stages including the second pipeline register without the switching function;
A control unit that outputs the switching control signal in response to control of the clock mode signal,
Cascading a set of pipeline stages formed by cascading the first and second pipeline stages;
When the clock mode signal designates the high-speed clock signal, the storage operation of the first pipeline register is performed to be effective by performing the storage operation, and the number of times of the second stage is doubled together with the second pipeline stage. Operating as a pipeline arithmetic processing device of the first stage number corresponding to
When the clock mode signal specifies the low-speed clock signal, the storage operation of the first pipeline register is stopped to invalidate the first pipeline register to operate as the second-stage pipeline arithmetic processing device. Pipeline arithmetic processing unit. The first pipeline register operates as a D flip-flop that holds input data according to a first level of the switching control signal, and holds the input data according to a second level of the switching control signal. 4. The pipeline arithmetic processing device according to claim 3, further comprising a D flip-flop with a through operation mode for performing a through operation of directly passing through without performing. The first pipeline register includes first and second D latches that are cascade-connected and have opposite clocks input to one clock input terminal,
A control circuit, wherein the control unit outputs a switching control signal in response to control of the clock mode signal;
An inverter that inverts the clock signal and outputs an inverted clock signal;
A first OR circuit which takes an OR logic of the switching control signal and the inverted clock signal and supplies a mask inverted clock signal to a clock input terminal of the first D latch; A second OR circuit that takes an OR logic and supplies a mask clock signal to a clock input terminal of the second D latch.
The first and second D latches operate as D flip-flops that hold input data in accordance with a first level of the switching control signal, and the input data in response to a second level of the switching control signal. 4. The pipeline operation processing device according to claim 3, wherein the pipeline operation processing device operates as a D flip-flop with a through operation mode that performs a through operation in which the data is not passed and the through operation is performed. First and second D latches, in which the D flip-flops with the through operation mode are cascaded and one of the clock input terminals receives clocks of opposite phases;
An inverter that inverts the clock signal and outputs an inverted clock signal;
A first OR circuit which takes an OR logic of the switching control signal and the inverted clock signal and supplies a mask inverted clock signal to a clock input terminal of the first D latch; 5. The pipeline arithmetic processing device according to claim 4, further comprising a second OR circuit that takes an OR logic and supplies a mask clock signal to a clock input terminal of the second D latch. A clock mode signal of a clock mode signal is formed by cascade-connecting a first number of pipeline stages each having an operation unit for executing a predetermined operation process and a pipeline register for temporarily storing operation data output by the operation unit. The number of stages of the pipeline stage is adjusted to the first stage number corresponding to the high-speed clock signal and the low-speed clock signal so that the high-speed clock signal and the low-frequency clock signal operate optimally under control. In a pipeline arithmetic processing device which is made variable by switching to a corresponding second stage number,
A switching control unit that outputs independent switching control signals for the first number of stages that independently control the pipeline registers of each of the first number of pipeline stages in response to control of the clock mode signal; ,
The pipeline register having a switching function in which each of the first number of pipeline stages is switched to one of an execution state and a stop state of a storage operation of the operation data in response to the supply of the independent switching control signal With
When the clock mode signal designates the high-speed clock signal, the storage operation of the pipeline register is performed to be effective by operating the pipeline operation device of the first stage number,
When the clock mode signal specifies the low-speed clock signal, the storage operation of the pipeline registers of the pipeline stages other than the pipeline stages of the second predetermined number of stages is invalidated by stopping the storage operation. A pipeline arithmetic processing device operated as a second stage number of pipeline arithmetic processing devices. 8. The pipe according to claim 7, further comprising a clock control unit that supplies an independent clock signal to each of the pipeline registers of each of the first number of pipeline stages in response to a supply of a system clock signal. Line arithmetic processing unit. A high-frequency (speed) configuration is made by cascading a first number of pipeline stages each having an arithmetic unit for executing a predetermined arithmetic process and a pipeline register for temporarily storing arithmetic data output from the arithmetic unit. ), The number of stages of the pipeline stage is switched between the first number of stages corresponding to the high-speed clock signal and the second number of stages corresponding to the low-speed clock signal so as to operate optimally with each of the first and low-frequency low-speed clock signals. In the pipeline operation control method which is made variable by
In the high-speed clock mode that is the high-speed clock signal, all of the pipeline registers of the first number of pipeline stages are made effective by performing the operation of storing the operation data, and the first number of pipeline stages is made effective. Operate as a pipeline arithmetic processing unit,
In the low-speed clock mode, which is the low-speed clock signal, in the third stage pipeline registers other than the pipeline registers of the second stage pipeline stages of the first stage pipeline stages. A pipeline operation control method, wherein the storage operation of operation data is stopped to invalidate the operation so as to operate as the pipeline operation device of the second stage number. When changing from the high-speed clock mode to the low-speed clock mode at a first time, operating in the high-speed clock mode until a time 0 immediately before the first time, and performing the pipeline operation processing of the first number of stages; Work as a device,
Switching the clock frequency supplied to the pipeline register to the low-speed clock at the first time, stopping fetching of a new instruction,
The remaining instructions at the time of stopping the instruction fetching are executed in the low-speed mode, the operation in the low-speed clock mode is started from the second time following the completion of all the instructions, and the new instruction is fetched. 10. The pipeline operation control method according to claim 9, wherein the method operates as a pipeline operation processing device. When the clock mode is changed at the first time, the clock frequency is not switched to the low-speed clock, the remaining instructions are executed in the high-speed clock mode, and the next third instruction after the completion of all the instructions is executed. 10. The pipeline operation control method according to claim 9, wherein the clock frequency is switched to the low-speed clock at a time to start the operation in the low-speed clock mode. Operating in the high-speed clock mode until the zeroth time, operating as the first stage number of pipeline arithmetic processing devices,
Switching the clock frequency supplied to the pipeline register to the low-speed clock at the first time, interrupting the fetch of a new instruction,
Resume fetching new instructions at a third time following the first time;
Interrupting the fetch of a new instruction at a fourth time following the third time;
Restart fetching new instructions at a fifth time following the fourth time;
10. The pipeline operation control method according to claim 9, wherein the clock frequency is switched to the low-speed clock and the operation in the low-speed clock mode is started at a sixth time subsequent to the fifth time.

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