JP2007166096A - Bias control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bias control circuit which facilitates reduction in power consumption. <P>SOLUTION: The bias control circuit 10 has a voltage source 16 for generating a variable DC voltage Vh to be fed to an avalanche photo diode (APD) 12. A current detection means 18 includes a current mirror circuit which detects photo current Iapd generated by the APD 12, and generates monitor voltage Vm according to the photo current Iapd. A voltage control means 24 controls the voltage source 16 to adjust the DC voltage Vh according to the monitor voltage Vm. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bias control circuit for an avalanche photodiode.

A bias control circuit for applying a bias voltage to an avalanche photodiode (APD) in an optical receiver is disclosed (for example, see Patent Documents 1 and 2). In these bias control circuits, a series resistor is connected between the bias voltage source and the APD so that an excessive bias voltage is not applied to the photodiode. The photocurrent generated by the APD in response to the optical input flows through the series resistance, causing a voltage drop. Since the output voltage of the bias voltage source is reduced by the voltage drop and then applied to the APD, the APD bias voltage decreases as the photocurrent increases. As a result, the multiplication factor of the APD photoelectric conversion can be suppressed for a large light input, and the APD can be prevented from being damaged by a large current.
JP-A-11-284445 Japanese Patent Laid-Open No. 2004-71982

  However, in the method of giving the optical input dependency to the bias voltage using the voltage drop due to the series resistance, the power consumed by the series resistance increases as the photocurrent increases, so it is easy to reduce the power consumption. is not. Therefore, an object of the present invention is to provide a bias control circuit that can easily reduce power consumption.

  The present invention relates to a bias control circuit for an avalanche photodiode. This bias control circuit includes a voltage source that generates a variable DC voltage applied to the avalanche photodiode, and a current mirror circuit that detects a photocurrent generated by the avalanche photodiode, and a monitor corresponding to the photocurrent. Current detection means for generating a signal, a voltage dividing circuit for dividing the DC voltage with a voltage dividing ratio according to the monitor signal, and a control circuit for controlling the voltage source according to the output of the voltage dividing circuit. The voltage dividing circuit includes a first resistor and a second resistor connected in series with each other to divide the DC voltage, and a variable resistance element connected to the first resistor or the second resistor. And an element having a resistance that changes accordingly.

  The multiplication factor of photoelectric conversion of the avalanche photodiode changes according to the bias voltage applied to the avalanche photodiode. This bias voltage depends on the DC voltage generated by the voltage source. If the control circuit controls the voltage source so as to reduce the DC voltage when an increase in photocurrent is detected, the multiplication factor of the avalanche photodiode is also lowered accordingly. As a result, the multiplication factor is suppressed when the light input intensity to the avalanche photodiode is high, and self-damage of the avalanche photodiode due to an excessive photocurrent is prevented. Since the direct current voltage is adjusted according to the photocurrent, the power consumption can be easily reduced.

  The current detection unit may include a current mirror circuit that generates a detection current corresponding to the photocurrent and a current-voltage conversion unit that converts the detection current into a voltage signal.

  The first or second resistor may have a temperature characteristic that compensates for the temperature characteristic of the avalanche photodiode. In this case, the voltage division ratio by the first and second resistors reflects the temperature of the photodiode.

  Since the bias control circuit of the present invention controls the voltage applied to the avalanche photodiode according to the light input intensity, it not only prevents damage to the avalanche photodiode due to excessive photocurrent but also reduces power consumption. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

First Embodiment FIG. 1 is a block diagram showing an outline of a bias control circuit of the present embodiment, and FIG. 2 is a circuit diagram of the same bias control circuit. The bias control circuit 10 is installed in the optical receiver 100. In addition to the bias control circuit 10, the optical receiver 100 includes an avalanche photodiode (hereinafter referred to as “APD”) 12 and a preamplifier 14. The bias control circuit 10 drives the APD 12 by applying a reverse bias voltage Vapd to the APD 12. During the driving, the APD 12 detects an optical input signal and converts the optical input signal into a photocurrent Iapd with a certain multiplication factor. The amplification factor of the APD 12 depends on the bias voltage Vapd. The photocurrent Iapd is modulated according to the optical input signal. A preamplifier 14 is connected to the anode of the APD 12. The preamplifier 14 converts the photocurrent Iapd into an electrical output signal Vout with an appropriate amplification factor.

  As shown in FIG. 2, in this embodiment, the preamplifier 14 is a transimpedance amplifier including an inverting amplifier 30 and a feedback resistor 32. However, the preamplifier 14 is not limited to a transimpedance amplifier, and may be composed of, for example, a load resistor connected to the anode of the APD 12 and a voltage amplifier that amplifies the voltage across the load resistor. .

  The bias control circuit 10 includes a high voltage generation circuit 16, a current detection circuit 18, a voltage dividing circuit 20, and a control circuit 22. Hereinafter, these components will be described sequentially.

  The high voltage generation circuit 16 is a voltage source that generates a DC output voltage Vh and applies it to the APD 12. An example of the high voltage generation circuit 16 is a DC-DC converter. The input terminal 41 of the high voltage generation circuit 16 is connected to an external power source. When the DC voltage Vcc is supplied from the external power source to the input terminal 41, the high voltage generation circuit 16 increases or decreases the voltage Vcc and generates the DC voltage Vh at the output terminal 42.

  The output terminal 42 of the high voltage generation circuit 16 is connected to the cathode of the APD 12 via the bias line 15. A current detection circuit 18 for detecting the photocurrent Iapd generated by the APD 12 is provided on the bias line 15. The current detection circuit 18 generates a voltage signal Vm corresponding to the photocurrent Iapd. Hereinafter, this voltage signal is referred to as a “monitor signal”. The current detection circuit 18 supplies the monitor voltage Vm to the voltage dividing circuit 20. One end of the voltage dividing circuit 20 is connected to a node 26 on the bias line 15.

  The control circuit 22 receives the output of the voltage dividing circuit whose voltage dividing ratio is adjusted in accordance with the monitor voltage Vm generated by the current detection circuit 18, and controls the high voltage generating circuit 16 to adjust the DC voltage Vh.

  The voltage dividing circuit 20 outputs a detection voltage corresponding to the monitor voltage Vm and the DC voltage Vh. The voltage dividing circuit 20 includes a first resistor 51 and a second resistor 52 connected in series to each other, and a field effect transistor 72 (hereinafter referred to as “FET”). One end of the first resistor 51 is connected to the output terminal 42 of the high voltage generation circuit 16 via the node 26 on the bias line 15, and the other end is connected to one end of the second resistor 52. The other end of the second resistor 52 is grounded. In FIGS. 1 and 2, the currents flowing through the resistors 51 and 52 are represented by I1 and I2, respectively.

  The FET 72 is connected in parallel to the second resistor 52. In the present embodiment, the FET 72 is a p-type MOSFET. The source of the FET 72 is connected to the node 28, and the drain is grounded. The gate of the FET 72 is connected to the output terminal of the current detection circuit 18 and supplied with the monitor voltage Vm.

The voltage dividing circuit 20 divides the DC voltage Vh by a certain voltage dividing ratio D. The voltage division ratio D depends not only on the resistors 51 and 52 but also on the resistance between the source and drain of the FET 72. When the values of the resistors 51 and 52 are represented as R1 and R2, respectively, and the value of the resistor of the FET 72 is represented as R3,
D = Rc / (R1 + Rc) (1)
It is expressed. Therefore, the node voltage Vfb of node 28 is
Vfb = Vh · D = Vh · Rc / (R1 + Rc) (2)
It is expressed. Here, Rc is a parallel resistance of the second resistance 52 and the resistance of the FET 72. As apparent from the equation (1), the node voltage Vfb depends on both the resistance of the FET 72 and the DC voltage Vh. Under a constant DC voltage Vh, the larger the parallel resistance Rc, the higher the node voltage Vfb.

  The node voltage Vfb is input to the control circuit 22. The output terminal 44 of the control circuit 22 is connected to the high voltage generation circuit 16. The control circuit 22 compares the node voltage Vfb with the reference voltage, increases the DC voltage Vh when the node voltage Vfb is lower than the reference voltage, and decreases the DC voltage Vh when the node voltage Vfb is higher than the reference voltage. The node voltage Vfb reflects the resistance R3 of the FET 72, and this resistance R3 reflects the monitor voltage Vm. Since the monitor voltage Vm depends on the photocurrent Iapd, the control circuit 22 adjusts the DC voltage Vh in accordance with the photocurrent Iapd.

  Furthermore, in the present embodiment, the second resistor 52 is made dependent on the temperature of the APD 12 in order to compensate for the temperature characteristics of the APD 12. That is, the second resistor 52 can be a variable resistor that changes according to the temperature of the APD 12. Instead of the second resistor 52, the first resistor 51 may have temperature dependency. Since the control circuit 22 adjusts the DC voltage Vh so as to keep the node voltage Vfb constant, if the temperature of the APD 12 changes, the DC voltage Vh also changes accordingly.

  The temperature dependence of the resistance can be realized using various known methods. For example, a temperature sensor such as a thermistor may be installed in the optical receiver 100, and the value of the second resistor 52 may be changed according to the temperature measured by the temperature sensor (digital resistor). Alternatively, a temperature sensitive resistance corresponding to that of the APD 12 may be used.

  As shown in FIG. 2, in this embodiment, the current detection circuit 18 includes a current mirror circuit including pnp transistors 33 and 34 and resistors 35 and 36 and a current-voltage conversion resistor 70.

In this current mirror circuit, when the photocurrent Iapd flows through the resistor 36 and the transistor 34, a mirror current corresponding to the photocurrent Iapd flows through the resistor 35 and the transistor 33. This mirror current is the detection current Id described above. The detection current Id is proportional to the photocurrent Iapd. The ratio of Id to Iapd is called a mirror current ratio and is determined according to the values of the resistors 35 and 36 and the size (collector size) of the transistors 33 and 34 used. Assuming that the transistors 33 and 34 are of the same type, if the values of the resistors 35 and 36 are represented as Re1 and Re2, respectively, the mirror current ratio m is represented as Re2 / Re1. Therefore,
Id = m · Iapd = (Re2 / Re1) · Iapd (3)
It is.

The detection current Id flows through the resistor 70 and causes a voltage drop. Thereby, the detection current Id is converted into the monitor voltage Vm. When the value of the resistor 70 is Rm, the monitor voltage Vm is
Vm = Rm.Id = Rm. (Re2 / Re1) .Iapd (4)
It is.

  The current I1 flowing through the resistor 51 branches to currents I2 and Iq at the node 28. The current I2 flows through the resistor 52, and the current Iq flows between the source and drain of the FET 72. The magnitude of the current Iq depends on the gate voltage of the FET 72.

  In the present embodiment, R1 = 520 kΩ, R2 = 10 kΩ, and the reference voltage of the control circuit 22 are 1.0 V at room temperature (25 ° C.). When the APD 12 is not receiving an optical signal, the photocurrent Iapd and the detection current Id are 0 mA, so the monitor voltage Vm is 0V. At this time, a current Iq of about 13 μA flows through the FET 72. The equivalent resistance of the FET 72 is calculated as 1Ω / 0.013 mA to 77Ω. The DC voltage Vh generated by the high voltage generation circuit 16 is (1V / (R1 = 10 kΩ) +0.013 mA) × (R1 = 520 kΩ) +1 to 59.7V. Since there is a voltage drop of about 0.5 V at the transistor 34 in the current detection circuit 18, when the APD 12 is not receiving an optical signal, a reverse bias voltage Vapd of about 59.2 V is applied to the APD 12. At this time, the multiplication factor of the APD 12 is about 9.5. Therefore, even when an optical signal is input to the optical receiver 100, good reception sensitivity can be obtained.

  When the APD 12 receives the optical signal, a photocurrent Iapd is generated, and the current detection circuit 18 generates a detection current Id accordingly. The detection current Id is converted into the monitor voltage Vm by the resistor 70. In this way, a positive monitor voltage Vm is applied to the gate of the FET 72 to determine a gate-source voltage (negative voltage). The higher the optical input intensity, the higher the monitor voltage Vm. Therefore, the current flowing between the drain and source of the FET 27 decreases and the equivalent resistance of the FET 72 increases. As a result, the parallel resistance Rc of the resistance of the FET 72 and the resistance 52 increases. According to the equations (1) and (2), when the parallel resistance Rc increases, the voltage dividing ratio D of the voltage dividing circuit 20 increases, and the voltage Vfb of the node 28 increases accordingly. Conversely, when the optical input intensity decreases, the monitor voltage Vm decreases, and the resistance of the FET 72 and the parallel resistance Rc decrease. As a result, the voltage division ratio D decreases and the node voltage Vfb decreases. Thus, the node voltage Vfb varies according to the light input intensity.

  In the present embodiment, Re1 = Re2 = 1 kΩ so that the mirror current ratio m of the current detection circuit 18 is about 1. Rm = 5 kΩ. Therefore, as shown in the equation (4), when the photocurrent Iapd is 300 μA, the monitor voltage Vm is about 1.5V. When the monitor voltage Vm increases from 0V to 1.5V, the FET 72 is gradually cut off, and the current Iq is reduced to about 2 μA. Since the control circuit 22 controls the DC voltage Vh so as to keep Vfb at 1.0 V, the DC voltage Vh is Vh = ((Vfb = 1V) / (R2 = 10 kΩ) +0.002) × (R1 = From 520 kΩ) + 1V to 52V, the DC voltage Vh is reduced. As a result, the DC voltage Vh is controlled to 52V. Compared to the case where there is no optical input, the DC voltage Vh is reduced by 7.7V.

  FIG. 3 is a graph showing the output voltage Vh characteristics of the high voltage generation circuit 16 of the present embodiment. The photocurrent Iapd is 250 μA or less, and the output voltage Vh changes depending on the photocurrent Iapd. When the photocurrent Iapd is 250 μA or more, the output voltage Vh does not change. This is because the FET 72 is completely turned off.

  Thus, the output voltage Vh of the high voltage generation circuit 16 decreases as the optical input intensity increases, and the reverse bias voltage Vapd applied to the APD 12 also decreases accordingly. The multiplication factor of photoelectric conversion of the APD 12 is lowered in accordance with the decrease of the reverse bias voltage Vapd. Therefore, the multiplication factor of the APD 12 is reduced as the optical input intensity increases. As a result, the power consumption of the entire optical receiving circuit is reduced from the case where the optical input intensity is small to the large case, and at the same time, the magnitude of the photocurrent Iapd flowing through the APD 12 is appropriately suppressed to prevent the APD 12 from being damaged. can do.

  The adjustment of the bias level of the APD is performed by arranging a series resistor in the bias line as disclosed in JP-A-11-284445 and JP-A-2004-71982 to reduce the voltage drop according to the photocurrent to a high voltage. It can also be realized by giving the output voltage of the generating circuit. It is also possible to monitor the voltage drop and turn off the high voltage to protect the APD. However, this method does not adjust the output voltage of the high voltage generation circuit in accordance with the photocurrent, so it is difficult to reduce power consumption. On the other hand, in the present embodiment, the output voltage Vh of the high voltage generation circuit 16 is reduced in accordance with the increase in the photocurrent Iapd, so that it is possible to easily reduce the power consumption of the bias control circuit 10. .

  FIG. 4 is a graph showing power consumption at room temperature for both the present embodiment and the bias control circuit of the conventional example (Japanese Patent Laid-Open No. 2004-71982). Although both bias control circuits tend to increase power consumption as the photocurrent Iapd increases, the bias control circuit of this embodiment has lower power consumption. FIG. 5 is a graph showing the power consumption reduction rate of this embodiment with respect to the conventional example. In the bias control circuit 10 of the present embodiment, when the photocurrent Iapd is about 400 μA, the power consumption is reduced by 20 mW, and a reduction in power consumption of 13% is achieved as a reduction rate. The data shown in FIGS. 3 to 5 are measured using an APD whose optimum bias voltage is 60 V when no optical signal is received at room temperature.

Second Embodiment Hereinafter, a second embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing the optical receiver 200 and the bias control circuit 10a of this embodiment. The bias control circuit 10a has a configuration in which the voltage dividing circuit 20 is replaced with a voltage dividing circuit 20a in the bias control circuit 10 of the first embodiment.

  The voltage dividing circuit 20 a is different from the voltage dividing circuit 20 in that an FET 73 is provided instead of the FET 72. The FET 73 is an n-type FET. The FET 73 is connected in parallel with the first resistor 51. The gate of the FET 73 is connected to the output terminal of the current detection circuit 18 and supplied with the monitor voltage Vm.

The voltage dividing circuit 20 a divides the DC voltage Vh by a certain voltage dividing ratio D and outputs the node voltage Vfb to the node 28. The voltage division ratio D depends not only on the resistances 51 and 52 but also on the resistance between the drain and source of the FET 73. When the values of the resistors 51 and 52 are expressed as R1 and R2, respectively, and the value of the resistance of the FET 73 is expressed as R3, in this embodiment, the voltage dividing ratio D is changed to the expression (1) of the first embodiment,
D = R2 / (R2 + Rc) (5)
It is expressed. Therefore, in this embodiment, the node voltage Vfb is replaced with the expression (2) in the first embodiment,
Vfb = Vh · D = Vh · R2 / (R2 + Rc) (6)
It is expressed. Here, Rc is a parallel resistance of the first resistor 51 and the FET 73.

  When the APD 12 is not receiving an optical signal, the monitor current Vm is 0 V because the photocurrent Iapd and the detection current Id are 0 mA. At this time, since the gate-source voltage of the FET 73 is smaller than the threshold value, the FET 73 is turned off, and the voltage division ratio D is R2 / (R2 + R1).

  When the APD 12 receives an optical signal, a photocurrent Iapd is generated, and a monitor voltage Vm is generated accordingly. In this way, a positive monitor voltage Vm is applied to the gate of the FET 73 to determine a gate-source voltage (positive voltage). The higher the optical input intensity, the higher the monitor voltage Vm, the FET 73 becomes conductive, and the parallel resistance Rc decreases.

  Since the control circuit 22 changes the DC output voltage Vh so as to keep the node voltage Vfb constant, the output voltage Vh decreases as the optical input intensity increases, and conversely increases as the optical input intensity decreases. .

Third Embodiment Hereinafter, a third embodiment of the present invention will be described. FIG. 7 is a circuit diagram showing the optical receiver 300 and the bias control circuit 10b of this embodiment. The bias control circuit 10b has a configuration in which the voltage dividing circuit 20a is replaced with a voltage dividing circuit 20b in the bias control circuit 10a of the second embodiment.

  The voltage dividing circuit 20b differs from the voltage dividing circuit 20a in that the drain of the FET 73 is connected to a constant reference voltage 74. A current Iq flows between the drain and source of the FET 73, and a current I1 flows through the first resistor 51. The current Iq depends on the gate bias applied to the FET 73. The currents Iq and I1 merge at the node 28 and become the current I2. The current I2 flows through the second resistor 52.

  In this embodiment, when the optical input intensity increases and the photocurrent Iapd increases, the monitor voltage Vm increases, and as a result, the current Iq that flows through the FET 73 increases. When the current I2 increases, the node voltage Vfb increases. When the light input intensity decreases, the monitor voltage Vm decreases, the current Iq decreases, and the node voltage Vfb decreases.

  The control circuit 22 changes the DC output voltage Vh of the high voltage generation circuit 16 so as to cancel the increase / decrease in the node voltage Vfb. Therefore, as in the first embodiment, the output voltage Vh decreases as the optical input intensity increases and the accompanying node voltage Vfb increases. Conversely, the optical input intensity decreases and the associated node voltage Vfb decreases. Rise according to. As a result, this embodiment can also obtain the same advantages as those of the first embodiment.

  In the present embodiment, an FET 72 that is a p-type MOSFET may be used instead of the FET 73 that is an n-type MOSFET. At this time, the reference voltage 74 is lower than the node potential Vfb. Therefore, the current I1 flowing through the first resistor 51 branches into currents I2 and Iq at the node 28. The current I2 flows through the second resistor 52, and the current Iq flows between the source and drain of the FET 72.

  The present invention has been described in detail based on the embodiments. However, the present invention is not limited to the above embodiment. The present invention can be variously modified without departing from the gist thereof.

  For example, in the above embodiment, the drain-source resistance of the field effect transistor is controlled according to the monitor voltage Vm. However, a bipolar transistor can be used instead of the field effect transistor. In that case, the current detection circuit 18 does not need to have the resistor 70, and supplies the detection current Id to the base of the bipolar transistor. The resistance between the collector and the emitter of the bipolar transistor changes according to the current supplied to the base. Therefore, by connecting such a bipolar transistor to the resistor 51 or 52, the voltage dividing ratio of the voltage dividing circuit 20 can be changed according to the detection current Id. As a result, a bias control circuit having advantages similar to those of the above embodiment can be obtained.

It is the schematic which shows the bias control circuit of 1st Embodiment. It is a circuit diagram showing a bias control circuit of the first embodiment. It is a graph which shows the output voltage of the high voltage generation circuit of 1st Embodiment. It is a graph which shows the power consumption of this embodiment and a prior art example. It is a graph which shows the reduction rate of the power consumption of this embodiment with respect to a prior art example. It is a circuit diagram which shows the bias control circuit of 2nd Embodiment. It is a circuit diagram which shows the bias control circuit of 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Bias control circuit, 12 ... Avalanche photodiode (APD), 14 ... Preamplifier, 15 ... Bias line, 16 ... High voltage generation circuit, 18 ... Current detection circuit, 20 ... Voltage division circuit, 22 ... Control circuit, 26, 28 ... node, 51, 52 ... resistor, 72 ... transistor (FET), 100 ... optical receiver.

Claims (3)

A bias control circuit for an avalanche photodiode,
A voltage source for generating a variable DC voltage applied to the avalanche photodiode;
A current mirror circuit that detects a photocurrent generated by the avalanche photodiode, and a current detection unit that generates a monitor signal according to the photocurrent;
A voltage dividing circuit for dividing the DC voltage at a voltage dividing ratio according to the monitor signal;
A control circuit for controlling the voltage source according to the output of the voltage dividing circuit;
With
The voltage dividing circuit includes:
First and second resistors connected in series with each other to divide the DC voltage;
A variable resistance element connected to the first or second resistor and having a resistance that changes in accordance with the monitor signal;
Including a bias control circuit. The variable resistance element is a transistor to which the monitor signal is input.
The bias control circuit according to claim 1.   The bias control circuit according to claim 1, wherein the first or second resistor has a temperature characteristic that compensates for a temperature characteristic of the avalanche photodiode.

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