JP2007158370A - Method of manufacturing semiconductor device having gate with nitride film sidewalls - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a gate with nitride film sidewalls whose shape of shoulders of a stopper nitride film is vertically formed and which can reduce recession of the nitride film during contact hole etching. <P>SOLUTION: In the method of manufacturing the semiconductor device having the gate with nitride film sidewalls by forming a contact by a self-alignment process; a stopper nitride film is deposited after forming a gate 31 with an offset nitride film 32; after performing sidewall etching, an insulating film 34 is formed and a CMP process is performed; an interlayer dielectric 36 is formed on the further planarized gate 31; and accordingly, the CMP process after forming the interlayer dielectric 36 can be eliminated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a gate with a nitride film sidewall.

  At present, miniaturization of design rules is progressing along with the high integration of semiconductor devices (semiconductor devices). Among them, the demand for reducing the hole diameter for contact hole etching is very high.

  The gate interval in the currently developed 0.20 μm device is designed to be 0.22 μm, but the dimension required for the diameter of the contact hole formed between the gates is about 0.06 μm. The limit of photolithography patterning is about 0.18 μm even if super-resolution technology is used, and it is impossible to form a hole of 0.1 μm or less by photolithography alone.

  Therefore, patterning of 0.1 μm or less is performed by PSC (Poly-Si Shrunken Contact) using a polysilicon side wall, but when further miniaturization progresses, it is very difficult to form a contact hole by PSC. Become. This is because the alignment margin of photolithography cannot fall below 0.07 to 0.08 μm due to misalignment of the apparatus, mask accuracy, securing of a short-circuit prevention film thickness, and the like.

  With mechanical alignment such as current steppers and scanners, it is difficult to improve alignment accuracy rapidly, and contact holes of 0.1 μm or less, which is expected to be greatly needed in future devices, can be stably photolithography. Patterning is not possible with technology alone.

  Thus, the SAC (Self Aligned Contact) process has been conceived from the limit of the alignment accuracy of photolithography. The SAC process is a technique for improving the alignment accuracy of photolithography by forming an offset nitride film on the gate and forming a nitride film sidewall on the gate sidewall when forming the gate, and using these nitride films as stopper films. is there.

  FIG. 6 is a process diagram for forming a gate structure in a conventional SAC process.

  First, as shown in FIG. 6A, a gate oxide film 2, a polysilicon film 3, a WSi film 4, and an offset nitride film 5 are sequentially formed on a silicon substrate 1.

  Next, as shown in FIG. 6B, the offset nitride film 5, the WSi film 4, the polysilicon film 3, and the gate oxide film 2 are processed by photolithography and etching to obtain a gate structure, and then a stopper nitride film. 6 is deposited.

  Next, as shown in FIG. 6C, a nitride film sidewall 7 is formed using the stopper nitride film 6.

  Here, a process condition in which the nitride film serves as a stopper, that is, a condition with a high nitride film / oxide film selection ratio is required. A high selectivity can be achieved by changing the gas species and depositing a fluorocarbon film on the nitride film as a protective film, but the problem is that sputtering by incident ions occurs.

  Since the nitride film sidewall 7 formed on the gate has a curvature, it is very easily sputtered by incident ions, and the nitride film / oxide film selection ratio is greatly reduced. Since the sputtering rate greatly depends on the curvature, reducing the curvature of the sidewall 7 is very useful for suppressing the sputtering.

In addition, when further miniaturization progresses, it can be considered that an etch stop occurs in the slit portion between the gates. One of the causes of etch stop is that the flux of incident ions is small, but if the flux is too large, sputtering increases. The key to the fine SAC process is how to solve the trade-off between etch stop and sputtering.
None

  However, in the SAC process using the nitride film sidewall described above, the shoulder of the nitride film on the sidewall always has a curved shape, so that the shoulder is retracted by sputtering of incident ions during contact hole etching. As shown in FIG. 7, there is a problem that a short circuit with the gate 8 occurs. In FIG. 7, 9A is an interlayer insulating film, and 9B is a resist pattern.

  The amount of retreat by ion sputtering increases as the shape has a large curvature, and conversely decreases as the shape becomes vertical. Currently, contact hole etching in the SAC structure is performed under process conditions such that a fluorocarbon film is formed as a protective film on the nitride film, but the hole diameter is reduced to a level at which etch stoppage is noticeable due to further miniaturization. Therefore, it is necessary to increase the flux of incident ions in order to improve the hole etching.

  In the side wall with a large curvature, it is considered that the sputtering is promoted by the increase of ion flux, and the selectivity is decreased. Therefore, if a vertical sidewall shape with a low sputtering rate can be applied to the SAC process, it is possible to reduce the amount of receding due to ion sputtering and realize high selectivity.

  The present invention eliminates the above-described problems, and manufactures a semiconductor device having a gate with a nitride film sidewall in which the shape of the shoulder of the stopper nitride film is made vertical, and the recession of the nitride film during contact hole etching can be reduced. It aims to provide a method.

In order to achieve the above object, the present invention provides
[1] In a method of manufacturing a semiconductor device having a gate with a nitride film sidewall in which a contact is formed by a self-alignment process, after forming a gate with an offset nitride film, depositing a stopper nitride film, etching the sidewall, The interlayer insulating film is formed on the flattened gate, and the CMP process after the generation of the interlayer insulating film is omitted.

  [2] In a method of manufacturing a semiconductor device having a gate with a nitride film sidewall in which a contact is formed by a self-alignment process, after forming a gate with a sacrificial film on the offset nitride film, a stopper nitride film is deposited, After the etching, an insulating film is generated and subjected to a CMP process. Further, an interlayer insulating film is generated on the planarized gate, and the CMP process after the generation of the interlayer insulating film is omitted.

  According to the present invention, the following effects can be achieved.

  (A) The shape of the shoulder of the stopper nitride film is substantially vertical, and the recession of the nitride film due to contact hole etching can be reduced. As a result, the margin of the contact hole etching time can be increased, and etching can be performed by extending the etching time even in a fine SAC structure and process conditions that are easily affected by the microloading effect. Further, since the nitride film / oxide film selectivity increases, the nitride film can be made thinner.

  (B) The CMP step in (A) above is not performed before the sidewall etching, but is performed after the sidewall etching, whereby the recess of the nitride film shoulder due to the contact hole etching can be further reduced.

  Further, since the CMP process is performed after the sidewall etching, it is possible to set the CMP polishing amount necessary for verticalizing the shoulder of the nitride film in consideration of the thickness of the offset nitride film (on the gate).

  (C) By forming an insulating film on the entire surface of the wafer before the CMP process, non-uniform polishing amount due to pattern density can be suppressed.

  In addition, by performing the CMP process performed after the generation of the interlayer insulating film in the conventional process at the time of verticalizing the sidewalls, the vertical shape of the nitride sidewalls can be changed only by changing the order of the steps without changing the total number of steps. And planarization of the interlayer insulating film can be performed simultaneously.

  Further, this allows the thickness of the interlayer insulating film to be set not by the CMP polishing rate but by the deposition rate of the interlayer insulating film, thereby enabling more precise control of the film thickness.

  (D) By forming a sacrificial film on the offset nitride film before forming the gate and then performing gate etching to form the gate, the uniformity of the polishing amount due to the film quality during the CMP process can be improved. In the CMP process, the sidewall nitride film is also polished at the same time, but compared with the above (C), the difference in the polishing amount in the wafer due to the film quality is small. As in the case of (C), the interlayer insulating film is formed after the CMP at the same time as the planarization of the interlayer insulating film, whereby the interlayer insulating film thickness can be controlled by the deposition rate of the insulating film.

  (E) The alignment in the word line parallel direction, which is a defect of the SAC structure, is guaranteed by the stopper nitride film. Since the nitride film is formed after the sidewall etching, the stopper nitride film on the gate is polished by CMP, but remains on the side wall and the base of the gate. The active region and the element isolation region are not scraped by the nitride film remaining on the base during the contact hole etching.

  A method of manufacturing a semiconductor device having a gate with a nitride film sidewall that forms a contact by a self-alignment process of the present invention includes: forming a gate with an offset nitride film; depositing a stopper nitride film; etching a sidewall; Then, a CMP process is performed, an interlayer insulating film is generated on the planarized gate, and the CMP process after the generation of the interlayer insulating film is omitted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a process diagram for forming a gate structure in a SAC process according to a first embodiment of the present invention.

  (1) First, as shown in FIG. 1A, a gate (gate material) 11 is formed on a silicon substrate 10 and an offset nitride film 12 is formed on the gate 11 before forming the gate. Thereafter, gate etching is performed to form a gate with an offset nitride film 12, and a nitride film is deposited on the gate. The thickness of the offset nitride film 12 is made thicker than the conventional one in consideration of film thickness reduction in the CMP process.

  (2) Next, after depositing the stopper nitride film 13, as shown in FIG. 1B, in order to verticalize the shoulder of the nitride film having a curvature that is easily ion-sputtered, CMP (chemical mechanical polishing) is performed here. ) Process.

  (3) Thereafter, as shown in FIG. 1C, sidewall nitride film etching is performed to form nitride film sidewalls 14.

  As described above, according to the first embodiment, the shape of the shoulder portion of the stopper nitride film (side wall) is substantially vertical, and the recession of the nitride film due to contact hole etching can be reduced. As a result, the margin of the contact hole etching time can be increased, and etching can be performed by extending the etching time even in a fine SAC structure and process conditions that are easily affected by the microloading effect. Further, since the nitride film / oxide film selectivity increases, the nitride film can be made thinner.

  Next, a second embodiment of the present invention will be described.

  FIG. 2 is a process diagram for forming a gate structure in the SAC process according to the second embodiment of the present invention.

  (1) First, as shown in FIG. 2A, a gate 21 is formed on the silicon substrate 20 and an offset nitride film 22 is formed on the gate 21 before forming the gate. Thereafter, gate etching is performed to form a gate with an offset nitride film 22, and a stopper nitride film 23 is deposited on the gate. The thickness of the offset nitride film 22 is made thicker than before in consideration of film thickness reduction in the CMP process.

  (2) Next, as shown in FIG. 2B, after forming a stopper nitride film, a nitride film sidewall 24 is formed by sidewall etching.

  (3) Next, as shown in FIG. 2C, the CMP process is performed after the sidewall etching.

  As described above, in the second embodiment, the CMP process is performed not after the nitride film sidewall etching but after the nitride film sidewall etching. In the method of performing the CMP process after depositing the nitride film and then performing the sidewall etching as in the first embodiment, it is considered that the stopper nitride film verticalized by the CMP process has a curvature again by the sidewall etching. It is done.

  Therefore, if the CMP process is performed after sidewall etching as in the second embodiment, the shape becomes the final shape and final film thickness of the stopper nitride film, so that a more vertical nitride film sidewall can be formed. .

  As described above, according to the second embodiment, the CMP process is not performed before the sidewall etching, but is performed after the sidewall etching, so that the recess of the nitride film shoulder due to the contact hole etching can be further reduced.

  Further, since the CMP process is performed after the sidewall etching, it is possible to set the CMP polishing amount necessary for verticalizing the shoulder of the nitride film in consideration of the thickness of the offset nitride film (on the gate).

  Next, a third embodiment of the present invention will be described.

  FIG. 3 is a process diagram for forming a gate structure in the SAC process according to the third embodiment of the present invention.

  (1) First, as shown in FIG. 3A, a gate 31 is formed on the silicon substrate 30 and an offset nitride film 32 is formed on the gate 31 before forming the gate. Thereafter, gate etching is performed to form a gate 31 with an offset nitride film 32, and a nitride film is deposited on the gate 31. The thickness of the offset nitride film 32 is made thicker than the conventional one in consideration of film thickness reduction in the CMP process. Next, after forming a stopper nitride film (not shown), a nitride film sidewall 33 is formed by sidewall etching. Then, an insulating film 34 is deposited thereon.

  (2) Next, as shown in FIG. 3B, a CMP process is performed to form a gate having the nitride film side wall 33.

  (3) Next, as shown in FIG. 3C, an interlayer insulating film 36 is formed, and then a resist is applied to form a resist pattern 37 for forming contact holes.

  In the CMP process in the second embodiment, it is conceivable that non-uniformity of the polishing amount in the wafer occurs due to the pattern density. Therefore, in the third embodiment, in order to prevent this problem, the insulating film 34 is formed on the entire surface of the wafer after the sidewall etching and before the CMP process. This reduces the non-uniformity of the polishing amount in the wafer due to the pattern density. Further, by forming the interlayer insulating film 36 after the CMP process, planarization can be expected without performing the CMP process after the generation of the interlayer insulating film 36.

  As described above, according to the third embodiment, by forming the insulating film on the entire surface of the wafer before the CMP process, it is possible to suppress non-uniform polishing amount due to the pattern density. In addition, by performing the CMP process performed after the generation of the interlayer insulating film in the conventional process at the time of verticalizing the sidewalls, the vertical shape of the nitride sidewalls can be changed only by changing the order of the steps without changing the total number of steps. And planarization of the interlayer insulating film can be performed simultaneously.

  Further, this allows the thickness of the interlayer insulating film to be set not by the CMP polishing rate but by the deposition rate of the interlayer insulating film, thereby enabling more precise control of the film thickness.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 4 is a process diagram for forming a gate structure in the SAC process according to the fourth embodiment of the present invention.

  (1) First, as shown in FIG. 4A, before forming the gate, an offset nitride film 42 is formed on the gate 41 on the silicon substrate 40, and a sacrificial film 43 is formed thereon. Thereafter, gate etching is performed to form a stopper nitride film (not shown), and then a nitride film sidewall 44 is formed by sidewall etching. Then, an insulating film 45 is deposited thereon.

  (2) Next, as shown in FIG. 4B, a CMP process is performed to form a gate having a nitride film sidewall 44.

  (3) Next, as shown in FIG. 4C, an interlayer insulating film 47 is formed, and then a resist is applied to form a resist pattern 48 for forming a contact hole.

  In the CMP process in the third embodiment, there is a concern that the polishing amount may be non-uniform due to the film quality. When the CMP process is performed after the sidewall etching as in the second embodiment, the residual film thickness of the offset nitride film (on the gate) can be set by the CMP polishing amount, thereby reducing the difference in polishing amount due to the film quality. Therefore, the offset nitride film is thinned, and a sacrificial film similar to the insulating film formed on the entire surface of the wafer before the CMP process is formed on the offset nitride film. Gate etching is performed to form an interlayer insulating film on the planarized structure through stopper nitride film deposition, sidewall nitride film etching, insulating film generation, and CMP processes, as in the third embodiment. To do.

  As described above, according to the fourth embodiment, the sacrificial film 43 is formed on the offset nitride film 42 before forming the gate, and then the gate is formed by performing gate etching. Uniformity can be increased. In the CMP process, the nitride film sidewall is also polished at the same time, but the difference in the polishing amount in the wafer due to the film quality is small as compared with the third embodiment. As in the third embodiment, the interlayer insulating film is formed after CMP at the same time as the planarization of the interlayer insulating film, so that the interlayer insulating film thickness can be controlled by the deposition rate of the insulating film.

  Next, a fifth embodiment of the present invention will be described.

  FIG. 5 is a process diagram for forming a gate structure in the SAC process according to the fifth embodiment of the present invention.

  (1) First, as shown in FIG. 5A, an offset nitride film 52 is formed on the gate 51 on the silicon substrate 50 before the gate is formed. Thereafter, gate etching is performed to form a stopper nitride film (not shown), and then a nitride film sidewall 53 is formed by sidewall etching. Further, a thinned nitride film 54 is formed thereon.

  (2) Next, as shown in FIG. 5B, a CMP process is performed to form a gate having a nitride film side wall 53.

  The SAC structure described so far can absorb the misalignment of photolithography in the direction perpendicular to the word line, but has no structural advantage in the parallel direction of the word line. Therefore, a thin nitride film is formed as a stopper after the sidewall etching, and then a CMP process is performed to make the sidewall vertical. A nitride film may be formed after CMP, but the shoulder of the nitride film has a curvature, so it is important to reduce the thickness of the nitride film 54 as a stopper.

  Thus, according to the fifth embodiment, alignment in the word line parallel direction, which is a defect of the SAC structure, is guaranteed by the stopper nitride film. Since the nitride film is formed after the sidewall etching, the stopper nitride film on the gate is polished by CMP, but remains on the side wall and the base of the gate. The active region and the element isolation region are not scraped by the nitride film remaining on the base during the contact hole etching.

  In addition, this invention is not limited to the said Example, A various deformation | transformation is possible based on the meaning of this invention, and these are not excluded from the scope of the present invention.

  The method for manufacturing a semiconductor device of the present invention can be used as a method for manufacturing a semiconductor device having a gate with a nitride film sidewall.

It is a formation process figure of the gate structure in the SAC process which shows the 1st example of the present invention. It is a formation process figure of the gate structure in the SAC process which shows the 2nd example of the present invention. It is a formation process figure of the gate structure in the SAC process which shows the 3rd example of the present invention. It is a formation process figure of the gate structure in the SAC process which shows the 4th example of the present invention. It is a formation process figure of the gate structure in the SAC process which shows the 5th example of the present invention. It is a formation process figure of the gate structure in the conventional SAC process. It is explanatory drawing of the problem of a prior art.

Explanation of symbols

10, 20, 30, 40, 50 Silicon substrate 11, 21, 31, 41, 51 Gate 12, 22, 32, 42, 52 Offset nitride film 13, 23 Stopper nitride film 14, 24, 33, 44, 53 Nitride film Side walls 34, 45 Insulating film 36, 47 Interlayer insulating film 37, 48 Resist pattern 43 Sacrificial film 54 Thinned nitride film

Claims (2)

In a method of manufacturing a semiconductor device having a gate with a nitride film sidewall that forms a contact by a self-alignment process,
After generating a gate with an offset nitride film, a stopper nitride film is deposited, sidewall etching is performed, an insulating film is generated and CMP is performed, and an interlayer insulating film is generated on the planarized gate, and the interlayer insulating film is formed. A method of manufacturing a semiconductor device, wherein CMP processing after film formation is omitted. In a method of manufacturing a semiconductor device having a gate with a nitride film sidewall that forms a contact by a self-alignment process,
After generating a gate with a sacrificial film on the offset nitride film, a stopper nitride film is deposited, sidewall etching is performed, an insulating film is generated and CMP is performed, and an interlayer insulating film is formed on the planarized gate. A method for manufacturing a semiconductor device, characterized in that a CMP process after the generation and the interlayer insulating film is omitted is omitted.

Images