JP2007157931A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To mixedly mount a salicided element and an unsalicided element on the same substrate while suppressing an increase in a chip area. <P>SOLUTION: Source and drain layers 17a and 17b provided with silicide layers 19a, 19b and 19c, and a gate electrode 14 are formed on the semiconductor substrate 11, an amorphous semiconductor layer 33 is formed on an insulation film 31 so that the inside of a concave portion 32 is filled, and the amorphous semiconductor layer 33 is irradiated with laser to melt and crystalize the amorphous semiconductor layer 33. In this way, a substantially single crystal semiconductor particle 34 is formed around the concave portion 32, and the unsalicided element is formed on the substantially single crystal particle 34. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and is particularly suitable for application to a three-dimensional integrated structure of a semiconductor device.

In a conventional semiconductor device, salicide technology is used in order to suppress an increase in parasitic resistance due to miniaturization of an integrated circuit. Further, for example, Patent Document 1 discloses that a source region and a drain region can be activated by a heat treatment at a relatively low temperature, and a high-performance thin film transistor can be obtained. A method is disclosed in which a semiconductor film is formed and then a heat treatment of the semiconductor film is performed to generate substantially single crystal grains centered on the starting point.
JP-A-2005-294628

However, when a salicided transistor and an electrostatic protection circuit are mixedly mounted on the same substrate, it is necessary to make the electrostatic protection circuit non-salicide in order to increase the resistance of the electrostatic protection circuit. There is a problem that the area is increased and the manufacturing process is complicated, leading to an increase in cost.
Accordingly, an object of the present invention is to provide a salicided element (hereinafter referred to as a salicide element) and a non-salicide element (referred to as a non-salicide element) on the same substrate while suppressing an increase in chip area. A semiconductor device and a method for manufacturing the semiconductor device that can be mixedly mounted on the semiconductor device.

In order to solve the above-described problem, a semiconductor device according to one embodiment of the present invention includes a salicide element formed over a semiconductor substrate, an amorphous semiconductor layer stacked over the salicide element, and the non-side semiconductor layer. And a non-salicide element formed on the crystalline semiconductor layer.
As a result, a non-salicide element can be stacked on a salicide element, and the salicide element and the non-salicide element are mixedly mounted on the same substrate without arranging the salicide element and the non-salicide element on the same plane. Is possible. For this reason, it is possible to suppress an increase in the chip area, and it is possible to perform a non-salicide process without being affected by the salicide process. Can be reduced.

In addition, according to the semiconductor device of one embodiment of the present invention, the salicide element formed over the semiconductor substrate, the substantially single crystal semiconductor grains stacked on the salicide element, and the substantially single crystal semiconductor grains are formed. And a non-salicide element.
Accordingly, it is possible to form a substantially single crystal semiconductor grain on the salicide element while keeping the temperature of the semiconductor substrate at about 400 ° C. or less, and it is possible to form a non-salicide element on the substantially single crystal semiconductor grain. However, a non-salicide element can be stacked on the salicide element. Therefore, the salicide element and the non-salicide element can be mounted on the same substrate without arranging the salicide element and the non-salicide element on the same plane, and an increase in the chip area can be suppressed. In addition, the electrical characteristics of the non-salicide element can be improved without adversely affecting the characteristics of the salicide element.

The semiconductor device according to one embodiment of the present invention is characterized in that the substantially single crystal semiconductor grain is an intrinsic semiconductor grain.
Thereby, activation annealing of the impurities implanted into the substantially single crystal semiconductor grains can be performed while maintaining the temperature of the semiconductor substrate at about 450 ° C. or lower. For this reason, it is possible to stack many single crystal semiconductor grains while adopting metal wiring and metal gate, and to realize miniaturization of semiconductor elements while suppressing the influence of propagation delay. It becomes possible.

In addition, according to the semiconductor device of one aspect of the present invention, the first substantially single crystal semiconductor grain stacked on the insulator, the salicide element formed on the first substantially single crystal semiconductor grain, and the salicide A second substantially single crystal semiconductor grain stacked on the element, and a non-salicide element formed on the second substantially single crystal semiconductor grain.
As a result, a non-salicide element can be stacked on a salicide element, and the salicide element and the non-salicide element are mixedly mounted on the same substrate without arranging the salicide element and the non-salicide element on the same plane. Is possible. For this reason, it is possible to suppress an increase in the chip area, and it is possible to perform a non-salicide process without being affected by the salicide process. Can be reduced.

According to the semiconductor device of one embodiment of the present invention, the non-salicide element is an electrostatic protection circuit.
Accordingly, the salicide element and the electrostatic protection circuit can be mixedly mounted on the same substrate without forming the electrostatic protection circuit on the semiconductor substrate on which the salicide element is formed. For this reason, it is possible to increase the resistance of the electrostatic protection circuit while suppressing complication of the manufacturing process, and it is possible to stably protect the semiconductor device from breakdown due to static electricity while suppressing an increase in cost. .

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a salicide element over a semiconductor substrate, a step of forming an insulating film over the salicide element, and an amorphous layer over the insulating film And a step of forming a non-salicide element on the amorphous semiconductor layer.
As a result, a non-salicide element can be stacked on a salicide element, and the salicide element and the non-salicide element are mixedly mounted on the same substrate without arranging the salicide element and the non-salicide element on the same plane. Is possible. For this reason, it is possible to suppress an increase in the chip area, and it is possible to perform a non-salicide process without being affected by the salicide process. Can be reduced.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a salicide element on a semiconductor substrate, a step of forming an insulating film on the salicide element, and a grain filter on the insulating film Forming an amorphous semiconductor layer on the insulating film so as to embed the grain filter, and performing laser irradiation on a region of the amorphous semiconductor layer including the grain filter, Forming a substantially single crystal semiconductor grain in which the amorphous semiconductor layer around the grain filter is substantially single crystal grain; and forming a non-salicide element on the substantially single crystal semiconductor grain. Features.

  Accordingly, it is possible to form a substantially single crystal semiconductor grain on the salicide element while keeping the temperature of the semiconductor substrate at about 400 ° C. or less, and it is possible to form a non-salicide element on the substantially single crystal semiconductor grain. However, a non-salicide element can be stacked on the salicide element. Therefore, the salicide element and the non-salicide element can be mounted on the same substrate without arranging the salicide element and the non-salicide element on the same plane, and an increase in the chip area can be suppressed. In addition, the electrical characteristics of the non-salicide element can be improved without adversely affecting the characteristics of the salicide element.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the non-salicide element on the single crystal semiconductor grain is performed on the single crystal semiconductor grain by a direct oxidation method using high-density plasma. A step of forming a gate insulating film; a step of forming a gate electrode on the gate insulating film; a step of implanting impurities into the single crystal semiconductor grains using the gate electrode as a mask; and a step of implanting the single crystal semiconductor grains. And a step of performing annealing for impurity activation at a temperature of 450 ° C. or lower.

  Thus, a transistor can be formed in a substantially single crystal semiconductor grain while keeping the temperature of the semiconductor substrate at about 450 ° C. or lower. For this reason, it is possible to stack over many layers of transistors formed on a substantially single crystal semiconductor grain, using metal wiring and metal gates, and miniaturizing transistors while suppressing the effects of propagation delay It becomes possible to do.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1 to 3 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
In FIG. 1A, the element isolation insulating film 12 is formed on the semiconductor substrate 11 by performing selective oxidation of the semiconductor substrate 11. The material of the semiconductor substrate 11 can be selected from, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, or ZnSe. Then, the gate insulating film 13 is formed on the semiconductor substrate 11 by performing thermal oxidation of the semiconductor substrate 11. As the material of the gate insulating film 13, for example, other _{SiO 2, HfO 2, HfON,} HfAlO, HfAlON, HfSiO, HfSiON, ZrO 2, ZrON, ZrAlO, ZrAlON, ZrSiO, ZrSiON, Ta 2 O 5, Y Dielectric materials such as ₂ O ₃ , (Sr, Ba) TiO ₃ , LaAlO ₃ , SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ , and Pb (Zi, Ti) O ₃ may be used.

Then, a polycrystalline silicon layer is formed on the semiconductor substrate 11 on which the gate insulating film 13 is formed by a method such as CVD, and the polycrystalline silicon layer is patterned by using a photolithography technique and a dry etching technique. Then, the gate electrode 14 is formed on the gate insulating film 13. Then, by using the gate electrode 14 as a mask, impurities such as As, P, B, and BF ₂ are ion-implanted into the semiconductor substrate 11, thereby forming LDD (Lightly Doped Drain) layers 15a and 15b made of a low concentration impurity introduction layer. It is formed on both sides of the gate electrode 14.

Next, as shown in FIG. 1B, an insulating layer is formed by a method such as CVD on the semiconductor substrate 11 on which the LDD layers 15a and 15b are formed, and anisotropic etching such as RIE is performed. A sidewall 16 is formed on the sidewall of the gate electrode 14. Then, impurities such as As, P, B, and BF ₂ are ion-implanted into the semiconductor substrate 11 using the gate electrode 14 and the sidewall 16 as a mask, so that source / drain layers 17a and 17b made of high-concentration impurity introduction layers are formed. Are formed on both sides of the sidewall 16.

Next, as shown in FIG. 1C, a metal layer 18 is formed on the semiconductor substrate 11 on which the source / drain layers 17a and 17b are formed by a method such as sputtering. Here, the metal layer 18 reacts with the semiconductor substrate 11 and can be alloyed. For example, a transition metal such as a Ti film, a Co film, a W film, a Mo film, a Ni film, or a Pt film can be used. .
Next, as shown in FIG. 1D, the semiconductor substrate 11 on which the metal layer 18 is formed is subjected to a heat treatment to cause a salicide reaction of the metal layer 18 to thereby form the source / drain layers 17a and 17b and the gate electrode. Silicide layers 19a, 19b, and 19c are formed on 14 respectively. When the semiconductor substrate 11 is other than Si, an interstitial compound layer of each semiconductor substrate material and the transition metal is formed instead of the silicide layer.

Next, as shown in FIG. 1E, the unreacted metal layer 18 is removed by performing wet etching on the semiconductor substrate 11 on which the silicide layers 19a, 19b, and 19c are formed.
Next, as shown in FIG. 2A, an interlayer insulating layer 21 is deposited on the entire surface of the semiconductor substrate 11 by a method such as CVD. Then, by patterning the interlayer insulating layer 21 using a photolithography technique and an etching technique, an opening 22 exposing the silicide layers 19a and 19b is formed in the interlayer insulating layer 21. Then, a conductive film embedded in the opening 22 is formed on the interlayer insulating layer 21 by a method such as sputtering, and the conductive layers are patterned using a photolithography technique and an etching technique, thereby forming silicide layers 19a and 19b. A wiring layer 23 connected to is formed. In addition, as a material of the wiring layer 23, a laminated structure such as a TiN / Al-Cu / Ti / TiN structure may be used in addition to Al and Cu.

Next, as shown in FIG. 2B, an insulating film 31 is formed on the interlayer insulating layer 21 on which the wiring layer 23 is formed by a method such as CVD. As a material of the insulating film 31, for example, SiO ₂ can be used. Here, it is preferable to use HDP-CVD as a method for forming the insulating film 31. Thereby, the deposition temperature of the insulating film 31 can be set to 450 ° C. or lower, and the insulating film 31 is formed on the wiring layer 23 while suppressing damage to the wiring layer 23 and the gate electrode 14 below the insulating film 31. Can be stacked.

And the recessed part 32 is formed in the insulating film 31 by patterning the insulating film 31 using a photolithographic technique and an etching technique. In addition, as a shape of the recessed part 32, cylindrical shape, conical shape, prismatic shape, pyramid shape etc. can be mentioned, for example. The concave portion 32 can function as a grain filter, and the size of the concave portion 32 can be set so that crystal growth using one crystal nucleus as a seed proceeds preferentially. For example, the size of the recess 32 can be set to a diameter of 50 nm to 150 nm and a depth of 750 nm or more.
If it is difficult to form the recess 32 having a desired size only by using the photolithography technique, a new insulating film is formed on the insulating film 31 in which the recess 32 is formed. The desired size may be realized by narrowing the width.

  Next, as shown in FIG. 2C, an amorphous semiconductor layer 33 is formed on the insulating film 31 so as to fill the recess 32 by a method such as CVD. Note that the amorphous semiconductor layer 33 may be a polycrystalline semiconductor in addition to an amorphous semiconductor. The film thickness of the amorphous semiconductor layer 33 is preferably set so that the recess 32 is completely embedded in the amorphous semiconductor layer 33. Here, as a method for forming the amorphous semiconductor layer 33, it is preferable to use LP-CVD. As a result, the deposition temperature of the amorphous semiconductor layer 33 can be set to 450 ° C. or lower, and the insulating film 31 is suppressed while preventing damage to the wiring layer 23 and the gate electrode 14 below the amorphous semiconductor layer 33. An amorphous semiconductor layer 33 can be stacked thereon.

Next, as shown in FIG. 2 (d), the amorphous semiconductor layer 33 is irradiated with a laser to melt and crystallize the amorphous semiconductor layer 33. 34 is formed. The term “substantially single crystal semiconductor grains” as used herein refers to grains that can include regular grain boundaries (corresponding grain boundaries) such as Σ3, Σ9, and Σ27 but do not include irregular grain boundaries. In general, irregular grain boundaries contain a large number of unpaired electrons, which is a major factor in the deterioration of characteristics and variations in the characteristics of the elements formed there, but the substantially single crystal semiconductor grains do not contain unpaired electrons. By forming an element in a substantially single crystal semiconductor grain, an element having excellent characteristics can be realized. As a condition for irradiating the amorphous semiconductor layer 33 with a laser, it is preferable to use a XeCl pulse excimer laser (wavelength 308 nm, pulse width 200 nsec) and an energy density of 0.4 to ² J / cm ² . Here, when the amorphous semiconductor layer 33 and the substantially single crystal semiconductor grain 34 are Si, the absorption coefficients of the amorphous semiconductor layer 33 and the substantially single crystal semiconductor grain 34 with respect to the wavelength of the XeCl pulse excimer laser are 0.139 nm ⁻ respectively. ^Since it is as large as ¹ and 0.149 nm ⁻¹ , the XeCl pulse excimer laser irradiated to the amorphous semiconductor layer 33 is almost absorbed by the surfaces of the amorphous semiconductor layer 33 and the substantially single crystal semiconductor grains 34. For this reason, even when the amorphous semiconductor layer 33 is melted, the temperature of the semiconductor substrate 11 can be suppressed to about 400 ° C. or less, and the wiring layer 23 and the gate electrode 14 exist under the substantially single crystal semiconductor grains 34. Even in this case, it is possible to prevent the wiring layer 23 and the gate electrode 14 from being damaged.

  Further, since the XeCl pulse excimer laser irradiated to the amorphous semiconductor layer 33 is almost absorbed by the surfaces of the amorphous semiconductor layer 33 and the substantially single crystal semiconductor grains 34, the amorphous semiconductor layer 33 is formed at the bottom of the recess 32. The amorphous semiconductor layer 33 on the insulating film 31 can be completely melted over the entire region while leaving an unmelted portion of the layer 33. When laser irradiation to the amorphous semiconductor layer 33 is stopped, solidification of the molten portion of the amorphous semiconductor layer 33 starts from the unmelted portion of the amorphous semiconductor layer 33 as a base point. Here, only one crystal grain reaches the upper part of the recess 32 by setting the cross-sectional dimension of the recess 32 so that the same size as that of one crystal grain is slightly smaller. When one crystal grain reaches the upper part of the recess 32, crystal growth proceeds around the recess 32 using the crystal grain as a nucleus, and the periphery of the recess 32 is accompanied by melt crystallization of the amorphous semiconductor layer 33. A substantially single crystal semiconductor grain 34 can be formed in the step. Note that, after the substantially single crystal semiconductor grains 34 are formed around the recesses 32, the substantially single crystal semiconductor grains 34 may be flattened by a method such as CMP (Chemical Mechanical Polishing). This is because when the surface roughness of the substantially single crystal semiconductor grain 34 increases, the electron mobility in the substantially single crystal semiconductor grain 34 decreases. Here, as an example of the conditions for performing CMP, for example, a soft polyurethane pad and a polishing liquid in which an abrasive such as silica particles is dispersed in an ammonia-based or amine-based alkaline solution are used in combination. Here, the hydrogen concentration of the polishing liquid is PH 11.0 or less, more preferably 9.0 or less.

Next, as shown in FIG. 3A, the amorphous semiconductor layer 33 and the substantially single crystal semiconductor grains 34 are patterned by using a photolithography technique and a dry etching technique, thereby forming the amorphous semiconductor layer 33. Then, unnecessary portions of the substantially single crystal semiconductor grains 34 are removed.
Next, as shown in FIG. 3B, a gate insulating film 36 is formed on the surface of the substantially single crystal semiconductor grain 34 by performing thermal oxidation, ALD or CVD treatment on the surface of the substantially single crystal semiconductor grain 34. . As the material of the gate insulating film 36, for example, other _{SiO 2, HfO 2, HfON,} HfAlO, HfAlON, HfSiO, HfSiON, ZrO 2, ZrON, ZrAlO, ZrAlON, ZrSiO, ZrSiON, Ta 2 O 5, Y Dielectric materials such as ₂ O ₃ , (Sr, Ba) TiO ₃ , LaAlO ₃ , SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ , and Pb (Zi, Ti) O ₃ may be used. Here, as a method of forming the gate insulating film 36, it is preferable to use a direct oxide film by high-density plasma. Thereby, the film formation temperature of the gate insulating film 36 can be set to 400 ° C. or lower, and the gate insulating film 36 is formed on the wiring layer 23 while suppressing damage to the wiring layer 23 and the gate electrode 14 below the gate insulating film 36. The film 36 can be stacked.

  Then, a polycrystalline silicon layer, a silicide layer, or a metal layer is formed on the substantially single crystal semiconductor grain 34 on which the gate insulating film 36 is formed by a method such as CVD or sputtering. Then, a gate electrode 37 is formed on the gate insulating film 36 by patterning the polycrystalline silicon layer, the silicide layer, or the metal layer using a photolithography technique and an etching technique. The material of the gate electrode 37 includes, for example, polycrystalline silicon, metal materials such as TaN, TiN, W, Pt, and Cu, metal laminated structures such as TaNx / bcc-Ta / TaNx, or alloys such as silicide. A material may be used. Here, as a method for forming the gate electrode 37, HDP-CVD is preferably used.

Next, using the gate electrode 37 as a mask, impurities such as As, P, B, and BF ₂ are ion-implanted into the substantially single crystal semiconductor grains 34 to thereby form source / drain layers respectively disposed on both sides of the gate electrode 37. 35a and 35b are formed in a substantially single crystal semiconductor grain 34. Then, after depositing an interlayer insulating layer 38 over the substantially entire surface of the single crystal semiconductor grain 34 by a method such as CVD, activation annealing of the source / drain layers 35a and 35b is performed. Here, the substantially single crystal semiconductor grain 34 is preferably an intrinsic semiconductor grain. As a result, the activation annealing temperature can be set to 450 ° C. or less, and the source / drain layers 35a and 35b are made to be the wiring layer 23 while suppressing damage to the wiring layer 23 and the gate electrode 14 below the insulating film 31. Can be laminated on top.

  Next, the interlayer insulating layer 38 is patterned by using a photolithography technique and an etching technique to form an opening 39 in the interlayer insulating layer 38 that exposes the source / drain layers 35a and 35b. Then, a conductive film embedded in the opening 39 is formed on the interlayer insulating layer 38 by a method such as sputtering, and the conductive film is patterned using a photolithography technique and an etching technique, whereby the source / drain layer 35a. , 35b is formed. Further, as shown in FIG. 3C, wiring layers 42 and 43 stacked on the semiconductor substrate 11 are formed via the interlayer insulating layer 41.

  As a result, it is possible to stack non-salicide elements on the salicide elements, and the salicide elements and non-salicide elements are mixedly mounted on the same semiconductor substrate 11 without arranging the salicide elements and non-salicide elements on the same plane. It becomes possible to do. For this reason, it is possible to suppress an increase in the chip area, and it is possible to perform a non-salicide process without being affected by the salicide process. Can be reduced.

  An example of the element formed on the substantially single crystal semiconductor grain 34 is an electrostatic protection circuit. Accordingly, the salicide element and the electrostatic protection circuit can be mixedly mounted on the same semiconductor substrate 11 without forming the electrostatic protection circuit on the same plane on the semiconductor substrate 11 on which the salicide element is formed. . For this reason, it is possible to increase the resistance of the electrostatic protection circuit while suppressing complication of the manufacturing process, and it is possible to stably protect the semiconductor device from breakdown due to static electricity while suppressing an increase in cost. .

In the above-described embodiment, the structure in which the transistors are stacked over two layers has been described as an example. However, by repeating the method of stacking the single crystal semiconductor layer over the insulating layer, the transistors are stacked over three or more layers. You may make it laminate | stack.
In the above-described embodiment, the method for forming a transistor in the substantially single crystal semiconductor grain 34 in which the amorphous semiconductor layer 33 is single-crystallized has been described as an example. However, the amorphous semiconductor layer 33 is single-crystallized. Alternatively, a transistor may be formed directly on the amorphous semiconductor layer 33.

  In the above-described embodiments, the case where one salicide element and one non-salicide element are formed has been described as an example. However, a plurality of salicide elements and non-salicide elements may be formed. At this time, a plurality of recesses 32 may be formed in the insulating film 31 to form a plurality of substantially single crystal semiconductor grains 34.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention.

Explanation of symbols

  11 Semiconductor substrate, 12 Element isolation insulating film, 13, 36 Gate insulating film, 14, 37 Gate electrode, 15a, 15b LDD layer, 16 Side wall, 17a, 17b, 35a, 35b Source / drain layer, 18 Metal layer, 19a 19b, 19c Silicide layer, 31 insulating film, 32 recess, 33 amorphous semiconductor layer, 34 substantially single crystal semiconductor grain, 21, 38, 41 interlayer insulating layer, 22, 39 opening, 23, 40, 42, 43 Wiring layer

Claims (8)

A salicide element formed on a semiconductor substrate;
An amorphous semiconductor layer stacked on the salicide element;
A semiconductor device comprising: a non-salicide element formed on the amorphous semiconductor layer. A salicide element formed on a semiconductor substrate;
A substantially single crystal semiconductor grain laminated on the salicide element;
A semiconductor device comprising: a non-salicide element formed on the substantially single crystal semiconductor grain.   The semiconductor device according to claim 2, wherein the substantially single crystal semiconductor grain is an intrinsic semiconductor grain. A first substantially single crystal semiconductor grain stacked on an insulator;
A salicide element formed on the first substantially single crystal semiconductor grain;
A second substantially single crystal semiconductor grain laminated on the salicide element;
A semiconductor device comprising: a non-salicide element formed on the second substantially single crystal semiconductor grain.   The semiconductor device according to claim 1, wherein the non-salicide element is an electrostatic protection circuit. Forming a salicide element on a semiconductor substrate;
Forming an insulating film on the salicide element;
Forming an amorphous semiconductor layer on the insulating film;
And a step of forming a non-salicide element on the amorphous semiconductor layer. Forming a salicide element on a semiconductor substrate;
Forming an insulating film on the salicide element;
Forming a grain filter in the insulating film;
Forming an amorphous semiconductor layer on the insulating film so as to embed the grain filter;
Forming a substantially single crystal semiconductor grain in which the amorphous semiconductor layer around the grain filter is made into a substantially single crystal grain by irradiating a region including the grain filter of the amorphous semiconductor layer with a laser; ,
And a step of forming a non-salicide element on the substantially single crystal semiconductor grain. Forming a non-salicide element on the single crystal semiconductor grain,
Forming a gate insulating film on the single crystal semiconductor grains by a direct oxidation method using high-density plasma;
Forming a gate electrode on the gate insulating film;
Implanting impurities into the single crystal semiconductor grains using the gate electrode as a mask;
The method for manufacturing a semiconductor device according to claim 7, further comprising a step of performing activation annealing of impurities implanted into the single crystal semiconductor grains at a temperature of 450 ° C. or lower.

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