JP2007157890A - Semiconductor integrated circuit and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where suppression of increase in a layout area of LSI by loading of a physical fuse and improvement of a security function are simultaneously realized. <P>SOLUTION: The semiconductor device is provided with a test pad 1, an input buffer circuit 2, a CMOS transfer circuit 3 and an input control circuit 4 controlling the CMOS transfer circuit 3. An active or a non-active state of the CMOS transfer circuit 3 is collectively controlled in accordance with a state of connection or disconnection of the physical fuse 21 loaded on the input control circuit 4. Since the test pad 1 required for inspection in an output signal VCONT10 of the input control circuit 4 can be controlled, increase of the layout area is suppressed, and security can simultaneously be secured by fuse disconnection at the time of shipping. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a semiconductor device in a semiconductor device equipped with a security function for the purpose of preventing and suppressing tampering from a third party.

  In recent years, as represented by an IC card, an individual has possessed a card in which important information such as personal information and money information is written. In order to protect such important information, strengthen the security function against forgery, falsification, etc. from third parties on the LSI mounted on the IC card, especially ROM data and nonvolatile memory data embedded in the LSI. Technology for the purpose is installed.

  A semiconductor device equipped with a conventional tamper resistant (security) technology will be described below. FIG. 8 is a circuit configuration diagram of a peripheral portion of a test pad of a conventional semiconductor device.

  As shown in FIG. 8, in the conventional semiconductor device, for the purpose of improving the inspection efficiency at the time of non-volatile memory inspection, there is a case where the inspection is performed using a test pad dedicated to the inspection separately from the pad actually used. is there. The conventional semiconductor device includes a test pad unit 1 composed of a plurality of test pads TPAD1 to TPADn and an input buffer circuit unit 102 composed of input buffer circuits BUFB1 to BUFBn corresponding to the plurality of test pads TPAD1 to TPADn. And a fuse portion 103 composed of fuses FUSE1 to FUSEn for connecting the test pad and the input buffer circuit. After completion of the inspection before shipment of the semiconductor device, immediately before shipment, the fuses FUSE1 to FUSEn are cut and cut by a device such as a laser trimmer. As a result, access other than using normal means can be prohibited, so in the subsequent customer process and user use, important information written in the non-volatile memory from tampering and counterfeiting by third parties. Safeguard information.

By adopting the configuration and method as described above, access to the non-volatile memory in which important information is written, data modification, and access to the ROM that controls the program cannot be accessed except for normal means. Measures are taken to prevent tampering with important programs and monitoring important information. (For example, see Patent Document 1)
JP-A-10-197600 (FIG. 1)

  However, in the case of the circuit configuration as described above, as the amount of data in the nonvolatile memory or the like which is important increases, there are a large number of terminals dedicated for inspection. In addition, when a large number of fuses are arranged in the vicinity of all the test pads, the LSI chip area is distributed due to the large number of fuse elements distributed and layout restrictions related to the arranged fuse elements. The problem that becomes large occurs.

  Accordingly, an object of the present invention is to provide a semiconductor integrated circuit and a semiconductor device that solve two conflicting problems of ensuring security while suppressing an increase in chip area.

  In order to solve the above problems, a semiconductor integrated circuit according to claim 1 of the present invention includes a test pad section provided for inspection, and an input buffer circuit section for converting a signal input from the test pad section to a predetermined level. In addition, the test pad unit and the input buffer circuit unit are electrically connected, and the activation or deactivation state of the switch circuit can be controlled according to the connection state or disconnection state of the transfer circuit unit having the switch circuit and the physical fuse. And a control circuit.

  According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the switch circuit is a CMOS switch circuit.

  According to a third aspect of the present invention, there is provided the semiconductor integrated circuit according to the second aspect, wherein the control circuit has at least one physical fuse connected in advance and at least one physical fuse cut in advance. The active or inactive state of the CMOS switch circuit can be controlled according to the connection or disconnection state of the mounted physical fuse.

  According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, the pre-cut fuse is marked with the same cut mark as the pre-connected fuse after the inspection is completed.

  According to a fifth aspect of the present invention, there is provided the semiconductor integrated circuit according to the second aspect, wherein the control circuit includes an input control circuit that outputs an “H” or “L” level in accordance with a connected or disconnected state of the physical fuse. , A non-volatile memory for storing data, a latch circuit for latching data in the non-volatile memory, an output signal of the input control circuit and the latch data held by the latch circuit, and output of the comparison result And a comparison circuit capable of controlling the active or inactive state of the CMOS switch circuit in accordance with the signal state.

  A semiconductor device according to a sixth aspect includes the semiconductor integrated circuit according to the first, second, third, fourth or fifth aspect.

  According to the semiconductor integrated circuit of the first aspect of the present invention, since the control circuit that can control the active or inactive state of the switch circuit according to the connection or disconnection state of the physical fuse is provided, In addition, by cutting the mounted physical fuse and deactivating the test pad, only access using normal means can be permitted, and input from other test pad portions can be prohibited. Therefore, compared to the increase in the number of fuses in proportion to the increase in test pads as in the conventional circuit, the number of required fuses can be minimized, the increase in layout area can be suppressed, and security can be achieved by cutting physical fuses at the time of shipment. Can be secured.

  In the present invention, the switch circuit is preferably a CMOS switch circuit. In this case, the input buffer circuit unit can directly apply the signal level input from the test pad unit to the input buffer, and the input state of the input buffer circuit can be confirmed. That is, there is an advantage that it is possible to directly confirm whether or not the pad is electrically separated by using the CMOS switch circuit and the resistance element.

  According to another aspect of the semiconductor integrated circuit of the present invention, the control circuit has at least one physical fuse connected in advance and at least one physical fuse cut in advance, and a plurality of mounted physical fuses. Since the active or inactive state of the CMOS switch circuit can be controlled in accordance with the connection or disconnection state, the number of necessary fuses can be minimized as in the case of claim 1, the increase in layout area can be suppressed, and Security can be secured. Also, after the fuse is cut, the security function is further improved because the test pad cannot be used again unless it is restored as prescribed.

  In claim 4, since the pre-cut fuse is marked with the same cut mark as the pre-connected fuse after the inspection is completed, the difference between the pre-cut fuse and the pre-connected fuse at the time of product shipment It becomes difficult to understand, and the security function is further improved.

  According to the semiconductor integrated circuit of the fifth aspect of the present invention, the control circuit stores the data and the input control circuit that outputs the “H” or “L” level according to the connection or disconnection state of the physical fuse. Nonvolatile memory, latch circuit for latching data in nonvolatile memory, output signal of input control circuit and latch data held in latch circuit are compared, and according to the state of output signal of comparison result And a comparison circuit capable of controlling the active or inactive state of the CMOS switch circuit, so that the active or inactive state of the CMOS transfer circuit unit is controlled according to the state of the output signal of the comparison result, The setting of the comparison target data stored in the nonvolatile memory can be changed for each LSI as well as the mounted fuse is cut. For this reason, the number of necessary fuses can be minimized, the layout area can be prevented from increasing, and security can be ensured as in the first aspect. Also, after the fuse is blown, it must be restored as specified, and it also supports the method of physically decoding the internal circuit by comparing with data that cannot be physically decoded. The security function is further improved by being able to do this and setting each LSI individually.

  According to the semiconductor device of the sixth aspect of the present invention, since the semiconductor integrated circuit according to the first, second, third, fourth or fifth aspect is mounted, the increase in the number of fuses in proportion to the increase in the number of test pads as in the conventional circuit. In comparison with the above, the number of necessary fuses can be minimized, the increase in layout area can be suppressed, and security can be ensured.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIG.

  FIG. 1 shows a circuit diagram relating to a first embodiment of the present invention.

  As shown in FIG. 1, in the first embodiment, a test pad unit 1 composed of test pads TPAD1 to TPADn provided for inspection and a signal input from the test pad unit 1 are converted to a predetermined level. Input buffer circuit unit 2 composed of BUFA1 to BUFAn, test pad unit 1 and input buffer circuit unit 2 are electrically connected, CMOS transfer circuit unit 3 composed of CMOS switches SW1 to SWn, and CMOS transfer circuit The input control circuit 4 collectively controls the active or inactive states of SW1 to SWn constituting the unit 3.

  The test pad unit 1 is composed of test pads TPAD1 to TPADn.

  The input buffer circuit unit 2 includes input buffer circuits BUFA1 to BUFAn, and converts a signal input from the test pad 1 to a CMOS level. An example of the input buffer circuit BUFA1 will be described based on the circuit configuration described in the input buffer circuit BUFA1 in FIG. The input buffer circuit BUFA1 includes a high resistance element 41 and an inverter 42. One of the high resistance elements 41 is connected to the input node and the inverter 42, and the other is connected to the ground terminal VSS.

  In the above description, the example in which the resistance element 41 is inserted between the input node and the ground terminal VSS has been described. However, the same function can be achieved even when the resistance element 41 is inserted between the input node and the power supply terminal VDD. Have.

  The CMOS transfer circuit unit 3 includes CMOS switch circuits SW1 to SWn. An example of the CMOS switch circuit SW1 will be described based on the circuit configuration described in SW1 of FIG. The CMOS switch SW1 includes an N channel transistor 11, a P channel transistor 12, and an inverter 13. The N-channel transistor 11 has a gate terminal connected to VCONT10 that is an output signal of the input control circuit 4, a source terminal connected to the test terminal TPAD1, and a drain terminal connected to the input terminal of the input buffer circuit BUFA1. The P-channel transistor 12 has a gate terminal connected to the output signal of the inverter 13, a source terminal connected to the test terminal TPAD1, and a drain terminal connected to the input terminal of the input buffer circuit BUFA1. The inverter 13 has an input terminal connected to the VCONT 10 and an output terminal connected to the gate terminal of the P-channel transistor 12.

  The input control circuit 4 makes it possible to control the active or inactive state of the CMOS switch circuits SW1 to SWn according to the connection or disconnection state of the physical fuse 21. In this case, the P-channel transistor 22 has a source terminal connected to the power supply terminal VDD, a gate terminal connected to the VBIAS terminal, and a drain terminal connected to the input of the inverter 31 and one of the fuses 21. The fuse 21 has one terminal connected to the VSS terminal and the other terminal connected to the input of the inverter 31 and the drain terminal of the P-channel transistor 22. The inverter 31 has an input terminal connected to the drain terminal of the P-channel transistor 22 and one terminal of the fuse 21, and an output terminal connected to the input terminal of the inverter 32. The inverter 32 has an input terminal connected to the output terminal of the inverter 31, and an output terminal connected to the input terminal of the inverter 33. The inverter 33 has an input terminal connected to the output terminal of the inverter 32, and an output terminal used as the control signal VCONT 10 of the CMOS transfer circuit unit 3.

  The potential of VBIAS is controlled to be controlled at a potential slightly lower than VDD−Vtp when the threshold voltage Vt of the P-channel transistor 22 is Vtp. The potential of VBIAS is controlled from VDD through the transistor 22 to the inverter circuit 31. Current flows into the input terminal. The equivalent resistance in the P-channel transistor 22 is set larger than the resistance value of the physical fuse 21.

  In the initial state where the physical fuse 21 remains connected, the gate potential of the inverter circuit 31 becomes “L” potential due to the relationship between the equivalent resistance of the P-channel transistor 22 and the resistance value of the physical fuse 21, and the CMOS switch control signal VCONT 10 is in the “H” potential state, and the CMOS switch circuit is activated. In this case, the test pad unit 1 and the input buffer circuit unit 2 are electrically connected, and the test pad unit 1 can be used for inspection.

  Further, by cutting the physical fuse 21 at the time of shipment, the input terminal of the inverter circuit 31 is connected only to the current supply source from VDD. In this case, the gate potential of the inverter circuit 31 becomes “H” potential, the CMOS switch control signal VCONT10 becomes “L” potential state, and the CMOS switch circuit becomes inactive. The test pad unit 1 and the input buffer circuit unit 2 are electrically disconnected, and control from the test pad becomes invalid.

  Further, according to this circuit configuration, in the initial state where the physical fuse 21 is connected, a voltage of a certain level or higher is applied to the test pad TPAD 1, thereby allowing the P-channel transistor 12, the N-channel transistor 11, and the high-resistance element 41 to pass Current flows. If the physical fuse is cut at the time of shipment, even if a voltage exceeding a certain level is applied to the test pad TPAD1, no current is generated because it is cut off electrically. You can easily check if it is done.

In the present embodiment, for the sake of simplicity of explanation, the number of inspection terminals has been narrowed down. However, as the number of inspection terminals increases, the LSI chip area suppression effect increases.
(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS. The same components as those in FIG.

  FIG. 2 shows a circuit diagram relating to the second embodiment of the present invention.

  As shown in FIG. 2, in the second embodiment, the test pad unit 1 composed of TPAD1 to TPADn, the input buffer circuit unit 2 composed of BUFA1 to BUFAn, the test pad unit 1 and the input buffer circuit unit 2 includes a CMOS transfer circuit unit 3 composed of SW1 to SWn that electrically connects 2 and a control circuit 5 that collectively controls the active or inactive states of SW1 to SWn that constitute the CMOS transfer circuit unit 3. Has been. Since the configuration other than the control circuit 5 is the same as that of the first embodiment, a detailed description is omitted.

  An example of the control circuit 5 is shown in FIG.

  The control circuit 5 includes an input control circuit 4, an input control circuit 6, and an AND circuit 63 that outputs a control signal VCONT20 using the output signal GCONT31 of the input control circuit 4 and the output signal GCONT32 of the input control circuit 6 as input signals. Is done. Since the input control circuit 4 has been described in the first embodiment, a detailed description thereof will be omitted.

  The input control circuit 6 will be described with reference to FIG. The input control circuit 6 includes a P-channel transistor 50, an electrical fuse 51 cut in advance, and inverters 61 and 62. The P-channel transistor 50 has a source terminal connected to the power supply terminal VDD, a gate terminal connected to the VBIAS terminal, and a drain terminal connected to the input of the inverter 61 and one of the fuses 51.

  The fuse 51 has one terminal connected to the VSS terminal and the other terminal connected to the input of the inverter 61 and the drain terminal of the P-channel transistor 50. The inverter 61 has an input terminal connected to the drain terminal of the P-channel transistor 50 and one terminal of the fuse 51, and an output terminal connected to the input terminal of the inverter 62. The inverter 62 has an input terminal connected to the output terminal of the inverter 61, and an output terminal serving as a control signal GCONT32.

  Similarly to the description in the first embodiment, the potential of VBIAS is controlled to be controlled at a potential slightly lower than VDD−Vtp when the threshold voltage Vt of the P-channel transistor 22 is Vtp. A current flows from VDD to the input terminal of the inverter circuit 31 via 22.

  In the input control circuit 6, since the physical fuse 51 is cut in advance, the gate potential of the inverter circuit 61 becomes "H" potential, and the control signal GCONT32 becomes "H" potential state.

  In an initial state where the physical fuse 21 remains connected, the control signal GCONT 31 is at “H” potential, and the control signal GCONT 32 is also at “H” potential. Therefore, VCONT 20 is also in the “H” potential state, and the CMOS switch circuit is activated. In this case, the test pad unit 1 and the input buffer circuit unit 2 are electrically connected, and the test pad unit 1 can be used for inspection.

  Further, by cutting the physical fuse 21 at the time of shipment, the control signal GCONT 31 becomes “L” potential, the VCONT 20 also becomes “L” potential state, and the test pad unit 1 and the input buffer circuit unit 2 are electrically disconnected, Control from the test pad is disabled.

  At the time of shipment, not only the fuse 21 but also the fuse 51 is marked with a laser trimmer so that a difference from the previously connected fuse 21 is not known.

  As described above, the fuse 51 is also marked with a cut as in the case of the fuse 21. Therefore, it is effective for ensuring security that the cut width of the fuse cut in advance is narrower than the cut mark of the laser device. is there.

  When a third party performs tampering, the physical fuse must be correctly restored. For example, when the fuse 51 is reconnected, the control signal GCONT 32 is in the “L” potential state, so the CMOS transfer circuit unit 3 is in the “L” potential state. Since the test pad unit 1 is in an inactive state, there is an effect of preventing or suppressing falsification from a third party.

Further, in this embodiment, for the sake of simplification of description, one input control circuit 4 using a pre-connected fuse and one input control circuit 6 using a pre-cut fuse are combined and each input is combined. As described above, the AND logic of the output control signal of the control circuit is taken to control the CMOS switch circuit. However, as shown in FIG. 4, the number of mounted input control circuits 4 and input control circuits 6 is increased. Needless to say, when the fuse elements are actually laid out, the security function is improved by random arrangement.
(Third embodiment)
A third embodiment of the present invention will be described with reference to FIGS. The same components as those in FIG.

  FIG. 5 shows an example of a control circuit for controlling the CMOS transfer circuit unit 3 according to the third embodiment of the present invention.

  As shown in FIG. 5, the control circuit includes an input control circuit 4, a nonvolatile memory 81 typified by EEPROM and FeRAM, a latch circuit 82 that latches data in the nonvolatile memory 81, and a comparison circuit 83. Composed.

  Data in the nonvolatile memory 81 is latched in the latch circuit 82. The latched data output signal GCONT52 and the output signal GCONT51 of the input control circuit 4 are input to the comparison circuit 83, and the states of the two signals are compared and output to the VCONT20 which is the control signal of the CMOS transfer circuit unit 3.

  In the initial state with the physical fuse 21 connected, the nonvolatile memory is controlled so that the control signal GCONT 51 is at “H” potential and the data output of the latch circuit is also at “H” potential. In this state, the output signal VCONT20 of the comparison circuit 83 is also in the “H” potential state, and the CMOS switch circuit is activated. In this case, the test pad unit 1 and the input buffer circuit unit 2 are electrically connected, and the test pad unit 1 can be used for inspection.

  Further, by cutting the physical fuse 21 at the time of shipment, the control signal GCONT 51 becomes “L” potential, the VCONT 20 also becomes “L” potential state, and the test pad unit 1 and the input buffer circuit unit 2 are electrically disconnected, The control from the test pad unit 1 becomes invalid.

  Also, the test pad can be deactivated by changing the data in the nonvolatile memory 81 at the time of shipment.

  Further, as shown in FIG. 6, it is needless to say that the same effect can be obtained by using the input control circuit 6 instead of the input control circuit 4 and changing the data in the nonvolatile memory at the time of shipment. . GCONT 62 is an output signal of the latched data, and GCONT 61 is an output signal of the input control circuit 6.

  Further, in the above embodiment, for the sake of simplification of explanation, the explanation is given in the embodiment in which one input control circuit 4 is used. However, as shown in FIG. 7, the input control circuit 4 and the input control circuit are used. Needless to say, a circuit configuration using a plurality of 6 improves the security function. GCONTs 71 and 72 are output signals of the input control circuit 4, and GCONTs 73 and 74 are output signals of the input control circuit 6.

  In addition, the data state of the nonvolatile memory cannot be deciphered by physical analysis, and the user can arbitrarily change the security code by comparing with the data of the nonvolatile memory. Since the usable state can be set for each LSI, the security function is further improved.

  The number of inverters may be any number as long as the above control can be performed. The switch circuit can also be realized with a NAND or NOR circuit configuration. However, there is an advantage that it is possible to directly confirm whether or not the pad is electrically separated by using the CMOS switch circuit and the resistance element.

  The semiconductor integrated circuit according to the present invention has a function of suppressing an increase in the layout area of an LSI equipped with a tamper resistant fuse and further improving the tamper resistance as a countermeasure against tampering by a third party, and a security function. Is useful as a semiconductor device for an IC card and the like.

1 is a circuit diagram showing a part of a semiconductor device according to a first embodiment of the present invention. It is a circuit diagram which shows a part of semiconductor device regarding the 2nd Embodiment of this invention. It is a circuit diagram which shows the 1st example of the input control circuit regarding the 2nd Embodiment of this invention. It is a circuit diagram which shows the 2nd example of the input control circuit regarding the 2nd Embodiment of this invention. It is a circuit diagram which shows the 1st example of the input control circuit regarding the 3rd Embodiment of this invention. It is a circuit diagram which shows the 2nd example of the input control circuit regarding the 3rd Embodiment of this invention. It is a circuit diagram which shows the 3rd example of the input control circuit regarding the 3rd Embodiment of this invention. It is a circuit diagram regarding the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Test pad part 2,102 Input buffer circuit part 3 CMOS transfer circuit part 4,5,6 Input control circuit 11 N channel transistor 12, 22, 50 P channel transistor 13, 31, 32, 33, 42 Inverter 21 Physical fuse 41 Resistance element 51 Physical fuses 63 and 71 previously cut AND circuit 81 Non-volatile memory 82 Latch circuits 83 and 84 Comparison circuit 103 Fuse part

Claims (6)

A test pad provided for inspection;
An input buffer circuit unit for converting a signal input from the test pad unit to a predetermined level;
A transfer circuit unit electrically connecting the test pad unit and the input buffer circuit unit and having a switch circuit;
A semiconductor integrated circuit comprising: a control circuit capable of controlling an active state or an inactive state of the switch circuit according to a connection or disconnection state of a physical fuse.   The semiconductor integrated circuit according to claim 1, wherein the switch circuit is a CMOS switch circuit.   The control circuit has at least one physical fuse connected in advance and at least one physical fuse cut in advance, and the CMOS switch circuit according to the connection or disconnection state of the plurality of mounted physical fuses The semiconductor integrated circuit according to claim 2, wherein the active or inactive state of said semiconductor device can be controlled.   4. The semiconductor integrated circuit according to claim 3, wherein the pre-cut fuse has a cut mark similar to that of the pre-connected fuse after completion of the inspection.   The control circuit latches the data stored in the nonvolatile memory, the input control circuit that outputs “H” or “L” level, the nonvolatile memory that stores the data, depending on the connection or disconnection state of the physical fuse And the latch signal held by the latch circuit, and the CMOS switch circuit is activated or deactivated according to the state of the output signal of the comparison result. A semiconductor integrated circuit according to claim 2, further comprising a comparison circuit that can control the circuit.   6. A semiconductor device on which the semiconductor integrated circuit according to claim 1, 2, 3, 4, or 5 is mounted.

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