JP2007156641A - Power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost power supply circuit enabling adoption of a package having large thermal resistance for an IC chip having a voltage stabilization circuit incorporated therein. <P>SOLUTION: A noise elimination circuit 2 connects a power supply unit (A) such as battery, includes a transistor Q between an input terminal from the power supply unit (A) and an output terminal to a voltage stabilization circuit 1, and outputs to the voltage stabilization circuit 1 a supply voltage in which a high voltage noise being superposed to an input voltage supplied from the power supply unit (A) is eliminated. By detecting the voltage of the output terminal to the voltage stabilization circuit 1, a voltage regulator circuit 3 controls the base of the transistor Q to let the output supply voltage of the noise elimination circuit 2 to be a predetermined voltage. The voltage stabilization circuit 1 outputs to a load side a supply voltage stabilized based on a predetermined reference voltage and noise of which is eliminated in the noise elimination circuit 2. The voltage stabilization circuit 1 is configured to be included in an IC chip ICa. Meanwhile, the transistor Q provided in the noise elimination circuit 2 is configured not to be included in at least the above IC chip ICa. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply circuit, and more particularly to a circuit configuration technique in a series regulator.

  As a recent market trend in electronic devices, there is a demand for a reduction in the number of components used as the cost of products is reduced and the mounting area of components is reduced. Therefore, also in a series regulator generally used in an in-vehicle control device or the like, a control circuit and an output transistor are mounted in the same package. However, when the output current of the power supply increases, the amount of heat generated by the power loss of the output transistor also increases and may exceed the performance limit temperature of the circuit element. Therefore, the temperature rise must be suppressed. As a countermeasure, it is necessary to use a package having a smaller thermal resistance, although the cost increases.

  As shown in FIG. 2, the conventional typical power supply circuit mainly includes a noise removal circuit 2 and a voltage stabilization circuit 1 built in a semiconductor integrated circuit device (IC chip) IC. The power supply circuit removes high-voltage noise superimposed on the input voltage supplied from a power supply device (power feeder) A such as a battery or a generator by the noise removal circuit 2, stabilizes it by the voltage stabilization circuit 1, and outputs power. Power is supplied from OUT to a load side (not shown). Each circuit configuration will be described below.

  The voltage stabilization circuit 1 includes a MOS transistor M1 that outputs a stabilized voltage, resistors R1 and R2 that divide the power supply output OUT, and a differential amplifier OP1 that controls the operation of the MOS transistor M1. The MOS transistor M1 has a source connected to the emitter of the bipolar transistor Q, a drain connected to one end of the resistor R1 as a power supply output OUT, and a gate connected to the output terminal of the differential amplifier OP1. The other end of the resistor R1 is connected to the non-inverting input terminal of the differential amplifier OP1 together with the other end of the resistor R2 whose one end is grounded. The reference voltage output from the reference voltage source VR is applied to the inverting input terminal of the differential amplifier OP1. Note that a high-capacitance capacitor C1 for stabilizing the output voltage is normally inserted between the power output OUT and the ground.

  The noise removal circuit 2 includes a bipolar transistor Q, a resistor R3 inserted between the collector and base of the bipolar transistor Q, a Zener diode ZD inserted between the base and ground, and a capacitor C2 inserted between the emitter and ground. The collector of the bipolar transistor Q is connected to the positive terminal of the power supply device A through a reverse connection protection diode D. The anode of the diode D is connected to the power supply device A, and the cathode is connected to the collector of the bipolar transistor Q. The negative terminal of the power supply device A is grounded.

  Next, the operation of the power supply circuit configured as described above will be described. The base voltage of the bipolar transistor Q is controlled by a resistor R3 and a Zener diode ZD. When high voltage noise is applied to the noise removal circuit 2, the voltage higher than the breakdown voltage of the Zener diode ZD is cut, and as a result, a voltage lower than the breakdown voltage of the Zener diode ZD is output from the emitter of the bipolar transistor Q.

  In the voltage stabilization circuit 1, the gate voltage of the MOS transistor M1 is controlled by the differential amplifier OP1 based on the resistance values of the resistors R1 and R2 and the voltage value of the reference voltage source VR, and the power output OUT that is output from the drain Is controlled to be constant regardless of the input (source side) voltage.

  As a technique related to the voltage stabilization circuit as described above, Patent Document 1 includes a reference voltage circuit, an operational amplifier, a power transistor, and a resistor, and changes from a predetermined input voltage to a desired output voltage. A series regulator circuit for converting a voltage value is disclosed. In this series regulator circuit, clamping means is connected between the output terminal and input terminal of the operational amplifier, and even if a power supply voltage exceeding the withstand voltage of the power MOS transistor is applied, the withstand voltage between the source and drain of the power MOS transistor is reduced. The breakdown voltage between the source and the gate can be ensured.

JP 2002-343874 A (FIG. 1)

  Incidentally, the noise removal circuit 2 in FIG. 2 has only a function of blocking high voltage noise superimposed on the input voltage, and has almost no voltage drop with respect to the normal input voltage. A large power loss due to a voltage drop between the input voltage and the power supply output OUT of the voltage stabilizing circuit 1 is not borne. For example, when the input voltage to the noise removal circuit 2 is 12V and the output voltage of the voltage stabilization circuit 1 is 5V, the output voltage of the noise removal circuit 2 via the bipolar transistor Q has a large voltage drop with respect to the input voltage. Since there is no voltage, the voltage is almost 12V, and the voltage drop of the MOS transistor M1 is 7V. Therefore, the voltage drop in the MOS transistor M1 of the voltage stabilizing circuit 1 is large, and the power loss of the MOS transistor M1 increases. For this reason, since the amount of heat generated in the IC chip incorporating the MOS transistor M1 increases, a package having a low thermal resistance must be used for the IC chip, which may increase the cost of the power supply circuit.

  Note that by setting the breakdown voltage of the Zener diode ZD to a voltage slightly higher than the output voltage of the voltage stabilizing circuit 1, it is possible to increase the voltage drop of the power source and reduce the loss of the MOS transistor M1, but the resistance R3 Therefore, it is necessary to constantly pass a relatively large current of about several mA through the Zener diode ZD. Therefore, the power supply circuit of FIG. 2 can be applied to a system that requires a sleep (low current consumption) mode in which most functions are stopped and the total current consumption of all circuits is about several tens of μA to several hundreds of μA or less. There wasn't.

  A power supply circuit according to one aspect of the present invention includes a noise removal circuit that removes noise superimposed on an input voltage and generates an output voltage having a voltage value in response to a control signal, and stabilizes the output voltage of the noise removal circuit. A voltage stabilizing circuit that outputs to the load side, and a voltage adjusting circuit that outputs a control signal so as to set the value of the output voltage of the noise removal circuit with respect to the value of the input voltage.

  According to the present invention, the voltage drop in the voltage stabilization circuit is reduced, and the heat generation amount is suppressed. Therefore, it is possible to adopt an inexpensive package having a large thermal resistance for the IC chip in which the voltage stabilizing circuit is built.

  The power supply circuit according to the embodiment of the present invention includes a noise removal circuit (2 in FIG. 1), a voltage adjustment circuit (3 in FIG. 1), and a voltage stabilization circuit (1 in FIG. 1). The noise removal circuit is connected to a power supply device (A in FIG. 1) such as a battery, and includes a transistor (Q in FIG. 1) between an input terminal from the power supply device and an output terminal to the voltage stabilization circuit. The power supply voltage from which high voltage noise superimposed on the input voltage supplied from the power supply device is removed is output to the voltage stabilization circuit. The voltage adjustment circuit detects the voltage at the output terminal to the voltage stabilization circuit so that the output power supply voltage of the noise removal circuit becomes a predetermined voltage, and controls the control terminal of the transistor (Q in FIG. 1). The voltage stabilization circuit stabilizes the power supply voltage from which noise has been removed by the noise removal circuit based on a predetermined reference voltage and outputs the stabilized power supply voltage to the load side. That is, the voltage stabilization circuit includes a transistor (M1 in FIG. 1) between the input terminal and the output terminal to the load side, and the transistor (M1 in FIG. 1) so that the output voltage to the load side is constant. To control the gate.

  The power supply circuit includes a mode input terminal (CT in FIG. 1), and the voltage adjustment circuit operates when the mode input terminal is set to the normal mode, and the mode input terminal is set to the sleep (low current consumption) mode. When set, it is configured to stop the operation.

  Further, the voltage stabilization circuit is included in the IC chip (ICa in FIG. 1), and the transistor (Q in FIG. 1) provided in the noise removal circuit is configured to be at least not included in the IC chip.

  In the power supply circuit configured as described above, a relatively large load current flows during normal operation. Therefore, the transistor (M1 in FIG. 1) in the voltage stabilization circuit has a voltage drop from the input voltage to the output voltage. Due to this, a large power loss occurs. By placing most of this power loss on the transistor (Q in FIG. 1) of the external noise elimination circuit, the power due to the voltage drop of the power output transistor (M1 in FIG. 1) built in the IC chip. Loss burden can be reduced, and heat generated in the package can be greatly reduced. Therefore, an inexpensive package having a large thermal resistance can be adopted for the IC chip. Note that the high-voltage noise countermeasure transistor (Q in FIG. 1) is provided with a heat dissipation measure, has a small thermal resistance of the package, and is relatively inexpensive.

  On the other hand, in the sleep mode in which the control device equipped with the power supply circuit stops normal operation and maintains the minimum necessary internal state, the voltage regulator circuit is used for the purpose of reducing current consumption and extending the power supply life of the battery, etc. Stop operation. In this case, the control method is switched to the same control method as in the conventional method, and the current consumption of the circuit is minimized. Hereinafter, it will be described in detail with reference to the drawings according to the embodiment.

  FIG. 1 is a circuit diagram of a power supply circuit according to an embodiment of the present invention. In FIG. 1, the power supply circuit includes a voltage stabilization circuit 1, a noise removal circuit 2, and a voltage adjustment circuit 3. 1, the same reference numerals as those in FIG. 2 represent the same items, and the description thereof is omitted.

  The voltage adjustment circuit 3 includes MOS transistors M2, M3, and M4, resistors R4, R5, and R6, a differential amplifier OP2, and an inverter INV. The inverter INV receives the sleep mode input CT and supplies an output to the gate of the MOS transistor M2. The drain of the MOS transistor M2 whose source is grounded is connected to the gate of the MOS transistor M3, one end of the resistor R4, and the control end of the differential amplifier OP2. The source of the MOS transistor M3 is connected to the other end of the resistor R4 and the emitter of the bipolar transistor Q of the noise removal circuit 2. The drain of the MOS transistor M3 is connected via a resistor R5 to the non-inverting input terminal of the differential amplifier OP2 and the other end of the resistor R6 whose one end is grounded. The reference voltage output from the reference voltage source VR is applied to the inverting input terminal of the differential amplifier OP2, and the output terminal of the differential amplifier OP2 is connected to the gate of the MOS transistor M4 whose source is grounded. The drain of the MOS transistor M4 is connected to the base of the bipolar transistor Q.

  The voltage stabilizing circuit 1, the voltage adjusting circuit 3, and the reference voltage source VR are built in a semiconductor integrated circuit device (IC chip) ICa.

  The operation of the power supply circuit configured as described above will be described below separately for (1) normal operation and (2) sleep (low current consumption) mode.

  (1) During normal operation, the sleep mode input CT is at a low level. When the sleep mode input CT is at a low level, the output of the inverter INV is at a high level and the MOS transistor M2 is turned on. As a result, the MOS transistor M3 is turned on, a current flows through the resistors R5 and R6, and the differential amplifier OP2 is activated. The base voltage of the bipolar transistor Q is controlled by the differential amplifier OP2, the MOS transistor M4, and the resistor R3 from the resistance setting values of the resistors R5 and R6 and the voltage value of the reference voltage source VR, and the emitter side voltage is changed to the collector side voltage. Regulated regardless of voltage. Note that the resistance value of the resistors R5 and R6 is set so that the voltage setting value on the emitter side of the bipolar transistor Q is lower than the breakdown voltage of the Zener diode ZD and larger than the voltage of the power supply output OUT of the voltage stabilizing circuit 1. Shall be set.

  In the voltage stabilization circuit 1, the gate voltage of the MOS transistor M1 is controlled by the differential amplifier OP1 from the resistance setting values of the resistors R1 and R2 and the voltage value of the reference voltage source VR. Therefore, the drain side output voltage (voltage of the power supply output OUT) of the MOS transistor M1 is held constant regardless of the input (source side) voltage. Further, by operating the voltage adjustment circuit 3 as described above, the source side voltage of the MOS transistor M1 is kept constant.

  As described above, the power supply circuit operates, the loss burden due to the voltage drop of the bipolar transistor Q increases, and conversely the loss burden of the MOS transistor M1 becomes relatively small. For example, when the output voltage of the noise removal circuit 2 whose input voltage from the power supply device A is 12V is 7V and the output voltage of the voltage stabilization circuit 1 is 5V, the voltage drop due to the bipolar transistor Q is expressed as “input voltage -7V, that is, 5V, and the voltage drop of the MOS transistor M1 is 2V.

  (2) In the sleep mode, the sleep mode input CT is at a high level. When the sleep mode input CT is at a high level, the output of the inverter INV is at a low level, and the MOS transistor M2 is turned off. As a result, the MOS transistor M3 is turned off, the current flowing through the resistors R5 and R6 is cut off, and the differential amplifier OP2 is in an operation stop state. Therefore, the output of the differential amplifier OP2 becomes low level, and the MOS transistor M4 is turned off. Therefore, the base voltage of the bipolar transistor Q is controlled by the resistor R3 and the Zener diode ZD as in the conventional case. The breakdown voltage of the Zener diode ZD is normally set to be equal to or lower than the withstand voltage of the semiconductor integrated circuit device ICa and higher than the maximum voltage of the power supply device A. When high voltage noise is applied by this setting, the breakdown voltage of the Zener diode ZD or higher is cut, and the voltage of “the breakdown voltage of the Zener diode ZD” −VBE is output from the emitter of the bipolar transistor Q. VBE is a voltage between the base and emitter of the bipolar transistor Q.

  Even in the sleep mode, in the voltage stabilization circuit 1, the gate voltage of the MOS transistor M1 is controlled by the differential amplifier OP1 from the setting of the resistors R1 and R2 and the voltage value of the reference voltage source VR, and the drain side output voltage is input. (Source side) Holds constant regardless of voltage.

  As described above, in the sleep mode, the operation of the voltage adjustment circuit 3 is stopped, and the current consumption of the semiconductor integrated circuit device ICa is reduced. In this case, the MOS transistor M1 bears a power loss corresponding to most of the voltage drop. However, since the current flowing in the circuit on the load side is extremely small due to the sleep mode, the generated power loss is significantly larger than that in the normal operation. Get smaller. However, in order to operate the reference voltage source VR and the voltage stabilization circuit 1 even in the sleep mode, the circuits of the reference voltage source VR and the voltage stabilization circuit 1 are configured so that the operating current is about several tens of μA or less. There is a need.

  The present invention can be applied to an application for supplying a constant voltage stepped down from an unstable input voltage such as a battery or a generator to an on-vehicle electronic control device.

It is a circuit diagram of the power supply circuit which concerns on the Example of this invention. It is a circuit diagram of the conventional power supply circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Voltage stabilization circuit 2 Noise removal circuit 3 Voltage adjustment circuit A Power supply device C1, C2 Capacitor CT Sleep mode input D Diode ICa Semiconductor integrated circuit device INV Inverter M1, M2, M3, M4 MOS transistor OP1, OP2 Differential amplifier OUT Power supply output Q Bipolar transistors R1, R2, R3, R4, R5, R6 Resistor VR Reference voltage source ZD Zener diode

Claims (5)

A noise removing circuit that removes noise superimposed on the input voltage and generates an output voltage having a voltage value in response to the control signal;
A voltage stabilization circuit that stabilizes the output voltage of the noise removal circuit and outputs it to the load side;
A voltage adjustment circuit that outputs the control signal so as to set the value of the output voltage of the noise removal circuit with respect to the value of the input voltage;
A power supply circuit comprising: The noise removal circuit includes a first transistor between an input terminal and an output terminal to the voltage stabilization circuit,
The voltage adjustment circuit is configured to detect a voltage of an output terminal to the voltage stabilization circuit and control a control terminal of the first transistor so as to become the predetermined voltage. The power supply circuit according to claim 1.   The voltage stabilizing circuit includes a second transistor between an input terminal and an output terminal to the load side, and a control terminal of the second transistor is set so that an output voltage to the load side is constant. The power supply circuit according to claim 1, wherein the power supply circuit is configured to be controlled. It has a mode input terminal,
The voltage regulator circuit is configured to operate when the mode input terminal is set to the first mode, and to stop operating when the mode input terminal is set to the second mode. The power supply circuit according to claim 1 or 2. The voltage stabilization circuit is included in a predetermined semiconductor integrated circuit device, and the first transistor included in the noise removal circuit is configured at least outside the predetermined semiconductor integrated circuit device. The power supply circuit according to claim 2.

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