JP2007155828A - Image forming apparatus and control method of image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect open/close states of a plurality of interlock switches without malfunctions by a circuit configuration that does not require addition of switches or photointerrupters. <P>SOLUTION: An image forming apparatus includes a second power source capable of supplying a second supply voltage lower than a first supply voltage; a control part for generating a switching signal for switching a power source to the second power source, on the basis of a detection result of a first detection circuit, which shows that a first switch is in an open state; a power source switching circuit for causing the second supply voltage to be supplied from the second power source to a second switch by the switching signal generated in the control part; and a second detection circuit for outputting a signal for detecting the open/close state of the second switch, on the basis of the second supply voltage supplied from the second power source. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image forming apparatus capable of detecting an open / closed state of a plurality of open / close mechanisms without malfunctioning, and a control method thereof.

  In recent years, during maintenance work such as jam handling or cartridge replacement that occurs in a copier or printer, a user directly touches a movable part such as a paper feed roller inside the apparatus or a high voltage part such as a high-voltage power supply device. There is a fear. Therefore, it is necessary to take measures to forcibly turn off the power supply to the image forming apparatus during maintenance work.

  From such a background, an image forming apparatus including a safety device for ensuring the safety of a user is becoming widespread. Using an interlock switch that can open and close contacts in conjunction with the opening and closing of the door cover provided on the housing, it detects the door cover open / closed state and controls the power supply to each part inside the device Products equipped with safety devices (interlock circuits) have been commercialized.

  For example, Patent Document 1 discloses a door cover opening / closing detection device that does not use a switch or a photo interrupter that separately detects opening / closing of a door cover by providing an interlock switch with a function of detecting opening / closing of a door cover. .

Further, Patent Document 2 discloses an image forming apparatus that detects opening / closing of a door cover without malfunctioning in an open / closed state by capturing a plurality of interlock state changes.
Japanese Patent No. 3175471 JP 2003-320731 A

  However, in the cover open / close detection device that does not use a switch or a photo interrupter disclosed in Patent Document 1, a single interlock switch is used to shut off a plurality of power supplies, and the bundling lines connecting the circuits are complicated. was there.

  Further, in the image forming apparatus disclosed in Patent Document 2, when the door cover is opened when the power is turned off, if the next door cover opening / closing operation is not performed, the opening / closing state of the door cover can be detected. There was a problem that I could not.

  FIG. 11 shows an example of a circuit configuration for controlling an interlock mechanism in a conventional image forming apparatus. The drive system power supply voltage is 24V, and the output voltage of 24V is supplied to the high voltage power supply 103, the main motor 104, the fixing motor 105, and the scanner 106 via the interlock switches 100 and 101. Interlock switches 100 and 101 are switches that interlock with opening and closing of a door cover provided in the image forming apparatus. Here, the interlock switch 100 is a switch whose contact is opened and closed in conjunction with opening and closing of a door cover (front door cover) provided on the front side of the image forming apparatus. The interlock switch 101 is a switch that opens and closes a contact in conjunction with opening and closing of a door cover (rear door cover) provided on the rear side of the image forming apparatus. When either the front door cover or the rear door cover is opened, the voltage supply to the high voltage power source 103, the main motor 104, the fixing motor 105, and the scanner 106 is cut off. Then, the voltage value obtained by dividing the voltages V1 and V2 by the resistors (200, 201, 300, 3001) and the reference voltage are compared by the comparators (306, 307), and the two interlock switches (100, 101) are compared. Open / close detection is performed.

  In this circuit, when the interlock switch 100 is closed, 24V is supplied to V1. A voltage higher than the reference voltage is input to the comparator 306, and the comparator 306 outputs a high signal (H). On the other hand, when the interlock switch 100 is open, no voltage is supplied to V1, and the voltage input to the comparator 306 is higher at the reference voltage, so the comparator 306 outputs a Low signal (L). To do.

  Similarly, when the interlock switch 101 is closed, 24V is supplied to V2. A voltage higher than the reference voltage is input to the comparator 307, and the comparator 307 outputs a high signal (H). On the other hand, when the interlock switch 101 is open, no voltage is supplied to V2, and the reference voltage is higher than the voltage input to the comparator 307, so the comparator 307 outputs a Low signal (L). .

  Output signals (signal 1 and signal 2) of the comparators 306 and 307 are input to the CPU. The CPU 102 determines that the interlock switch is closed when the “H” level signal is input, and the interlock switch is open when the “L” level signal is input. FIG. 12 is a diagram illustrating combinations (Nos. 1 to 4) of the open / closed states of the interlock switches 100 and 101 and the signal levels (H and L) of the output signals (1 and 2) output from the comparators 306 and 307. It is.

  However, according to the circuit configuration shown in FIG. 11, when the interlock switch 100 is in the open state (Nos. 3 and 4 in FIG. 12), the output signal 2 of the comparator 307 is not related to the open / close state of the interlock switch 101. Always “L”. For this reason, there is a problem that the open / close state of the interlock switch 101 cannot be detected correctly.

  As shown in FIG. 11, in the conventional image forming apparatus connected with a plurality of interlocks, the protection function of the driving means and the image forming means and the opening / closing detection of the plurality of door covers are always performed without using a switch or a photo interrupter. It is difficult. Therefore, a switch and a photo interrupter for detecting only opening and closing of the door are separately required.

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an image forming apparatus that can monitor the open / close detection of a plurality of open / close mechanisms without malfunctioning by a circuit configuration without adding a switch or a photo interrupter. To do.

In order to achieve the above object, an image forming apparatus according to the present invention includes a first switch that is turned on and off in conjunction with opening and closing of the first opening and closing mechanism, and an ON and OFF that is linked with opening and closing of the second opening and closing mechanism, A second switch connected in series with the first switch, a first power supply for supplying a first power supply voltage for driving the image forming means via the first and second switches, and opening / closing of the first switch An image forming apparatus having a first detection circuit that outputs a signal for detecting a state,
A second power supply capable of supplying a second power supply voltage lower than the first power supply voltage;
Control means for generating a switching signal for switching the power source to the second power source based on a detection result indicating that the first switch by the first detection circuit is in an open state;
Power supply switching means for supplying the second power supply voltage from the second power supply to the second switch side by a switching signal generated by the control means;
A second detection circuit that outputs a signal for detecting an open / closed state of the second switch based on the second power supply voltage supplied from the second power supply;
It is characterized by providing.

  According to the present invention, it is possible to detect the open / closed states of a plurality of open / close mechanisms without malfunctioning by a circuit configuration without adding a switch or a photo interrupter.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration of an interlock circuit in the image forming apparatus according to the first embodiment. In the circuit configuration shown in FIG. 1, 24 V is used as the drive system power supply voltage (first power supply voltage). The drive system power supply voltage 24V is supplied to the transport unit 150, the high voltage power supply 103, the main motor 104, the fixing motor 105, and the scanner 106 via the diode 112 and the interlock switches 100 and 101.

  Interlock switches 100 and 101 are switches that open and close in conjunction with opening and closing of a first opening / closing mechanism (front door) and a second opening / closing mechanism (rear door) provided in the image forming apparatus. When the front door cover (hereinafter simply referred to as “front door”) or the rear door cover (hereinafter also simply referred to as “rear door”) is opened, the high voltage power source 103, the main motor 104, the fixing unit 105, and the scanner 106 are opened. The power supply is cut off.

  In the present embodiment, detection of the open / closed state of the front door and the rear door is described as an example of the maintenance opening / closing mechanism provided in the housing of the image forming apparatus, but the gist of the present invention is this example. Needless to say, it is not limited to the above. For example, the present invention can be applied to a configuration that detects that a maintenance work state is present. The present invention is not limited to the detection of the open / closed state of the front door and the rear door as long as it can detect the maintenance work state for a plurality of mechanisms (units).

  Here, the high-voltage power supply 103 is a power supply unit that converts the DC power supply 24V into a DC high voltage (several kV) for corona discharge. The main motor 104 drives a sheet-like recording medium (paper) and a drum. The fixing motor 105 drives a heat roller for fixing the image transferred on the paper. The scanner 106 is a scanner unit for irradiating a laser beam to form an electrostatic latent image. The thermistor 107 is attached to the fixing device, and the temperature of the heater is detected by monitoring the resistance value by the CPU 102.

  The high-voltage power supply 103, the main motor 104, the fixing motor 105, the scanner 106, and the thermistor 107 constitute image forming means for forming an image on a sheet, and each unit (103 to 107) is driven by supplying a power supply voltage of 24V. .

  The diode 112 is for preventing backflow when the voltage supply of 24V is stopped and 3.3V is supplied. Note that the diode 112 may not be provided as long as the 24V power is always supplied when 3.3V is supplied.

  Next, features of the interlock circuit will be described. When the interlock switch 100 is opened and closed, a power source of a low voltage (3.3 V is shown as an example in FIG. 1) is supplied to the contact V1. In the configuration of the interlock circuit in the present embodiment, a signal 1 indicating the open / closed state of the interlock switch 100 and a switching signal output from the CPU 102 are input to the power supply switching unit 109. The power supply switching unit 109 controls the base voltage of the FET 113 based on the signal 1 and the switching signal, and controls ON / OFF of the FET 113. When the FET 113 is turned on, a low voltage (3.3 V) is supplied to the interlock switch 101 at the subsequent stage.

  When the interlock switch 100 is closed, the drive system power supply voltage 24V is higher than the low voltage (3.3V), and therefore 24V is supplied to the interlock switch 101 regardless of whether the FET 113 is on or off. . The diode 111 is for preventing backflow. Here, although 3.3V is shown as the low voltage, the gist of the present invention is not limited to 3.3V, and a lower voltage may be used in view of malfunction of the circuit and safety.

  FIG. 2 is a diagram illustrating an example of a circuit configuration of the power supply switching unit 109 in the interlock circuit of FIG. In the circuit configuration of FIG. 2, the signal 1 indicating the open / close state of the interlock switch 100 is not directly input to the power supply switching unit 109 but is temporarily input to the NOT circuit 116 via the CPU 102. According to the circuit configuration of FIG. 2, the switching signal transmitted from the CPU 102 and the output signal of the NOT circuit 116 are input to the OR circuit 115, and ON / OFF of the FET 113 can be controlled based on the result of the logical operation. Note that the configuration of the power supply switching unit 109 is not limited to the example of FIG. 2, and may be configured by a logic circuit that can obtain an output for controlling the base voltage based on the signal 1 and the switching signal. is there.

  Next, a method for detecting opening / closing of the front door that operates in conjunction with the interlock switch 100 will be described. The voltage of the contact V0 is divided into about 3V (hereinafter referred to as “3V”) by the resistor 200 (47 KΩ) and the resistor 201 (6.8 KΩ). The comparator 110 compares this voltage value with a voltage value using, for example, 2 V as a reference voltage (voltage divided by the resistor 202 and the resistor 203), and detects the opening / closing of the interlock switch 100. A diode 205 is connected to the positive input side of the comparator 110, and a resistor 204 is connected to the output side.

  In this interlock circuit, when the interlock switch 100 is closed, 24V is supplied to the contacts V0 and V1. 24 V is divided into 3 V by the resistor 200 (47 KΩ) and the resistor 201 (6.8 KΩ), and is input to the comparator 110. When the comparator 110 compares the divided input voltage 3V and the reference voltage 2V and determines that the input voltage is higher than the reference voltage, a high (H) signal indicating that the interlock switch 100 is closed. Is output.

  On the other hand, when the interlock switch 100 is in the open state, no voltage is supplied to the contacts V0 and V1, and the input voltage input to the comparator 110 is also zero. In this case, since the reference voltage 2V is higher than the input voltage, the comparator 110 outputs a Low (L) signal indicating that the interlock switch 100 is in an open state.

  This output signal (signal 1) is input to the CPU 102, and the CPU 102 determines the open / closed state of the front door of the image forming apparatus based on the signal 1 indicating a high (H) or low (L) level. can do. That is, the CPU 102 determines that the interlock switch 100 is in a closed state when the signal 1 is a signal indicating “H” level, and the interlock switch 100 is opened when the signal 1 is a signal indicating “L” level. It is determined that it is in a state.

  Further, a method for detecting the opening / closing of the interlock switch 101 in conjunction with the opening / closing of the rear door of the image forming apparatus will be described. In this case, since the determination criteria differ depending on the open / close state of the interlock switch 100, the following description will be made according to the open / close state of the interlock switch 100.

(When interlock switch 100 is closed)
When the interlock switch 100 is in the closed state, 24V is also supplied to the subsequent circuit. Therefore, the voltage supplied to the contact V2 is determined by the open / close state of the interlock switch 101.

  When the interlock switch 101 is open, 0V is supplied to the contact V2. When the interlock switch 101 is closed, 24V is supplied to the contact V2. The 24V supplied to the contact V2 is divided to about 3V (hereinafter referred to as “3V”) by the resistor 206 (47KΩ) and the resistor 207 (6.8KΩ), and then is supplied to the analog / digital (A / D) converter 108. Input and A / D conversion. By this A / D conversion, the value is converted to “0” in the open state, and is converted to a value larger than “0” in the closed state. For example, when the A / D converter 108 is 8 bits, it is converted to a value close to “255”. The output of the A / D converter 108 is input to the CPU 102 as the signal 2. For example, the CPU 102 can set the threshold value to 128 and detect the open / close state of the interlock switch 101 based on the signal 2 output from the A / D converter 108. The threshold value setting by the CPU 102 can be selected in the range of 1 to 254 in the case of an 8-bit converter in consideration of variations in resistance value.

(When interlock switch 100 is open)
When the interlock switch 100 is in an open state, 24V is not supplied to the subsequent circuit. In this case, the signal 1 indicating the open state of the interlock switch 100 and the switching signal output from the CPU 102 are input to the power supply switching unit 109, and the FET 113 functioning as the second power supply voltage is controlled to be ON. When the FET 113 is controlled to be ON, (3.3V-VF1 (forward rising voltage of the diode 111)) V is supplied to the circuit on the interlock switch 101 side.

  When the interlock switch 101 is in the closed state, the voltage at the contact V2 is (3.3−VF1) V. Further, when the interlock switch 101 is in the open state, the voltage at the contact V2 becomes zero. At this time, even if (3.3-VF1) V is supplied to the high-voltage power supply 103, the main motor 104, the fixing motor 105, and the scanner 106, the driving voltage is not satisfied, so that each element does not malfunction. The circuit configuration ensures user safety. Further, since the door opening / closing detection may be detected every several hundred ms, the CPU 102 and the power supply switching unit 109 can control the operation of the FET 113 in accordance with the door opening / closing detection timing.

  The voltage of the contact V2 is divided by the resistor 206 and the resistor 207, input to the A / D comparator 108, and the CPU 102 can determine the open / close state of the interlock switch based on the converted digital value.

  When the interlock switch 101 is open, the CPU 102 can read “0” as the output of the A / D converter 108.

  Further, when the interlock switch 101 is in the closed state, the voltage value obtained by dividing (3.3−VF1) V is digitally converted, so that the CPU 102 converts the voltage value slightly larger than “0” into a digital value. Can be read as For example, if VF1 is 0.7V, (3.3-0.7) = 2.6V is supplied to the contact V2.

  By dividing 2.6 V, 2.6 × (resistor 207 (6.8 KΩ) / (resistor 206 (47 KΩ) + resistor 207 (6.8 KΩ)) = 0.33 V is A / D converted. In the case of a bit A / D converter, it is converted to 255 × (0.33 / 3.3) ≈26.

  However, when the threshold value set in the A / D converter 108 is the same as the threshold value (for example, 128) when 24V is divided and converted to a digital value, the interlock switch 101 based on the voltage supplied from the FET 113 is used. The open / closed state of cannot be accurately determined. Therefore, when the signal 1 is at the L level, the CPU 102 switches and sets the threshold value of the A / D converter 108. For example, the CPU 102 can detect the open / closed state of the interlock 101 by setting the threshold for determining whether the interlock switch is open / closed to be lower than the A / D conversion value “26” in the closed state. .

  Here, the MAX value of the A / D converter is set to 3.3V, but is not limited to 3.3V. If the CPU 102 drives to 5V, the MAX value may be set to 5V. Good.

  FIG. 3 is a flowchart for explaining the process flow of the opening / closing detection operation in the interlock circuit according to the first embodiment.

  In step S100, the CPU 102 starts door opening / closing detection.

  In step S101, first, in order to detect opening / closing of the front door, it is detected whether the signal 1 is H level or L level. If the signal output from the comparator 110 is at 1H level (S101-YES), the process proceeds to S102, and if it is L level (S101-NO), the process proceeds to step S103.

  In step S102, the CPU 102 detects whether the signal 2 output from the A / D converter 108 is H level or L level. If it is at the H level (S102-YES), the process proceeds to step S105, and the CPU 102 detects that the front door is closed and the rear door is also closed.

  On the other hand, if it is determined in step S102 that the signal 2 is at L level (S102-NO), the process proceeds to step S106, and the CPU 102 detects that the front door is closed and the rear door is open.

  If it is determined in step S101 that the signal 1 is at the L level (S101-NO), the process proceeds to step S103, the FET 113 functioning as the second power supply voltage supply means is controlled to be turned on, and the second power A voltage is supplied (in the case of FIG. 1, (3.3-VF1) V).

  Next, in step S <b> 104, the CPU 102 performs switching and setting of a threshold value for determining whether the interlock switch 101 is opened or closed.

  In step S107, the digitally converted value (signal 2) is compared with the set threshold value. If the digitally converted value is greater than the threshold (S107—YES), the process proceeds to step S108.

  In step S108, the CPU 102 detects that the front door is open and the rear door is closed. On the other hand, if the digitally converted value is smaller than the threshold value (S107-NO), the process proceeds to step S109, and the CPU 102 detects that the front door is open and the rear door is open.

  Thereafter, the process proceeds to step S110, the CPU 102 restores the switched threshold value, and controls the power supply switching unit 109 to stop the voltage supply from the FET 113 functioning as the second power supply voltage supply unit in step S111. To do.

  When opening / closing is detected as described above, the process proceeds to step S112 to end the process.

  As described above, according to the present embodiment, it is possible to detect the open / closed states of a plurality of open / close mechanisms without malfunctioning by a circuit configuration without adding a switch or a photo interrupter.

  Further, it is not necessary to secure a space for separately providing a photo interrupter or a switch for detecting only opening / closing of the door cover, and the image forming apparatus can be reduced in size and cost.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 4 is a diagram showing the configuration of the interlock circuit according to the second embodiment, and the same reference numerals are assigned to the same components as those in the configuration of the first embodiment (FIG. 1).

  In the second embodiment, the FET 114 can be controlled by the ON / OFF signal output from the CPU 102 to supply or stop the 24V output. In FIG. 4, separate output signals are used as switching signals to the FET 114 and the power supply switching unit 109, but a common signal may be used. With this configuration, the 24V power line and the 3.3V line can be separated.

  FIG. 5 is a flowchart for explaining the flow of processing of the opening / closing detection operation in the interlock circuit according to the second embodiment.

  In step S200, the CPU 102 starts door opening / closing detection.

  In step S201, first, in order to detect opening / closing of the front door, it is detected whether the signal 1 is at H level or L level. If the signal output from the comparator 110 is at the 1H level (S201-YES), the process proceeds to S202. If the signal is at the L level (S201-NO), the process proceeds to step S203.

  In step S202, the CPU 102 detects whether the signal 2 output from the A / D converter 108 is H level or L level. If it is at the H level (S202—YES), the process proceeds to step S206, and the CPU 102 detects that the front door is closed and the rear door is also closed.

  On the other hand, if it is determined in step S202 that the signal 2 is at the L level (S202-NO), the process proceeds to step S207, and the CPU 102 detects that the front door is closed and the rear door is open.

  If it is determined in step S201 that the signal 1 is at the L level (S201-NO), the process proceeds to step S203, and the CPU 102 controls the FET 114 functioning as the first power supply voltage supply unit to be turned off.

  In step S204, the CPU 102 controls the FET 113 functioning as the second power supply voltage supply unit to be turned on. By controlling the FET 113 to be ON, it becomes possible to supply (3.3−VF1) V as the second power supply voltage to the interlock switch 101 side.

  Next, in step S205, the CPU 102 performs switching and setting of a threshold value for determining whether the interlock switch 101 is opened or closed.

  In step S208, a value obtained by digitally converting the divided voltage value (signal 2) is compared with a set threshold value. If the digitally converted value is greater than the threshold (S208—YES), the process proceeds to step S209.

  In step S209, the CPU 102 detects that the front door is open and the rear door is closed. On the other hand, if the digitally converted value is smaller than the threshold value (S208-NO), the process proceeds to step S210, and the CPU 102 detects that the front door is open and the rear door is open.

  Thereafter, the process proceeds to step S211, and the CPU 102 restores the switched threshold value.

  In step S212, the CPU 102 controls the power supply switching unit 109 so as to stop (OFF) the voltage supply from the FET 113 functioning as the second power supply voltage supply unit.

In step S213, the CPU 102 controls the FET 114 to be ON so as to start voltage supply from the FET 114 functioning as the first power supply voltage supply means.
Thereafter, the process proceeds to S211, the threshold is restored, the supply of the second power is stopped (S212), and the supply of 24V power is started (S213).

  If opening / closing is detected as described above, the process proceeds to step S214 to end the process.

(Modification of the second embodiment)
FIG. 8A is a diagram showing a modification of the interlock circuit shown in FIG. FIG. 8B is a flowchart for explaining the flow of processing for detecting the open / closed state of the interlock switches 100 and 101 based on the circuit configuration of FIG. 8A. Hereinafter, this example will be described with reference to both the drawings. In the circuit configuration shown in FIG. 8A, the circuit configuration on the interlock switch 101 side is the same as that in FIG. 4, but the circuit configuration on the interlock switch 100 side is different from FIG. 4 in that the comparator 110 is not used. The voltage at the contact V 0 is divided by the resistors 200 and 201, and the divided voltage is input to the A / D converter 108. The divided voltage is converted into a digital value and input to the CPU 102 (signal 1).

  Here, a first threshold value for detecting the open / closed state of the interlock switch 100 is set in the CPU 102 based on the signal 1 converted into a digital value, and the magnitude relationship between the input signal 1 and the first threshold value is set. Based on this, the open / close state of the interlock switch 100 is detected.

  In step S800, door open / close detection processing is started under the control of the CPU. In step S801, the CPU 102 compares the first threshold value with the signal 1 converted into a digital value. If the signal 1 is greater than the first threshold value, the interlock switch 100 (front door) is in the closed state. Determination is made (S802).

  The voltage at the contact V2 is divided by the resistors 206 and 207, and the divided voltage is input to the A / D converter 108. The divided voltage is converted into a digital value and input to the CPU 102 (signal 2). The CPU 102 is set with a second threshold value for detecting the open / closed state of the interlock switch 101 based on the signal 2 converted into a digital value. Based on the magnitude relationship between the input signal 2 and the second threshold value. Thus, the open / close state of the interlock switch 100 is detected.

  In step S803, the CPU 102 compares the second threshold value with the signal 2 converted into a digital value, and if the signal 2 is larger than the second threshold value, the interlock switch 101 (rear door) is in the closed state. Determination is made (S804).

  In step S803, if the signal 2 is smaller than the second threshold, the CPU 102 determines that the interlock switch 101 (rear door) is in the open state (S805).

  In step S807, the FET 113 functioning as the second power supply voltage supply means is controlled to be turned on to supply the second power supply voltage (in the case of FIG. 1, (3.3-VF1) V).

  In step S808, the CPU 102 performs switching and setting of a threshold value in order to determine whether the interlock switch 101 is opened or closed. Here, the threshold value is switched and set from the second threshold value corresponding to 24V supplied from the FET 114 to the third threshold value corresponding to (3.3−VF1) V supplied from the FET 113.

  In step S809, the digitally converted value (signal 2) is compared with the set third threshold value. If the digitally converted value is greater than the third threshold (S810—YES), the process proceeds to step S810.

  In step S810, the CPU 102 detects that the rear door is closed. On the other hand, if the digitally converted value is smaller than the third threshold (S809-NO), the process proceeds to step S811, and the CPU 102 detects that the rear door is in the open state.

  Thereafter, the process proceeds to step S812, and the CPU 102 returns the switched third threshold value to the second threshold value. In step S813, the power source switching is performed so as to stop the voltage supply from the FET 113 functioning as the second power source voltage supply unit. The unit 109 is controlled.

  And a process is complete | finished by step S814.

  As described above, according to the present embodiment, it is possible to detect the open / closed states of a plurality of open / close mechanisms without malfunctioning by a circuit configuration without adding a switch or a photo interrupter.

  Further, it is not necessary to secure a space for separately providing a photo interrupter or a switch for detecting only opening / closing of the door cover, and the image forming apparatus can be reduced in size and cost.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 6 is a diagram showing the configuration of the interlock circuit according to the third embodiment, and the same reference numerals are assigned to the same components as those in the configuration of the first embodiment (FIG. 1).

  In the circuit configuration of the third embodiment, as shown in FIG. 6, the resistor 208 and the FET 209 are connected in parallel between the contact V2 and the contact V3, and the ON / OFF of the FET 209 is switched to switch the voltage at the contact V3. It is characterized by that.

  The CPU 102 outputs a switching signal, and this switching signal is input to the power source switching unit 109 and the base of the FET 209. Based on the switching signal input to the base of the FET 209, the CPU 102 can control ON / OFF of the FET 209.

  When the FET 209 is ON, the voltage at the contact V3 is determined by the ratio of the resistor 206 and the resistor 207.

  That is, the voltage of the contact V3 = the voltage of the contact V2 × the resistance value of the resistor 207 / (the resistance value of the resistor 206 + the resistance value of the resistor 207).

  On the other hand, when the FET 209 is OFF, the voltage at the contact V3 is determined by the ratio of the ratio of the resistor 208 and the resistor 206 to the resistor 207.

  In this case, the voltage of the contact V3 = the voltage of the contact V2 × the resistance value of the resistor 207 / (the resistance value of the resistor 208 + the resistance value of the resistor 206 + the resistance value of the resistor 207).

  In the first and second embodiments, when 3.3V is supplied as the second power supply voltage, the voltage input to the A / D converter 108 is a low voltage of about 0.33V. On the other hand, by adopting the configuration shown in FIG. 6, the voltage at V3 input to the A / D converter 108 can be increased by 1 V or more, so that open / close detection is accurately performed without being affected by variations in resistance and setting of threshold values. It becomes possible to do.

(Fourth embodiment)
FIG. 7 is a diagram showing the configuration of the interlock circuit according to the fourth embodiment of the present invention. The same reference numerals are given to the same components as those of the second embodiment (FIG. 4). Yes.

  In the circuit configuration of the fourth embodiment, the power supply switching unit 109 includes a comparator 117 as a circuit configuration. In the circuit configuration of FIG. 4, the signal 1 output from the comparator 110 is once input to the CPU 102, and the CPU 102 outputs a switching signal to the power supply switching unit 109 based on the input signal. On the other hand, in the circuit configuration of FIG. 7, the signal 1 output from the comparator 110 is input to the CPU 102 and also to the comparator 117. The comparator 117 compares the input signal 1 with a reference voltage obtained by dividing 3.3V by the resistor 210 and the resistor 211, and controls ON / OFF of the FET 113 based on the comparison.

  In FIG. 7, an example in which both the resistor 210 and the resistor 211 are set to 1 KΩ and 1.5 V (reference voltage) is input to the minus side of the comparator 117 will be described. When the interlock switch 100 is in the closed state, the signal 1 becomes H level (3.3 V), and the comparator 117 outputs a High (H) level signal indicating that the signal 1 is higher than the reference voltage. In this case, since the FET 113 is not turned on, the second power supply voltage (3.3-VF1) V from the FET 113 is not supplied. On the other hand, when the interlock switch 100 is in the open state, the signal 1 is at the Low (L) level, and the comparator 117 outputs an L level signal. Since the FET 113 is controlled to be ON based on the L level signal 1, the second power supply voltage (3.3-VF1) V is supplied from the FET 113 to the interlock switch 101 side.

  According to this circuit configuration, it is possible to control the second power supply voltage supply means in conjunction with detection of the open / close state of the interlock switch 100 without going through the CPU 102 (while reducing the load on the CPU 102).

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. FIG. 9 is a diagram showing the configuration of the interlock circuit according to the fifth embodiment. The same components as the configuration of the first embodiment (FIG. 1) and the configuration of the second embodiment (FIG. 4) are shown in FIG. , Are given the same reference numbers.

  The fifth embodiment is characterized in that a power supply IC 118 (regulator) is used as the second power supply voltage supply means. With this circuit configuration, the power supply IC 118 is turned on only when the interlock switch 100 is in the open state, and it is possible to supply power to the subsequent circuit on the interlock switch 101 side.

  In the circuit configuration of FIG. 9, the signal 1 indicating the open / close state of the interlock switch 100 is used as the enable signal of the regulator 118, but the CPU 102 that has received the signal 1 outputs an enable signal to the regulator 118. It may be configured. With the circuit configuration of FIG. 9, it is possible to detect opening / closing of the interlock switches 100 and 101 as in the above-described embodiments.

  That is, according to the present embodiment, it is possible to detect the open / closed states of a plurality of open / close mechanisms without malfunctioning by a circuit configuration without adding a switch or a photo interrupter.

  Further, it is not necessary to secure a space for separately providing a photo interrupter or a switch for detecting only opening / closing of the door cover, and the image forming apparatus can be reduced in size and cost.

(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described. FIG. 10 is a diagram showing the configuration of the interlock circuit according to the sixth embodiment, and the same reference numerals are assigned to the same components as those in the configuration of the first embodiment (FIG. 1). This circuit configuration is different from the circuit configuration of FIG. 1 in that an FET 120 functioning as third voltage supply means is provided in addition to the FET 113 functioning as second power supply voltage supply means. Here, the relationship of the supply voltage is 24> Va ≧ Vb (V).

  Furthermore, unlike the circuit configuration in the first embodiment, the circuit configuration in FIG. 10 is provided with three switches that operate in conjunction with door opening and closing. Since the open / close detection method of the interlock switch 100 and the interlock switch 101 is the same as the process flow in the first embodiment, the description thereof will be omitted here, and the open / close detection method of the interlock switch 119 will be described below.

(When interlock switches 100 and 101 are closed)
When both the interlock switch 100 and the interlock switch 101 are closed, 24 V supplied from the power supply voltage is supplied to the contact V2. The voltage supplied to the contact V3 is determined by the open / close state of the interlock switch 119. That is, when the interlock switch 119 is in the open state, the contact V3 is 0 V, and when it is in the closed state, 24 V is supplied to the contact V3. The voltage at the contact V3 is divided by the resistor 212 and the resistor 213, and converted from an analog value to a digital value by the A / D converter 118. The A / D converter 118 outputs the value converted to the digital value as the signal 3 to the CPU 102. The CPU 102 can detect the open / closed state of the interlock switch 119 based on the set threshold and the signal 3 input from the A / D converter 118.

  When the digitally converted value (signal 3) is larger than the threshold value, the CPU 102 detects that the interlock switch 119 is closed. On the other hand, when the digitally converted value (signal 3) is smaller than the threshold value, the CPU 102 detects that the interlock switch 119 is in the open state.

(When interlock switch 100 is open and 101 is closed)
Next, the case where the interlock switch 100 is in the open state and the interlock switch 101 is in the closed state will be described. In this case, the second power supply voltage is supplied from the FET 113 functioning as the second power supply voltage supply means. Thereby, the voltage of the contact V2 becomes (Va-VF1 (rising voltage of the diode 111)) V. The voltage at the contact V3 is determined by the open / close state of the interlock switch 119. When the interlock switch 119 is open, the voltage at the contact V3 is 0V, and when it is closed, the voltage at the contact V3 is (Va-VF1) V.

  The voltage at the contact V3 is divided by the resistor 212 and the resistor 213 and converted into a digital value by the A / D converter 118. The A / D converter 118 outputs the value converted to the digital value as the signal 3 to the CPU 102. The CPU 102 switches and sets a threshold value for the A / D converter 118 based on the input of the signal 1 indicating that the interlock switch 100 is in the open state. The CPU 102 detects the open / close state of the interlock switch 119 based on the switched and set threshold values and the signal 3 input from the A / D converter 118.

  When the digitally converted value (signal 3) is larger than the switching threshold, the CPU 102 detects that the interlock switch 119 is closed. On the other hand, if the digitally converted value (signal 3) is smaller than the threshold value set for switching, the CPU 102 detects that the interlock switch 119 is in the open state.

  After the open / close detection, the CPU 102 returns the threshold value setting to before switching, and controls the power supply switching unit 109 to stop the voltage supply from the FET 113.

  The above processing corresponds to the processing from step S104 to S111 in FIG.

(When interlock 101 is open)
Next, a case where the interlock switch 101 is in an open state will be described. In this case, regardless of the open / close state of the interlock switch 100, the voltage at the contact V3 is OV. That is, when the interlock switch 101 is in the open state, the voltage at the contact V2 is 0V, and the signal 2 output from the A / D converter 108 is 0. When 0 is input as the signal 2 to the CPU 102, the CPU 102 determines that the interlock switch 101 is in the open state based on the signal 2 being 0, and switches the power supply to the switching signal for turning on the FET 120. To the unit 122.

  When the FET 120 is controlled to be in the ON state based on the switching signal, the interlock switch 119 is closed and the voltage at the contact V3 becomes (Vb−VF2 (rising voltage of the diode 121)) V. When the interlock switch 119 is open, the voltage at the contact V3 is 0V even if the FET 120 is in the ON state.

  0V or (Vb−VF2) is input to the A / D converter 118 divided by the resistor 212 and the resistor 213 as the voltage of the contact V3. The conversion result of the A / D converter 118 is input to the CPU 102 as the signal 3.

  The CPU 102 switches and sets the threshold for the A / D converter 118 based on the input of the signal 2 indicating that the interlock switch 101 is in the open state. The CPU 102 detects the open / close state of the interlock switch 119 based on the switched and set threshold values and the signal 3 input from the A / D converter 118.

  When the digitally converted value (signal 3) is larger than the switching threshold, the CPU 102 detects that the interlock switch 119 is closed. On the other hand, if the digitally converted value (signal 3) is smaller than the threshold value set for switching, the CPU 102 detects that the interlock switch 119 is in the open state.

  After the opening / closing detection, the CPU 102 returns the setting of the threshold value to before switching, and controls the power supply switching unit 122 so as to stop the voltage supply from the FET 120.

  The above processing corresponds to the processing from step S104 to S111 in FIG.

  In this embodiment, an example of detecting the open / closed state of the three interlock switches has been shown. However, the gist of the present invention is not limited to this, and N (N is a natural number of 3 or more) interlocks. It is also possible to detect the open / closed state of the switch.

  In this case, the image forming apparatus is turned ON / OFF in conjunction with the opening / closing of the Nth opening / closing mechanism with respect to the circuit configuration of FIG. 1, and is connected in series with the (N−1) th switch. A natural number of 3 or more). The image forming apparatus further includes an Nth power supply capable of supplying an Nth power supply voltage lower than the first power supply voltage (24V). Here, the relationship between the supply voltages is 24> Va ≧ Vb...> Vn-1 ≧ Vn ≧ Vn + 1 (V) (n is a natural number of 3 or more).

  The image forming apparatus further includes a power supply switching unit (N is a natural number of 3 or more) that supplies the Nth power supply voltage from the Nth power supply to the Nth switch side by a switching signal generated by the control unit (CPU 102). The image forming apparatus further includes an Nth detection circuit (N is a natural number of 3 or more) that outputs a signal for detecting the open / closed state of the Nth switch based on the Nth power supply voltage supplied from the Nth power supply. Prepare.

  Here, the control unit (CPU 102) determines the Nth switch based on the detection result indicating that the first switch to the (N-1) switch by any one of the first detection circuit to the (N-1) th detection circuit is in the open state. A switching signal for switching the power source to the power source is generated.

  As described above, according to the present embodiment, it is possible to detect the open / closed states of a plurality of open / close mechanisms without malfunctioning by a circuit configuration without adding a switch or a photo interrupter.

  Further, it is not necessary to secure a space for separately providing a photo interrupter or a switch for detecting only opening / closing of the door cover, and the image forming apparatus can be reduced in size and cost.

(Other embodiments)
Needless to say, the object of the present invention can also be achieved by supplying a storage medium storing software program codes for realizing the functions of the above-described embodiments to a system or apparatus. Needless to say, this can also be achieved by the computer (or CPU or MPU) of the system or apparatus reading and executing the program code stored in the storage medium.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for supplying the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a nonvolatile memory card, a ROM, or the like can be used.

  Further, the functions of the above-described embodiment are realized by executing the program code read by the computer. In addition, an OS (operating system) running on a computer performs part or all of actual processing based on an instruction of a program code, and the above-described embodiment is realized by the processing. Needless to say.

FIG. 3 is a diagram illustrating a configuration of an interlock circuit in the image forming apparatus according to the first embodiment. FIG. 2 is a diagram illustrating an example of a circuit configuration of a power supply switching unit in the interlock circuit of FIG. 1. 5 is a flowchart for explaining the flow of processing of an open / close detection operation in the interlock circuit according to the first embodiment. It is a figure which shows the structure of the interlock circuit which concerns on 2nd Embodiment. It is a flowchart explaining the flow of a process of the opening / closing detection operation | movement in the interlock circuit which concerns on 2nd Embodiment. It is a figure which shows the structure of the interlock circuit concerning 3rd Embodiment. It is a figure which shows the structure of the interlock circuit concerning 4th Embodiment. It is a figure which shows the modification of the interlock circuit shown in FIG. It is a flowchart explaining the flow of the process for detecting the opening / closing state of an interlock switch based on the circuit structure of FIG. 8A. It is a figure which shows the structure of the interlock circuit which concerns on 5th Embodiment. It is a figure which shows the structure of the interlock circuit which concerns on 6th Embodiment. It is a figure which shows an example of the circuit structure for controlling the interlock mechanism in the conventional image forming apparatus. It is a figure which shows the combination of the open / close state of the interlock switch in the conventional image form apparatus, and the output signal output from a comparator.

Claims (12)

A first switch that is turned on / off in conjunction with opening / closing of the first opening / closing mechanism, a second switch that is turned on / off in conjunction with opening / closing of the second opening / closing mechanism, and is connected in series with the first switch; A first power supply for supplying a first power supply voltage for driving the image forming means via the first and second switches; a first detection circuit for outputting a signal for detecting the open / closed state of the first switch; An image forming apparatus having
A second power supply capable of supplying a second power supply voltage lower than the first power supply voltage;
Control means for generating a switching signal for switching the power source to the second power source based on a detection result indicating that the first switch by the first detection circuit is in an open state;
Power supply switching means for supplying the second power supply voltage from the second power supply to the second switch side by a switching signal generated by the control means;
A second detection circuit that outputs a signal for detecting an open / closed state of the second switch based on the second power supply voltage supplied from the second power supply;
An image forming apparatus comprising: The image forming apparatus according to claim 1, wherein the second detection circuit includes an analog-to-digital conversion circuit that converts a voltage value based on the second power supply voltage from an analog value to a digital value. 2. The control unit according to claim 1, wherein the control unit switches a threshold value for determining an open / closed state of the second switch based on a detection result indicating that the first switch is opened by the first detection circuit. The image forming apparatus according to 2. The control means determines the open / closed state of the second switch based on a comparison between the threshold value and a value output from the second detection circuit and converted into a digital value by the analog-digital conversion circuit. The image forming apparatus according to claim 1, wherein the image forming apparatus is an image forming apparatus. A first power supply control element for controlling supply and stop of the first power supply voltage;
The control means controls the first power supply control element to stop the supply of the first power supply voltage based on a detection result indicating that the first switch is opened by the first detection circuit. The image forming apparatus according to claim 1. The second detection circuit further includes a switching element for controlling a resistance value for dividing the second power supply voltage supplied from the second power supply,
The image forming apparatus according to claim 1, wherein the control unit controls the operation of the switching element based on a detection result indicating that the first switch is opened by the first detection circuit. A first switch that is turned on / off in conjunction with opening / closing of the first opening / closing mechanism, a second switch that is turned on / off in conjunction with opening / closing of the second opening / closing mechanism, and is connected in series with the first switch; An image forming apparatus comprising: a first power supply that supplies a first power supply voltage for driving the image forming means via the first and second switches;
A detection circuit that outputs a digital signal for detecting an open / closed state of each of the first switch and the second switch;
A second power supply capable of supplying a second power supply voltage lower than the first power supply voltage;
Control means for generating a switching signal for switching the power source to the second power source based on a detection result indicating that the first switch by the detection circuit is in an open state;
Power supply switching means for controlling the second power supply according to a switching signal generated by the control means and supplying the second power supply voltage to the second switch side,
The control means switches a threshold value for determining an open / closed state of the second switch based on a detection result indicating that the first switch is open by the detection circuit,
An image forming apparatus, wherein the open / close state of the second switch is determined based on a comparison between the switched threshold and an output signal from the detection circuit. The image forming apparatus according to claim 1, wherein the second power source is configured by an FET or a regulator that supplies a voltage lower than the first power source voltage. N-th switch (N is a natural number of 3 or more) that is turned on / off in conjunction with opening / closing of the N-th opening / closing mechanism and connected in series with the (N-1) th switch;
An Nth power supply (N is a natural number of 3 or more) capable of supplying an Nth power supply voltage lower than the first power supply voltage;
Nth power supply switching means (N is a natural number of 3 or more) for supplying the Nth power supply voltage from the Nth power supply to the Nth switch side by a switching signal generated by the control means;
An Nth detection circuit (N is a natural number of 3 or more) for outputting a signal for detecting an open / closed state of the Nth switch based on the Nth power supply voltage supplied from the Nth power supply; The image forming apparatus according to claim 1. The control means includes the first switch to the (N-1) switch (N is a natural number of 3 or more) according to any one of the first detection circuit to the (N-1) th detection circuit (N is a natural number of 3 or more). 10. The image forming apparatus according to claim 1, wherein a switching signal for switching a power source to the Nth power source is generated based on a detection result indicating an open state. A first switch that is turned on / off in conjunction with opening / closing of the first opening / closing mechanism, a second switch that is turned on / off in conjunction with opening / closing of the second opening / closing mechanism, and is connected in series with the first switch; A first power supply for supplying a first power supply voltage for driving the image forming means via the first and second switches; a first detection circuit for outputting a signal for detecting the open / closed state of the first switch; And a second power supply capable of supplying a second power supply voltage lower than the first power supply voltage.
A control step of generating a switching signal for switching the power source to the second power source based on a detection result indicating that the first switch by the first detection circuit is open;
A power source switching step of supplying the second power source voltage from the second power source to the second switch side by a switching signal generated by the control step;
A second detection step of outputting a signal for detecting an open / closed state of the second switch based on the second power supply voltage supplied from the second power supply;
An image forming apparatus control method comprising: A first switch that is turned on / off in conjunction with opening / closing of the first opening / closing mechanism, a second switch that is turned on / off in conjunction with opening / closing of the second opening / closing mechanism, and is connected in series with the first switch; A first power supply for supplying a first power supply voltage for driving the image forming means via the first and second switches; a second power supply capable of supplying a second power supply voltage lower than the first power supply voltage; A method for controlling an image forming apparatus having
A detection step of outputting a digital signal for detecting an open / closed state of each of the first switch and the second switch;
A control step of generating a switching signal for switching the power source to the second power source based on a detection result indicating that the first switch by the detection circuit is in an open state;
A power supply switching step of controlling the second power supply by a switching signal generated by the control step and supplying the second power supply voltage to the second switch side,
The control step switches a threshold value for determining an open / closed state of the second switch based on a detection result indicating that the first switch is open by the detection circuit,
An image forming apparatus control method, comprising: determining an open / closed state of the second switch based on a comparison between the switched threshold and an output signal from the detection circuit.

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