JP2007006663A - Power supply protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply protection circuit that efficiently prevents any malfunction from occurring when a power supply circuit that outputs a plurality of power sources is started. <P>SOLUTION: Overcurrents and overvoltages of DC-DC converters 12<SB>1</SB>-12<SB>n</SB>are detected by detection portions 13<SB>1</SB>-13<SB>n</SB>. AND operation of each detection result is obtained by a logical portion 14 to detect an output abnormality. A changeover portion 15 makes this detection result invalid until the start-up of the DC-DC converter 12<SB>n</SB>to be started up last is detected, and makes the detection result valid after the detection of the start-up of the DC-DC converter 12<SB>n</SB>. An output portion 16 controls a switching element 11 to a closed state when the detection result is made invalid. When the detection result is made valid, the switching element 11 is controlled to the closed state when an output is normal and the element 11 is controlled to an open state if output abnormality is detected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply protection circuit, and more particularly to a circuit that prevents malfunction at the time of startup of a power supply that outputs a plurality of types of power supplies.

  The power supply circuit that outputs a predetermined power supply to the load usually has a power protection circuit that constantly monitors the output power supply and automatically stops the power supply when an abnormality such as overcurrent or overvoltage is detected. Is provided. By providing a power protection circuit, the device can be protected from abnormalities such as overcurrent and overvoltage.

  In Patent Document 1 below, an input power supply is converted into a plurality of constant output voltages and supplied to a plurality of loads, respectively, and a plurality of output voltages are detected. On the other hand, a power supply device has been proposed that can detect abnormalities in a plurality of outputs supplied to the power supply.

JP 2004-357460 A

  By the way, when the power supply is started, that is, at the start of power supply start and immediately after the start of start-up, phenomena such as an overshoot in which the waveform of the output voltage temporarily exceeds a specified level and an inrush current in which a large current flows instantaneously occur. Since the output power supply is not stable, a detection unit that detects abnormalities such as overcurrent and overvoltage of the output power supply may detect these phenomena and malfunction. Since the power supply device of Patent Document 1 does not have a function to prevent malfunction at the time of activation, it is assumed that the detection unit malfunctions and output of the power supply stops.

  In Patent Document 2 below, when an overcurrent that significantly exceeds the rated output current is detected, an overcurrent protection operation is performed immediately, and an overcurrent slightly exceeding the rated output current continues beyond the allowable overcurrent duration. At this time, an overcurrent protection circuit for a switching power supply device configured to perform an overcurrent protection operation has been proposed. Thus, if the overcurrent detection value of the detection unit for detecting overcurrent is set higher than the inrush current, malfunction due to the inrush current at the time of starting the power supply can be prevented.

Japanese Patent Application Laid-Open No. 11-234892

  However, since the overcurrent protection circuit of Patent Document 2 is set to an unnecessarily high overcurrent detection value in a steady state, the device is not sufficiently protected against overcurrent, and high safety cannot be ensured. .

  Therefore, the conventional power supply protection circuit normally provides a period (hereinafter referred to as a mask time as appropriate) when the detection unit is regarded as a standby state when the power supply is started so that the operation of the detection unit becomes invalid in the standby state. As a result, the above-mentioned specific malfunction at the start-up of the power supply is prevented.

FIG. 6 shows an example of the configuration of a conventional power protection circuit. In the power supply protection circuit shown in FIG. 6, the drive power supplied from the power supply path via the switching element 111 is converted into a DC-DC converter (indicated as DD converter in the figure) 112 ₁ , 112 ₂ ,. 112 _n is provided in a power supply circuit that supplies a plurality of types of DC power supplies to a load by supplying each of them to a predetermined voltage.

DC-DC converter 112 _1, 112 _2, ..., 112 _n, when the power source is started, the startup sequence control unit 118, DC-DC converter 112 _1, 112 _2, ..., is controlled to be activated in the order of 112 _n The

Detector _{113 1, 113 2, ...,} 113 n are each DC-DC converter _{112 1, 112 2, ...,} 112 n of the over-current of the output power, overvoltage constantly monitors, during normal high level, abnormal Supplies a low level signal to the logic unit 114 as a detection signal. As a result, the detection units 113 ₁ , 113 ₂ ,..., 113 _n detect these when an output voltage overshoot or inrush current occurs when the power supply is activated.

The logic unit 114 determines whether or not the output power is all normal based on signals supplied from the detection units 113 ₁ , 113 ₂ ,..., 113 _n , and outputs a signal corresponding to the determination result to the output unit. 16 is supplied.

  The mask unit 117 is for avoiding a specific malfunction at the start-up of the power supply by applying a mask for a certain time at the start-up of the power supply, and determines whether the mask time has elapsed after the power supply is started up. Then, a signal corresponding to the determination result is supplied to the output unit 116.

  The output unit 116 generates a control signal for controlling the switching element 111 based on the signals supplied from the logic unit 114 and the mask unit 117, and supplies the generated control signal to the switching element 111. 111 is closed, i.e., on, otherwise it is closed if all output power supply voltages are normal based on the signal from the logic unit 114, and is open, i.e., off if any abnormality is detected. To control.

The activation sequence control unit 118 sets the activation start delay time and activation sequence of each of the DC-DC converters 112 ₁ , 112 ₂ ,..., 112 _n , and the DC-DC converters 112 ₁ , 112 ₂ ,. supplies a control signal based on each of the setting conditions for each 112 _n, DC-DC converter 112 _1, 112 _2, ..., and controls the respective activation of 112 _n. Thereby, DC-DC converter 112 _1, 112 _2, ..., 112 _n may, DC-DC converter 112 at a predetermined timing _1, 112 _2, ..., starts in the order of 112 _n.

FIG. 7 shows an exemplary configuration of the logic unit 114, the output unit 116, and the mask unit 117. The logic unit 114 is configured by an AND circuit 121. Detection signals are supplied from the detection units 113 ₁ , 113 ₂ ,..., 113 _n to the input side of the AND circuit 121. The AND circuit 121 supplies a signal that is a logical product of the detection signals supplied from the detection units 113 ₁ , 113 ₂ ,..., 113 _n to the voltage comparator 122 that constitutes the output unit 116. The voltage comparator 122 compares the voltage supplied from the AND circuit 121 with the threshold voltage V _th3, and supplies a signal corresponding to the comparison result to the switching element 123 configuring the output unit 116.

The mask unit 117 includes a voltage comparator 124 and a CR integration circuit including a capacitor C11 and a resistor R11. The CR integration circuit supplies the voltage of the integrated waveform of the reference voltage V _R to the negative input of the voltage comparator 124. The time until the potential of the capacitor C11 is charged and reaches the threshold value is set as a mask time. The mask time is set by appropriately setting the constant of the CR integration circuit. Note that the threshold voltage V _th2 is supplied to the positive input of the voltage comparator 124.

The voltage comparator 124 compares the threshold voltage V _th2 with the voltage from the CR integration circuit, and supplies a signal corresponding to the comparison result to the control terminal of the switching element 123.

The switching element 123 is controlled to be turned on / off according to a signal supplied to the control terminal. That is, the switching element 123 disables the detection of the abnormality of the output power supply by the detection units 113 ₁ , 113 ₂ ,..., 113 _n and the logic unit 114 and sets the switching element 111 in the closed state within the mask time. Is output to the switching element 111. After the elapse of the mask time, the detection of the output power supply abnormality by the detection units 113 ₁ , 113 ₂ ,..., 113 _n and the logic unit 114 is validated. A control signal for making the closed state is output to the switching element 111, and when it is determined that there is an abnormality, a control signal for making the switching element 111 open is output to the switching element 111.

  Since the voltage of the integral waveform is supplied to the negative input of the voltage comparator 124, the switching element 123 switches after delaying a predetermined time after starting the power supply. As described above, by setting the mask time when the power supply is activated, it is possible to prevent malfunction of the detection unit at the time of activation.

  However, although the power supply protection circuit that sets the mask time by the CR integration circuit as described above can quantitatively determine the charge / discharge characteristics of the CR integration circuit, the steep input power supply ON / OFF that occurs in actual operation can be obtained. In the off state or the like, it is difficult to quantitatively suppress the influence of the residual charge on the charge / discharge characteristics. Therefore, the mask time is lengthened in consideration of this. In addition, since the accuracy of the mask time depends on the accuracy of the resistors and capacitors that make up the CR integration circuit, it was necessary to set the mask time with a margin to the theoretical mask time by an experimental rule. .

  Therefore, an object of the present invention is to provide a power supply protection circuit that can efficiently prevent malfunctions that occur when a power supply circuit that outputs a plurality of power supplies is started.

In order to solve the above-described problem, the present invention includes a switching element that opens and closes a supply path that supplies driving power to a plurality of DC-DC converters;
An abnormality detection unit for detecting an output abnormality of a plurality of DC-DC converters;
Until the activation of the DC-DC converter that is activated last among the plurality of DC-DC converters is detected, the detection result of the abnormality detection unit is invalidated, and the activation of the DC-DC converter that is activated last is activated. After being detected, the activation detection unit that validates the detection result of the abnormality detection unit,
When the detection result of the abnormality detection unit is invalidated by the activation detection unit, the switching element is closed, and when the detection result of the abnormality detection unit is validated by the activation detection unit, an output abnormality is detected by the abnormality detection unit. A power supply protection circuit comprising: a control unit that closes the switching element if not detected, and that opens the switching element when an output abnormality is detected by the abnormality detection unit.

  The activation detection unit can detect the activation of the DC-DC converter activated last based on the output voltage level of the DC-DC converter activated last.

  The activation detection unit and the control unit are preferably configured by a logic circuit.

  The start detection unit outputs to each output of a two-stage Schmitt inverter that receives a switching signal according to the start state of the DC-DC converter that is started last, and a two-stage Schmitt inverter that switches according to the state of the switching signal Based on the totem pole type switch that switches between valid / invalid of the detection result of the anomaly detection unit based on this. More preferably, the totem pole type switch is constituted by a bus switch.

  The activation detection unit preferably includes a delay unit that extends a period during which the detection result of the abnormality detection unit is invalid. As a result, the activation detection unit gives a margin to the period during which the detection result of the abnormality detection unit is invalidated by the delay unit, and finally activates based on the activation control signal that controls the activation of the DC-DC converter that is activated last. It is possible to detect the activation of the DC-DC converter.

  In the present invention, the output abnormality of a plurality of DC-DC converters is detected, and the detection result is invalid until the activation of the DC-DC converter that is activated last among the plurality of DC-DC converters is detected. After the activation of the DC-DC converter to be activated last is detected, the detection result is validated, and when the detection result is invalid, the supply path for supplying drive power to the plurality of DC-DC converters When the switching element that opens and closes is controlled to the closed state and the detection result is validated, the switching element is controlled to the closed state if the abnormality detection unit does not detect the output abnormality, and the abnormality detection unit detects the output abnormality Then, the switching element is controlled to be in an open state.

  According to the present invention, the masking time is shortened, and the power protection function is more effective. In addition, since it is possible to logically determine whether the detection result of the abnormality detection unit is valid or invalid depending on whether or not the last activated DC-DC converter is detected, a masking time is set in advance. Even if it is not, it is possible to prevent malfunction at the time of starting the power supply. Further, even when the activation order of the DC-DC converter is changed, the constant of the mask part is not required as in the case where the CR integration circuit is used for setting the mask time, so that maintenance is facilitated. In addition, since the error (accuracy) of the mask time is improved, the stability of the circuit is improved.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example of the configuration of a power supply protection circuit according to an embodiment of the present invention. One embodiment according to the power supply protection circuit, a driving power source via a switching element 11 is supplied from the power supply path, DC-DC converter 12 _1, 12 _2, ..., and supplied to each of the 12 _n, predetermined in each Is provided in a power supply circuit that converts a plurality of types of DC power supplies to a load. Each component shown in FIG. 1 is operated by a driving power source on the front side of the switching element 11.

The switching element 11 opens and closes a power supply path to the DC-DC converters 12 ₁ , 12 ₂ ,..., 12 _n and is constituted by a power switching transistor such as a field effect transistor or a bipolar transistor. . Power The startup, the switching element 11 is closed, DC-DC converter 12 _1, 12 _2, ..., power is supplied to each of the 12 _n. Details of the operation control of the switching element 11 will be described later.

DC-DC converter 12 _1, 12 _2, ..., 12 _n, when the power supply is activated, the activation sequence controller 18, the DC-DC converter 12 _1, 12 _2, ..., to start in order of 12 _n Be controlled. The startup control order of the DC-DC converters 12 ₁ , 12 ₂ ,..., 12 _n is the same as the normal startup order, that is, the output order of stable power supplies (hereinafter referred to as startup order as appropriate). That is, among the DC-DC converters 12 ₁ , 12 ₂ ,..., 12 _n , the last n-th activation order, that is, the one activated last is the DC-DC converter 12 _n .

The power protection circuit is configured to protect the device from an abnormality in the output power by controlling the opening / closing operation of the switching element 11 using the abnormality detection function, the activation detection function, and the control function. The abnormality detection function is realized by the detection units 13 ₁ , 13 ₂ ,..., 13 _n and the logic unit 14, the activation detection function is realized by the switching unit 15, and the control function is realized by the output unit 16.

Detector _{13 1, 13 2, ...,} 13 n are each DC-DC converter _{12 1, 12 2, ...,} 12 n constantly monitors the output state of the power supply, and binarized by a normal state and abnormal state The signal is supplied to the logic unit 14. That is, the detection unit 13 _1, 13 _2, ..., 13 _n are each DC-DC converter 12 _1, 12 _2, ..., and detects the overcurrent and overvoltage of the power supply output to a load from 12 _n, a detection signal This is supplied to the logic unit 14. As a result, the detectors 13 ₁ , 13 ₂ ,..., 13 _n detect these when an output voltage overshoot or inrush current occurs when the power supply is activated. The detection units 13 ₁ , 13 ₂ ,..., 13 _n assume that they are normal if neither overcurrent nor overvoltage is detected, and set the detection signal supplied to the logic unit 14 to a high level. If either one of overcurrent and overvoltage is detected, it is determined that an abnormality has occurred, and the detection signal supplied to the logic unit 14 is set to a low level.

The logic unit 14 determines whether or not the output power supply is all normal based on the detection signals supplied from the detection units 13 ₁ , 13 ₂ ,..., 13 _n and switches the signal according to the determination result. To the unit 15. That is, the logic unit 14 performs normal logic when all of the detection signals supplied from the detection units 13 ₁ , 13 ₂ ,..., 13 _n are high-level signals supplied at normal times. Generate. In addition, any one of the detection signals supplied from each of the detection units 13 ₁ , 13 ₂ ,..., 13 _{n has} a logic that becomes abnormal when it is a low level signal supplied at the time of abnormality. Generate. Then, the logic unit 14 supplies a signal corresponding to the generated logic to the switching unit 15.

In order to obtain the same effect as that of the mask, the switching unit 15 outputs the path for transmitting the signal supplied from the logic unit 14 to the output unit 16 and the output of the DC-DC converter 12 _{n that} is last activated by the activation sequence control unit 18. Switching with voltage as a trigger. That is, the switching unit 15 determines a normal state or an abnormal state based on the switching signal supplied from the DC-DC converter 12 _n and the signal supplied from the logic unit 14 and outputs a signal corresponding to the determination result. To the unit 16.

When the power supply is activated, it is determined to be in a normal state until a switching signal from the normally activated DC-DC converter 12 _n is confirmed. That is, the switching unit 15 supplies a signal corresponding to the normal state to the output unit 16 until the last n-th power output is confirmed. After confirming the switching signal, if the signal supplied from the logic unit 14 corresponds to the normal state, it is determined as a normal state, and if it corresponds to the abnormality, it is determined as an abnormal state.

  The output unit 16 generates a control signal for controlling the switching element 11 based on the signal supplied from the switching unit 15, and supplies the generated control signal to the switching element 11 to control the opening / closing operation of the switching element 11. . That is, the output unit 16 controls the switching element 11 to be in a closed state if the signal supplied from the switching unit 15 corresponds to a normal state, and switches the switching element 11 if it corresponds to an abnormal state. The element 11 is controlled to be in an open state.

The activation sequence control unit 18 sets the activation start delay time and activation sequence of each of the DC-DC converters 12 ₁ , 12 ₂ ,..., 12 _n , and the DC-DC converters 12 ₁ , 12 ₂ ,. supplies a control signal based on each of the setting conditions for each 12 _n, DC-DC converter 12 _1, 12 _2, ..., and controls the respective activation of the 12 _n. Thereby, DC-DC converter 12 _1, 12 _2, ..., 12 _n is, DC-DC converter at a predetermined timing 12 _1, 12 _2, ..., starts in the order of 12 _n.

Note that the output power of the DC-DC converter 12 _n is used as a switching signal supplied to the switching unit 15. However, as shown by the broken arrow to the switching unit 15, the DC-DC converter 12 _n is activated at the start of activation. An activation control signal supplied from the sequence control unit 18 to the DC-DC converter 12 _n may be used as a switching signal.

Figure 2 shows an example of the configuration of the logic unit 14, switching unit 15 and the output unit 16 in the case of using the output power of the DC-DC converter 12 _n as a switching signal. The logic unit 14 is configured by an AND circuit 21. Detection signals are supplied from the detection units 13 ₁ , 13 ₂ ,..., 13 _n to the input side of the AND circuit 21. AND circuit 21, the detection unit 13 _1, 13 _2, ..., 13 if the detection signal is all high level supplied from each of _n, outputs a high level signal corresponding to the logic becomes normal, either If even one of them is at a low level, a low level signal corresponding to the logic that becomes abnormal is output. The output signal of the AND circuit 21 is supplied to the switching unit 15.

  The switching unit 15 includes two-stage inverters 22 and 23 and a totem pole type switch. Inverters 22 and 23 are Schmidt inverters. The Schmitt inverter has a hysteresis characteristic in which the voltage at which the input voltage rises and the input becomes high level is different from the voltage at which the input voltage drops and the input becomes low level.

  The totem pole type switch is configured such that the switching element 24 on the H side and the switching element 25 on the L side have a totem pole configuration. The switching elements 24 and 25 are constituted by bus switches. The bus switch is configured to control on / off of a connection between two input / output terminals based on an input to a control terminal. The bus switch has a characteristic that propagation delay time is extremely small and power consumption is low.

The output voltage of the DC-DC converter 12 _n is supplied to the input side of the inverter 22 as a switching signal. The first-stage inverter 22 prevents the logic from being inverted when the switching signal input to the switching unit 15 is near the threshold due to the hysteresis characteristic described above. The inverter 22 outputs a high level signal from the output side when the switching signal is at a low level, and outputs a low level signal when the switching signal is at a high level. The output signal of the inverter 22 is supplied to the control terminal of the switching element 24 and the input side of the inverter 23.

  The switching element 24 is turned on when a high level signal is supplied from the inverter 22 to the control terminal, and turned off when a low level signal is supplied.

  The second-stage inverter 23 is for ensuring that only one of the switching elements 24 and 25 is turned on. The inverter 23 outputs a low level signal from the output side when the signal supplied from the inverter 22 is high level, and outputs a high level signal when the signal is low level. The output signal of the inverter 23 is supplied to the control terminal of the switching element 25.

  The switching element 25 is turned on when a high level signal is supplied from the inverter 23 to the control terminal, and turned off when a low level signal is supplied.

A reference voltage V _R is supplied to one input / output terminal of the switching element 24 via a resistor R1. The output signal from the AND circuit 21 is supplied to one input / output terminal of the switching element 25. The other input / output terminals of the switching element 24 and the switching element 25 are connected to each other, and output signals from the switching elements 24 and 25 are supplied to the output unit 16.

  In the illustrated example, the masking time is when the switching element 24 is on and the switching element 25 is off. That is, in a state where the switching element 24 is on and the switching element 25 is off, a high level signal is supplied to the output unit 16 via the resistor R1 as a normal state. At this time, the output of the AND circuit 21 is not supplied to the output unit 16. That is, regardless of the output signal of the logic unit 14, the input of the output unit 16 is always at a high level, so that the mask is effective.

  When the switching element 24 is off and the switching element 25 is on, a high level signal corresponding to normality or a low level signal corresponding to abnormality supplied from the AND circuit 21 is supplied to the output unit 16. Is done. Since the output of the output unit 16 changes depending on the output signal of the logic unit 14, the mask becomes invalid.

The output unit 16 includes a voltage comparator 26. A signal supplied from the switching unit 15 is supplied to the plus input of the voltage comparator 26. A threshold voltage V _th1 from a known threshold voltage generation circuit is supplied to the negative input of the voltage comparator 26. The voltage comparator 26 compares the voltage supplied from the switching unit 15 with the threshold voltage V _th1, and outputs a high level signal when the voltage supplied from the switching unit 15 is higher than the threshold voltage V _th1. When the voltage supplied from the unit 15 is lower than the threshold voltage V _th1 , a low level signal is output.

  An output signal output from the output side of the voltage comparator 26 is supplied to the switching element 11 as a control signal for controlling the opening / closing operation of the switching element 11. The switching element 11 is closed when a high level signal is supplied from the voltage comparator 26, and is opened when a low level signal is supplied.

With the above configuration, the power supply protection circuit operates as follows. First, in a state where the power source is not activated, the output voltage of the DC-DC converter 12 _n is at a low level. Therefore, a low level switching signal is input to the switching unit 15. Thus, high level signals are sequentially output from the switching unit 15 and the output unit 16. The high-level signal output from the output unit 16 is supplied to the switching element 11 and the switching element 11 is closed.

When the power supply is started from this state, the DC-DC converters 12 ₁ , 12 ₂ ,..., 12 _n are turned on by the DC-DC converters 12 ₁ , 12 ₂ ,. Start in the order of 12 _n . When the DC-DC converter 12 _{n that} is activated last is activated, a high-level switching signal is supplied to the switching unit 15. As a result, the signal supplied from the logic unit 14 is output from the switching unit 15.

That is, when all the output power sources from the detection units 13 ₁ , 13 ₂ ,..., 13 _n are normal, high level signals are sequentially output from the switching unit 15 and the output unit 16. The high level signal output from the output unit 16 is supplied to the switching element 11 and the closed state of the switching element 11 is maintained.

When any one of the detection units 13 ₁ , 13 ₂ ,..., 13 _n becomes abnormal, low level signals are sequentially output from the switching unit 15 and the output unit 16. The low level signal output from the output unit 16 is supplied to the switching element 11 to switch the switching element 11 to the open state.

Thus, at the time of starting the power supply, the switching element 11 is closed until the switching signal is confirmed by the switching unit 15. As a result, even if the detection units 13 ₁ , 13 ₂ ,..., 13 _n detect output voltage overshoot or inrush current when starting the power supply, the detection result becomes invalid and the power protection circuit malfunctions when starting the power supply. Can be prevented.

  In addition, since the logic unit 14, the switching unit 15, and the output unit 16 are configured by a logic circuit, the accuracy of the mask time can be increased and the mask time can be shortened.

Further, since the mask time is automatically determined based on the switching signal, it is possible to take a countermeasure against malfunction at the time of starting the power supply without setting the mask time in advance. As a result, even _if the starting order of the DC-DC converters 12 ₁ , 12 ₂ ,..., 12 _n is changed, it is not necessary to change the constant of the mask part as in the case of setting the mask time using the CR integration circuit. Maintenance becomes easy.

FIG. 3 shows an example of the configuration of the logic unit 14, the switching unit 15, and the output unit 16 when the activation control signal from the activation sequence control unit 18 is used as a switching signal. When the activation control signal supplied from the activation sequence control unit 18 to the DC-DC converter 12 _n is used as the switching signal, a margin is provided for a period during which the detection result by the abnormality detection function is invalidated, and the switching element 24 described above is used. It is necessary to delay the timing of turning on the switching element 25 and turning on the switching element 25 until the output power of the DC-DC converter 12 _n is stabilized.

  Therefore, in the circuit configuration shown in FIG. 3, in the switching unit 15, a delay circuit 27 and a delay circuit 28 are provided between the inverter 22 and the switching element 24 and between the inverter 23 and the switching element 25, respectively. Other configurations are the same as those shown in FIG.

The delay circuits 27 and 28 are constituted by, for example, a well-known counter circuit. The delay circuit 27 supplies the signal input from the inverter 22 to the switching element 24 with a delay of a predetermined time or more. The delay circuit 28 delays the signal input from the inverter 23 by a predetermined time or more and supplies it to the switching element 25. As a result, at a timing delayed by a predetermined time or more from the timing at which the activation control signal is supplied from the activation sequence control unit 18 to the DC-DC converter 12 _n until the output power of the DC-DC converter 12 _n is stabilized, The switching element 24 can be turned off and the switching element 25 can be turned on.

As described above, the delay circuits 27 and 28 provide a margin for a period during which the detection result from the logic unit 14 output from the switching unit 15 is invalid, and the activation control signal for controlling the activation of the DC-DC converter 12 _n. by detect the start of the DC-DC converter 12 _n based on the same effect as when using the output supply voltage of the DC-DC converter 12 _n as a switching signal.

As shown in FIG. 4, delay circuits 27 and 28 for extending the period during which the detection result by the abnormality detection function is invalid may be provided regardless of the type of the switching signal. For example, even when the output voltage of the DC-DC converter 12 _n is used as the switching signal, the timing at which the switching elements 24 and 25 are switched can be adjusted by providing the delay circuits 27 and 28.

FIG. 5 shows an example of an operation sequence diagram for comparing the mask time of the power protection circuit according to the embodiment and the mask time of the power protection circuit according to the prior art using the CR integration circuit under the same conditions. In the figure, the horizontal axis represents time (t), and the vertical axis represents voltage (V). The input power supply voltage V _IN is a drive power supply voltage. Output power supply voltages V ₁ , V ₂ and V _n are output power supply voltages of the DC-DC converters 12 ₁ , 12 ₂ and 12 _n , respectively. The output power supply voltages of converters other than the DC-DC converters 12 ₁ , 12 ₂ , 12 _n are not shown.

The masking required period is a period until all of the output power supply voltages V ₁ , V ₂ ,..., V _n become stable power supply voltages. In this example, the masking period is required until the output power supply voltage V _n exceeds the threshold value. This threshold is a voltage at which the inverter 22 makes the input high level, that is, a voltage that makes the output low level.

Section a, the power supply indicates a start time of the input supply voltage V _IN and the reference voltage V _R from being activated. Section b, the section c, the startup delay time of the output power voltages V ₁ from the power source is started, the output power voltages V ₁ indicates the start time of the output power voltages V ₁ from being activated. Further, the interval d indicates the start delay time of the output power supply voltage V _n, in this example, DC-DC converter 12n from the time the output power voltages V ₁ reaches the threshold value delayed by interval d is activated Yes. The section g indicates the time from when the output power supply voltage V _n exceeds the threshold to when the switching element 11 is switched.

  The conventional masking setting time (min) is a theoretically shortest masking time set by assuming a residual charge generated when the input power supply is steeply turned on / off due to the charge / discharge characteristics of the capacitor constituting the CR integration circuit. . The conventional masking setting time (typ) is a masking time that takes into account errors due to the accuracy of the capacitors and resistors that make up the CR integration circuit, as the design value for the masking setting time (min) to reliably mask the required masking period. is there. For example, when the masking setting time (typ) is set to 24 [ms] as protection of a power supply having a masking period of 12 [ms], the masking setting time (min) is 15.6 [ms], which is about 35. Even if it becomes shorter, it will surely become longer than the required mask period. That is, in the power protection circuit according to the prior art, the mask time shown in the section e is necessary.

On the other hand, in the power supply protection circuit according to the embodiment, the mask time is set by a highly accurate logic circuit and is switched by a high-speed bus switch. In other words, the interval g can be minimized and an optimal mask time can be set for the required mask period. For example, when the activation control signal of the DC-DC converter 12 _n is used as the switching signal, the delay time of the delay circuits 27 and 28 is set to at least the time from the end of the section d to the start of the required mask period. That's fine.

  Thus, since the power protection circuit according to the embodiment has an improved mask time error, that is, accuracy, the mask time may be in the range indicated by the section f, and the stability of the circuit can be improved. Further, since the mask time is optimized, the function of the power protection circuit can be made more effective.

The present invention is not limited to the above-described embodiments of the present invention, and various modifications and applications are possible without departing from the spirit of the present invention. For example, in the above-described embodiment, the startup control order and the normal startup order of the DC-DC converters 12 ₁ , 12 ₂ ,..., 12 _n are the same, but they may be different. In this case, the output voltage of the converter that outputs the output power supply voltage at the last nth or the start control signal can be used as the switching signal.

  In addition, as long as masking is performed according to the same technical idea as that of the embodiment, the circuits constituting each unit are not limited to those described above. For example, although Schmitt inverters are used as the inverters 22 and 23 and bus switches are used as the switch elements 24 and 25, other known inverters and switch elements may be used as the inverters 22 and 23 and the switch elements 24 and 25, respectively. .

In addition, the plurality of DC-DC converters 12 ₁ , 12 ₂ ,..., 12 _{n according} to the above-described embodiment are provided with a plurality of types of output power supply voltages V ₁ , V ₂ ,. _It may be capable of outputting _n .

It is a figure which shows an example of a structure of the power supply protection circuit by one Embodiment of this invention. It is a figure which shows an example of the circuit structure of a logic part, a switching part, and an output part when an output voltage is made into a switching signal. It is a figure which shows an example of the circuit structure of a logic part, a switching part, and an output part when a starting control signal is made into a switching signal. It is a figure which shows an example of the circuit structure of a logic part, a switching part, and an output part when a delay circuit is provided irrespective of the kind of switching signal. It is an operation | movement sequence diagram for demonstrating the mask time in one Embodiment. It is a figure which shows an example of a structure of the conventional power supply protection circuit. It is a figure which shows an example of the circuit structure of the logic part of the conventional power supply protection circuit, an output part, and a mask part.

Explanation of symbols

11 ... switching elements _{12 1, 12 2, ...,} 12 n ··· DC-DC converter _{13 1, 13 2, ...,} 13 n ··· detector 14 ... logic 15 ... switching unit DESCRIPTION OF SYMBOLS 16 ... Output part 18 ... Starting sequence control part 21 ... AND circuit 22, 23 ... Inverter 24, 25 ... Switching element 26 ... Voltage comparator 27, 28 ... Delay circuit

Claims (7)

A switching element for opening and closing a supply path for supplying driving power to a plurality of DC-DC converters;
An abnormality detection unit for detecting an output abnormality of the plurality of DC-DC converters;
Until the activation of the DC-DC converter activated last is detected among the plurality of DC-DC converters, the detection result of the abnormality detection unit is invalidated, and the DC-DC converter activated last. After the activation is detected, the activation detection unit that validates the detection result of the abnormality detection unit,
When the detection result of the abnormality detection unit is invalidated by the activation detection unit, the switching element is closed, and when the detection result of the abnormality detection unit is validated by the activation detection unit, the abnormality is detected. A control unit that closes the switching element when the output abnormality is not detected by the detection unit, and that opens the switching element when the output abnormality is detected by the abnormality detection unit. Power supply protection circuit.   2. The power protection circuit according to claim 1, wherein the activation detection unit detects activation of the DC-DC converter activated last, based on an output voltage level of the DC-DC converter activated last. .   The power supply protection circuit according to claim 1, wherein the activation detection unit and the control unit are configured by a logic circuit.   The start detection unit includes a two-stage Schmitt inverter to which a switching signal corresponding to a start state of the DC-DC converter that is started last is input, and the two-stage Schmitt inverter that is switched according to the state of the switching signal. 2. The power supply protection circuit according to claim 1, wherein the power protection circuit comprises a totem pole type switch that switches between valid / invalid of the detection result of the abnormality detection unit based on each output of.   5. The power protection circuit according to claim 4, wherein the totem pole type switch is constituted by a bus switch.   The power supply protection circuit according to claim 1, wherein the activation detection unit includes a delay unit that extends a period during which the detection result of the abnormality detection unit is invalid. The activation detection unit has a margin in a period during which the detection result of the abnormality detection unit is invalidated by the delay unit, and the last detection unit controls the activation of the last activated DC-DC converter based on the activation control signal. 7. The power supply protection circuit according to claim 6, wherein activation of the DC-DC converter activated by the power supply is detected.

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