JP2007151128A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with variable power function. <P>SOLUTION: In embodiment, the semiconductor device has at least one circuit element which is set to generate output data. At least one control circuit is set so as to variably control the power of the output data, based on the feedback from a receiving side semiconductor device which receives the output data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a function of changing the power of an output signal.

  FIG. 1 shows a data output interface unit 100 of a conventional semiconductor memory device and a data input interface unit 200 of a memory control unit. As shown in the figure, the data output interface unit 100 receives data output from a memory cell array (not shown) of the memory device and converts the k-bit parallel data to the parallel-serial converter PSC; 12-1 to 12-n. The data output part 10 distributed to each of these is included. Each parallel-serial converter PSC; 12 converts the received parallel data into differential serial data do1, do1B to don, donB.

  The clock generator 14 generates clock signals P1-Pk to clock the k-bit data for the respective parallel-to-serial converter PSC; 12. The clock signals P1 to Pk may have different phases and may be synchronized in response to a clock signal applied from the memory control unit 200 and received from the outside. The parallel-serial converter 12 performs a parallel-serial conversion operation based on the received clock signal.

  The data output interface unit 100 includes a plurality of output drivers OD; 16-1 to 16-n. Each output driver OD; 16-1 to 16-n corresponds to one parallel-serial converter 12. In particular, each output driver OD; 16-1 to 16-n receives differential serial data and generates differential output signals D01, D01B to D0n, D0nB. The differential output signal is transmitted to the input data interface unit 200 through a signal transmission medium such as a bus.

  The control circuit CC; 18 outputs a control signal CON composed of m bits c1 to cm to the output drivers OD; 16-1 to 16-n. The driving capabilities of the output drivers OD; 16-1 to 16-n are set in response to the control signal CON. The control circuit 18 has a fuse structure for setting the respective bits c1 to cm of the control signal CON. By cutting each fuse in the fuse structure of the control signal 18, each bit c1 to cm is set to a fixed value. Since the control signal CON is fixed, the swing widths of the output signals D01 to D0n and the inverted output signals D01B to D0nB are also fixed. That is, the driving capabilities of the output drivers OD; 16-1 to 16-n are fixed. The respective values of the bits c1 to cm are set by setting the respective bits in the register structure of the control circuit CC; 18. Since the control signal CON is set regardless of the characteristics of the channel 300, the swing widths of the output signals D01B to D0nB and the inverted output signals D01B to D0nB are also set regardless of the channel characteristics. That is, the drive capability of the output drivers OD; 16-1 to 16-n is not related to the characteristics of the channel 300.

  In order to ensure a stable operation of the memory system including the data output interface 100, a fixed value of the control signal CON and a fixed driving capability of the output drivers OD; 16-1 to 16-n according to the fixed value Is set to a relatively high value. This helps to ensure fast speed operation, but is not desirable to reduce power consumption.

As shown in FIG. 1, the input data interface 200 includes input driver IDs 34-1 to 34-n, each corresponding to one of the output drivers OD; 16-1 to 16-n. Each of the input drivers 34 converts the received differential output signal into differential input data di1, di1B to din, dinB. Each of the plurality of serial / parallel converters SPC32-1 to 32-n converts the differential input data output from the input driver 34 into parallel data din1 to dinn of k bits. The data input unit 30 receives parallel data from the serial / parallel converter 32 and outputs an input data stream. Similar to the output data interface unit 100, the input data interface unit 200 includes a clock signal generator 36. The clock signal generator 36 generates k clock signals. The clock signals have different phases and can be synchronized with the internal clock signal of the memory control unit 200. The serial / parallel converter 32 performs an operation of converting serial to parallel based on the received clock signal.
US Pat. No. 5,936,896 JP-A-8-329685 Korean open patent 1997-012738 Korean registered patent 200,917

  An object of the present invention is to provide a semiconductor device capable of reducing power consumption by adjusting a swing of transmitted data to have a swing that can be transmitted without error.

  Another object of the present invention is to provide a memory system including a semiconductor device for achieving the object.

  In an embodiment of the semiconductor device according to the present invention, at least one or more circuit elements are configured to generate output data, and the at least one or more circuit elements are based on feedback from a receiving-side semiconductor device that receives the output data. Thus, the power of the output data can be variably controlled (for example, adaptively controlled).

  In one embodiment, the control circuit can be configured to periodically determine the power of the output data.

  For example, while determining the power of the output data, the control circuit decreases the power of the output data from the initial power value until an error signal indicating that there is an error in the received output data is received from the receiving semiconductor device. Configured for. The control circuit can be configured to determine the power of the output data prior to the power of the output data that produced the error signal.

  In one embodiment, the control circuit includes a first storage device, a second storage device, and a selector. The first storage device can be configured to store an initial control signal indicative of an initial power value and to change the stored control signal. The second storage device can be configured to store control signals previously stored in the first storage device. The selector selectively outputs a control signal stored in one of the first storage device and the second storage device as a power control signal. For example, the selector outputs the control signal stored in the first storage device until the error signal indicates that there is an error in the received output data, and thereafter, outputs the control signal to the second storage device. It can be configured to output the stored control signal.

  In other embodiments, the control circuit can be configured to perform an output power determination operation in response to an error signal indicating that there is an error in the received output data. For example, while determining the power of the output data, the control circuit is configured to increase the power of the output data from the initial power value until the error signal indicates that the received output data is error free. .

  In one embodiment, the control circuit may include a first storage device, a second storage device, and a selector. The first storage device is configured to store an initial control signal indicating an initial power value and to change the stored control signal. The second storage device is configured to store the control signal stored in the first storage device. The selector can selectively output the control signal stored in one of the first storage device and the second storage device as a power control signal based on the error signal. For example, in one embodiment, the selector outputs a control signal stored in the first storage device until the error signal indicates that there is no error in the received output data, and the control stored in the second storage device. Configured to output a signal.

  In yet another embodiment, the control circuit periodically performs the first output data power determination, and if the first output data power determination is not performed, an error signal indicates that there is an error in the received output data. A second output data power determination is configured in response to the signal.

  In yet another embodiment, the at least one parallel to serial converter PSC is configured as one first circuit element to convert parallel input data to serial input data. The at least one output driver is configured to generate output data based on the serial input signal as the second circuit element. The first control circuit is configured to variably control power (for example, adaptively control) based on feedback from the receiving-side semiconductor device, and the second control circuit is based on feedback from the receiving-side semiconductor device. It is configured to variably control the power of output data (for example, adaptively control).

  In another embodiment of the present invention, a system includes a data output interface circuit configured to generate output data, and data configured to receive data output from the data output circuit and generate feedback information. And an input interface circuit. The data output interface circuit is configured to variably control (eg, adaptively control) the power of the output data based on feedback information and at least one or more circuit elements configured to generate output data. And at least one control circuit.

  In a related embodiment, the input data interface circuit includes at least one error detector capable of detecting an error in output data from the data output interface circuit, and an error signal generator that generates feedback information based on the output from the error detector. It comprises.

  The present invention further relates to a variable power control method. One embodiment includes a generation step of generating output data, and a variable control step of variably controlling (for example, adaptively controlling) the power of the output data based on feedback from a receiving-side semiconductor device that receives the output data. Including.

  The semiconductor device of the present invention can reduce power consumption by adjusting a swing of transmitted data to have a swing that can be transmitted without error.

  The present invention relates to a data output interface unit and a data input interface unit connected thereto. The data output interface unit can be a data output interface unit of the memory device, and the data input interface unit can be a data input interface unit of the memory control unit. However, the data output interface unit and the data input interface unit of the present invention are not limited to such applications.

  FIG. 2 is a diagram illustrating a data output interface unit 100 'and a data input interface unit 200' according to an embodiment of the present invention. As shown in the figure, the data output interface unit 100 ′ receives data output from, for example, a memory cell array (not shown), and receives a plurality of parallel-serial converters PSC; 12-1 ′ to 12-n ′ and a plurality of data. The data output unit 10 distributes k-bit parallel data to each of the error detection code generators EDCG 20-1 to 20-n. Each of the error detection code generators 20-1 to 20-n is connected to one of the parallel-serial converters 12-1 'to 12-n', and the parallel-serial converters 12-1 'to 12-n' are data. An s bit error code is generated for k bits received from the output unit 10. Each of the parallel / serial converters 12-1 'to 12-n' converts the received parallel data bits and the code bits connected thereto into differential serial data do1 ', do1B' to don ', donB'.

  The clock generator 14 'generates k + s clock signals P1' to P '(k + s) for supplying k + s bit clocks to the parallel-serial converters 12-1' to 12-n '. The clock signals P <b> 1 ′ to P ′ (k + s) have different phases, and can be synchronized with the external reception clock signal transmitted from the memory control unit 200. The parallel-serial converters 12-1 'to 12-n' perform an operation of converting parallel data into serial based on the received clock signal.

  The data output interface unit 100 'includes a plurality of output drivers 16-1 to 16-n. Each output driver 16-1 to 16-n corresponds to one of the parallel-serial converters 12-1 'to 12-n'. More specifically, each output driver 16-1 to 16-n receives differential serial data and generates an associated differential output signal D01 ', D01B'-D0n', D0nB '. . The differential output data signal is transmitted to the input data interface 200 'through a signal transmission medium such as a bus.

  The control circuit 25 outputs a control signal CON of c1 to cm bits to the output drivers 16-1 to 16-n. The driving capabilities of the output drivers 16-1 to 16-n are set in response to the control signal CON. FIG. 3A is a diagram illustrating an embodiment of an output driver 16 according to the present invention. As illustrated, the resistor R1 is connected in series with the NMOS transistor N1 between the voltage supply line and the common node ND. The gate of the NMOS transistor N1 receives the differential serial data do ', and the drain of the NMOS transistor N1 is used to output an inverted differential data signal DOB'. The resistor R2 is connected in series with the NMOS transistor N2 between the voltage supply line and the common node ND. The gate of the NMOS transistor N2 receives the inverted differential serial data doB ', and the drain of the NMOS transistor N2 is used to output a differential output signal DO'.

  All of the m NMOS transistors N3-1 to N3-m are connected in parallel between the common node ND and the ground. Each of the NMOS transistors N3-1 to N3-m receives one of the bits c1 to cm constituting the control signal CON. If the control bit c has a logical value “high” or “1”, the respective NMOS transistors N3-1 to N3-m are turned on. On the other hand, if the control bit c is a logical value “low” or “0”, the respective NMOS transistors N3-1 to N3-m are turned off. Therefore, the control signal CON controls whether the NMOS transistors N3-1 to N3-m are turned on. By such a method, the control signal CON controls the driving capability of the output drivers 16-1 to 16-n. As more NMOS transistors N3-1 to N3-m are turned on, the drive capability of the output drivers 16-1 to 16-n increases. If the NMOS transistors N3-1 to N3-m have different sizes, they will provide different driving capabilities. With such an arrangement, it is possible to control the driving capability of the output drivers 16-1 to 16-n.

  During operation, if the differential serial data do 'is greater than the inverted differential serial data doB', the differential output signal DO 'has a greater voltage than the inverted differential output signal DOB'.

  FIG. 3B is a diagram showing still another embodiment of the output driver 16 according to the present invention. As illustrated, the resistor R1 'is connected in series with the NMOS transistor N1' between the common node ND 'and the ground. The gate of the NMOS transistor N1 'receives the differential serial data do', and the drain of the NMOS transistor N1 'is used to output an inverted differential data signal DOB'. The resistor R2 'is connected in series with the NMOS transistor N2' between the common node ND 'and the ground. The gate of the NMOS transistor N2 'receives the inverted differential serial data doB', and the drain of the NMOS transistor N2 'is used to output the inverted differential data signal DO'.

  All of the m PMOS transistors P1-1 to P1-m are connected in parallel between the voltage supply line and the common node ND '. Each of the PMOS transistors P1-1 to P1-m receives one of the c1 to cm bits constituting the control signal CON. If the control bit c has a logical value “high” or “1”, each PMOS transistor P1 is turned off. If the control bit c is a logical value “low” or “0”, each PMOS transistor P1 is turned on. Thus, the control signal CON controls whether the PMOS transistors P1-1 to P1-m are turned on. In this way, the control signal CON controls the driving capability of the output drivers 16-1 to 16-n. As more PMOS transistors P1-1 to P1-n are turned on, the driving capability of the output drivers 16-1 to 16-n increases. It can be understood that when the PMOS transistors P1-1 to P1-m have different sizes, different driving capabilities are provided. With such an arrangement, it is possible to control the driving capability of the output drivers 16-1 to 16-n.

  During operation, if the differential serial data do 'is greater than the inverted differential serial data doB', the differential output signal DO 'has a greater voltage than the inverted differential output signal DOB'.

  FIG. 3C is a diagram showing still another embodiment of the output driver according to the present invention. As illustrated, the resistor R1 ″ is connected in series with the PMOS transistor P2 between the common node ND ″ and the ground. The gate of the PMOS transistor P2 receives the differential serial data do ', and the drain of the PMOS transistor P2 is used to generate an inverted differential data signal DOB'. The resistor R2 ″ is connected in series with the PMOS transistor P3 between the common node ND ″ and the ground. The gate of the PMOS transistor P3 receives the inverted differential serial data doB ', and the drain of the PMOS transistor P3 is used to generate the differential output signal DO'.

  All of the m PMOS transistors P1-1 to P1-m are connected in parallel between the common node ND ″ and the voltage supply line. Each of the PMOS transistors P1-1 to P1-m has a control signal CON. When the control bit c is a logic “high” or “1”, each of the PMOS transistors P1-1 to P1-m is turned off. If the control bit c is a logical value “low” or “0”, each PMOS transistor P1 is turned on. Thus, the control signal CON controls whether the PMOS transistors P1-1 to P1-m are turned on. With such a method, the control signal CON controls the driving capability of the output driver 16. As more PMOS transistors P1-1 to P1-m are turned on, the driving capability of the output drivers 16-1 to 16-m increases. It can be understood that when the PMOS transistors P1-1 to P1-m have different sizes, different driving capabilities are provided. With such an arrangement, it is possible to control the driving capability of the output driver 16 even greater.

  During operation, if the differential serial data do 'is greater than the inverted differential serial data doB', the differential output signal DO 'has a greater voltage than the inverted differential output signal DOB'.

  Returning to the control circuit 25 shown in FIG. 2, as shown, the control circuit 25 generates a control signal CON based on the signal received from the input data interface unit 200 '. Therefore, before describing the control circuit 25 in detail, the input data interface unit 200 'will be described first.

  The input data interface unit 200 'includes input driver IDs 34-1 to 34-n, and each input driver 34-1 to 34-n corresponds to one of the output drivers 16-1 to 16-n. The input drivers 34-1 to 34-n convert the received differential output data signals into differential input data di1 ', di1B' to din ', dinB', respectively.

  FIG. 4A is a diagram illustrating an embodiment of one input driver 34 according to the present invention. As illustrated, the resistor R11 and the NMOS transistor N11 are connected in series between the power supply line and the common node ND2. The gate of the NMOS transistor N11 receives the output data signal DO 'from the output data interface 100'. The drain of the NMOS transistor N11 is used to generate serial input data di '. The resistor R21 and the NMOS transistor N21 are connected in series between the power supply line and the common node ND2. The gate of the NMOS transistor N21 receives the inverted output data signal DOB '. The drain of the NMOS transistor N21 is used to generate inverted serial input data diB '. Constant current source I3 is connected between common node ND2 and ground. During operation, if the differential output data DO 'is greater than the inverted differential output data DOB', the differential input data di 'has a greater voltage than the inverted differential input data diB'.

  FIG. 4B is a diagram showing still another embodiment of the input driver 34 according to the present invention. As illustrated, the resistor R11 'and the NMOS transistor N11' are connected in series between the common node ND2 'and the ground. The gate of the NMOS transistor N11 'receives the output data signal DO' from the output data interface unit 100 '. The drain of the NMOS transistor N11 'applies the output of the inverted serial input data diB'. The resistor R21 'and the NMOS transistor N21' are connected in series between the common node ND2 'and the ground. The gate of the NMOS transistor N21 'receives the inverted output data signal DOB'. The drain of the NMOS transistor N21 'applies the output of the serial input data di'. The constant current source I4 is connected between the common node ND2 'and the power supply line. During operation, if the differential output data DO 'is greater than the inverted differential output data DOB', the differential input data di 'has a greater voltage than the inverted differential input data diB'.

  FIG. 4C is a diagram showing still another embodiment of the input driver 34 according to the present invention. As illustrated, the resistor R11 ″ and the PMOS transistor P2 ′ are connected in series between the common node ND2 ″ and the ground. The gate of the PMOS transistor P2 'receives the output data signal DO' from the output data interface unit 100 '. The drain of the PMOS transistor P2 'is used to output inverted serial input data diB'. The resistor R21 ″ and the PMOS transistor P3 ′ are connected in series between the common node ND2 ″ and the ground. The gate of the PMOS transistor P3 'receives the inverted output data signal DOB'. The drain of the PMOS transistor P3 'is used to output serial input data di'. The constant current source I4 is connected between the common node ND2 ″ and the power supply line. During operation, if the differential output data DO ′ is larger than the inverted differential output data DOB ′, the differential input data di ′ has a larger voltage than the inverted differential input data diB ′.

  Returning to the input data interface unit 200 ′ shown in FIG. 2, each of the plurality of serial-parallel converters (SPC) 32-1 ′ to 32-n ′ is output from the other input drivers 34-1 to 34-n. The differential input data is converted into parallel data din1 to din of k bits and parallel data of k + s bits different from this. The data input unit 30 receives k-bit parallel data from the serial / parallel converter 32 and outputs an input data stream.

  Each of the plurality of error detectors ED38-1 to 38-n is connected to one of the series-parallel converters 32 and receives the k + s-bit output output from each of the series-parallel converters 32. The plurality of error detectors 38-1 to 38-n generate different error signals E1 to En, respectively. Each error signal E indicates whether or not the k-bit parallel data received by the data input unit 30 is an error. The error signal generator 40 receives the other error signals E1 to En and generates a collective error signal ER. For example, the error signal generator 40 performs a logical OR operation on the error signals E1 to En in order to generate the collective error signal ER.

  The collective error signal ER is supplied to the output driver 42 having the same structure as the output drivers 16-1 to 16-n. At this time, a fixed reference voltage is supplied as an input to the output driver 42 that is inverted from the collective error signal ER. The output driver 42 generates an error output signal ED and an inverted error output signal EDB, and outputs them to the output data interface unit 100 '. For example, such signals are transmitted over a suitable medium such as a bus.

  Similar to the output data interface unit 100 ', the input data interface unit 200' includes a clock generator 36 '. The clock generator 36 'generates a k + s bit clock signal. The clock signals have different phases and can be synchronized with an internal clock signal of the device including the input data interface unit 200 '. The serial / parallel converters 32-1 'to 32-n' perform a serial / parallel conversion operation based on the received clock signal.

  Returning to FIG. 2 again, the control circuit 25 and its operation will be described in more detail. As illustrated, the control circuit 25 includes an input driver 22 having the same structure as the input drivers 34-1 to 34-n. The input driver 22 receives the error output signal ED and the inverted error output signal EDB, and generates an error signal er and an inverted error signal erB.

  The enable and clock signal generator ENCC; 24 periodically generates the enable signal EN and the clock signal CCLK, and generates the enable signal EN and the clock signal CCLK based on the error signal er and the inverted error signal erB. Interrupt. The drive control signal generator DCSG 26 receives the enable signal EN and the clock signal CCLK, and generates a control signal CON based on them.

  FIG. 5 shows the enable and clock signal generator ENCC; 24 in detail. As shown, the enable and clock signal generator 24 includes an enable signal generator 24-1 that periodically generates an enable signal EN, and a clock signal generator 24-2. The enable signal generator 24-1 interrupts generation of the enable signal EN based on the error signal er and the inverted error signal erB. The clock signal generator 24-2 generates a clock signal CCLK in response to the enable signal EN. The operation of the enable and clock signal generator 24 will be described in more detail with respect to the waveforms shown in FIG. 7A after the drive control signal generator 26 is first described.

  FIG. 6 is a diagram showing an embodiment of the drive control signal generator 26 according to the present invention. As shown, the drive control signal generator 26 includes a first storage device 50 and a second storage device 52 connected to a selector 54. For example, in the embodiment, the first storage device 50 and the second storage device 52 are registers. However, the first storage device 50 and the second storage device 52 are not limited to registers. As shown in the figure, the first register 50 includes m D flip-flops DF10 to DF1m connected in cascade, and a ground voltage is applied to the data input of the first D flip-flop DF10. Each D flip-flop DF1 receives the clock signal CCLK at the clock input and the EN enable signal EN at the set input. Therefore, if the enable signal EN is a logical value “low” or “0” indicating that it is not enabled, the D flip-flops DF10 to DF1m of the first register 50 are set, and the D flip-flops DF10 to DF10 of the first register 50 are set. Each of DF1m stores a logical “high” or “1” value. The enable signal EN indicates that it is enabled when the logic value is “high” or “1”, and the D flip-flops DF10 to DF1m are not set. Therefore, the clocking of the D flip-flops DF10 to DF1m causes the logical value “low” or “0” to be transferred via the D flip-flops DF10 to DF1m. The outputs of the first to mth D flip-flops DF10 to DF1m-1 are supplied to the selector 54 as the first register input REG1. The outputs of the first to m-th D flip-flops DF10 to DF1m-1 correspond to the respective bits c of the control signal CON; c1 to cm.

  The second register 52 includes m D flip-flops DF21 to DF2m connected in cascade. The inputs of the D flip-flops DF21 to DF2m are connected to the outputs of the 2nd to (m + 1) th D flip-flops DF11 to DF1m, respectively. The D flip-flops DF21 to DF2m receive the clock signal CCLK at the clock input. The outputs of the D flip-flops DF21 to DF2m are supplied to the selector 54 as the second register input REG2. Each of the D flip-flops DF21 to DF2m corresponds to the bits c1 to cm of the control signal CON, respectively. In response to the clock signal CCLK, the first to m-th D flip-flops DF21 to DF2m store the values of the previous version of the first register input REG1. That is, the second register input REG2 is equal to the first register input REG1 from the previous pulse of the clock signal CCLK.

  The selector 54 selectively outputs one of the first register input REG1 and the second register input REG2 as the control signal CON. Further details will be described later with reference to FIGS. 7A and 7B, and the selector 54 is configured so that the enable signal EN is enabled when the enable signal EN is enabled (in this example, when the logic value is “high”). The first register input REG1 is output, and the second register input REG2 is output if the enable signal EN is not enabled (in this example, the logic value is “low”).

  Next, the operation of the control circuit 25 will be described in detail with reference to FIGS. 7A and 7B. FIG. 7A is a diagram illustrating waveforms generated by the control circuit 25 during operation. FIG. 7B is a diagram illustrating not only the first register input REG1 and the second register input REG2, but also the register input selected by the selector 54 as an operation example of the control circuit 25.

  Referring to FIGS. 7A and 7B, an example of the enable signal EN periodically enabled by the enable signal generator 24-1 is shown. The period in which the enable signal generator 24-1 enables the enable signal EN is determined by design choice. When the enable signal EN is “high” or “1” as a logical value (for example, enable in this embodiment), the clock signal generator 24-2 starts generating the clock signal CCLK. In response to the transition of the enable signal EN to the logical value “high”, the D flip-flops DF10 to DF1m of the first register 50 are not set to “1”. However, if the enable signal EN is a logic “low”, the first register inputs REG1 will all be set to “1”. When the enable signal EN is the logical value “high”, the selector 54 outputs the first register input REG1 as the control signal CON. FIG. 7B is a diagram illustrating the state of the first register input REG1 and the state of the register input output by the selector 54.

  Returning to FIG. 7A, the clock signal CCLK is generated in response to the enable signal EN transitioning to a logic high level. Each pulse of the clock signal CCLK causes the logic value “low” or “0” to be shifted in series with the first flip-flops DF10 to DF1m (in synchronization with its rising or falling edge). Each pulse of the clock signal CCLK causes the D flip-flops DF21 to DF2m to store the previous first register input REG1. As a result, the second register input REG2 output by the second register 52 is equal to the previous value of the first register input REG1. In this regard, the three clock pulses of the clock signal CCLK shown in FIG. 7A are clearly shown in FIG. 7B.

  The output of the selector 54 is a control signal CON. When the enable signal EN indicates enable, all the bits of the first register input REG1 are “1” in the control signal CON. Thus, for example, all of the NMOS transistors N3-1 to N3-m included in each of the output drivers 16-1 to 16-n in FIG. 3A are turned on, and the output power of the output drivers 16-1 to 16-n Is maximized. At this time, when the first register input signal REG1 transitions to a state including a logical value “0” in response to the clock signal CCLK, the NMOS transistors N3-1 to N3-m of the output drivers 16-1 to 16-n are turned off. Thus, the driving capabilities of the output drivers 16-1 to 16-n are reduced.

  In this embodiment, the NMOS transistors N3-1 to N3-m are turned off sequentially. However, the first register 50 can be configured such that the NMOS transistors N3-1 to N3-m are turned off by other procedures and / or other combinations. For example, the one or more NMOS transistors N3-1 to N3-m can be turned off at a time. Further, as described above, the NMOS transistors N3-1 to N3-m can have different sizes and driving capabilities. The structure in which the NMOS transistors N3-1 to N3-m are turned off is determined by different driving capabilities. Further, in response to the enable signal EN, the first register 50 can set the driving capability smaller than the maximum driving capability of the output drivers 16-1 to 16-n.

  The operation of the embodiment of the control circuit 25 has been described using the output driver structure shown in FIG. 3A. However, it can be understood that the present invention is not limited to this application. For example, the control circuit 25 can use the output driver structure shown in FIG. 3B. In this example, instead of setting the D flip-flops DF10-DF1m and shifting the logical value “low”, the D flip-flops DF10-DF1m are reset and shift the logical value “high”. This is because the drive transistor of the output driver in FIG. 3B is a PMOS transistor.

  Returning to FIG. 7B, in this example, after the third clock pulse of the clock signal CCLK, the input data interface 200 'generates an aggregate error signal ER indicating an error. As a result, the input driver 22 outputs an error signal er indicating an error. In response to the clock signal CCLK, the control signal CON decreases the driving capability of the output drivers 16-1 to 16-n. At some point, the output data is driven by the output drivers 16-1 to 16-n with low output power such that an error is detected by one of the error detectors E. As a result, a set error signal ER and an error signal er are generated.

  Upon receipt of the error signal er, the generation of the enable signal EN having a logic “high” is interrupted (eg, in this embodiment, the enable signal EN transitions to a logic “low”). As a result, the generation of the clock signal CCLK is interrupted, and the selector 54 outputs the second register input REG2 as the control signal CON. As a result, the output drivers 16-1 to 16-n are driven by the control signal CON value of the previous version that generates the error signal er. Such an operation is illustrated in FIG. 7B.

  By periodically repeating such operations, the driving capabilities of the output drivers 16-1 to 16-n are variably controlled so as to minimize power consumption while ensuring stable and fast operations.

  FIG. 8 is a diagram showing still another embodiment of the drive control signal generator 26 according to the present invention. In this embodiment, enable and drive signal generator 24 does not periodically generate enable signal EN. Instead, in this embodiment, the enable signal EN is generated in response to the received error signal er.

  As shown in the figure, in the embodiment of FIG. 8, the drive control signal generator 26 includes a first storage device 60 and a second storage device 62 connected to a selector 64. For example, in this embodiment, the first storage device 60 and the second storage device 62 are registers. However, the first storage device 60 and the second storage device 62 are not limited to registers. As shown in the figure, the first register 60 includes m D flip-flops DF31 to DF3m connected in cascade, and a power supply voltage (for example, a high voltage) is applied to the data input of the first D flip-flop DF31. ing. Each of the D flip-flops DF31 to DF3m receives a clock signal CCLK at a clock input and receives an enable signal EN at a reset input. Next, if the enable signal EN is a logical value “low” or “0” indicating that it is not enabled, the D flip-flops DF31 to DF3m of the first register 60 are reset and the D flip-flop DF31 of the first register 60 is reset. Each of ˜DF3m stores a logical value “low” or “0”. However, the D flip-flop DF3 is not reset when the enable signal EN is a logical value “high” or “1” indicating that it is enabled. When enabled, clocking of D flip-flops DF31-DF3m causes a logical “high” or “1” to be transferred through D flip-flops DF31-DF3m. The outputs of the first to mth D flip-flops DF31 to DF3m are supplied to the selector 54 by the first register input REG1 '. The outputs of the first to mth D flip-flops DF31 to DF3m correspond to the respective bits c of the control signals c1 to cm.

  The second register 62 includes m D flip-flops DF41 to DF4m connected in cascade. The data input of the first D flip-flop DF41 is connected to the power supply voltage. Data inputs to the second to mth D flip-flops DF42 to DF4m are connected to the outputs of the first to m-1st D flip-flops DF32 to DF3m-1. The D flip-flops DF41 to DF4m receive the clock signal CCLK at the clock input. The outputs of the D flip-flops DF41 to DF4m are supplied to the selector 64 as the second register input REG2 '. Each of the D flip-flops DF41 to DF4m corresponds to the bits c1 to cm of the control signal CON, respectively. In response to the clock signal CCLK, the first to m-th D flip-flops DF41 to DF4m store the same version value as the first register input REG1 '. More specifically, the second register input REG2 'is equal to the first register input REG1' when the enable signal EN is enabled.

  The selector 64 selectively outputs one of the first register input REG1 'and the second register input REG2' as a control signal CON. Further details will be described later with reference to FIG. 9A and FIG. 9B. The selector 64, if the enable signal is enabled (in this example, when the logic value is “high”), the first register input REG1. 'Is output, and the second register input REG2' is output if the enable signal is not enabled (in this example, when the logic value is "low").

  Next, the operation of the control circuit 25 will be described in detail with reference to FIGS. 9A and 9B. FIG. 9A is a diagram showing a waveform diagram generated by the control circuit 25 during operation. FIG. 9B is a diagram illustrating not only the first register input REG 1 ′ and the second register input REG 2 ′ but also register inputs selected by the selector 64 as an operation example of the control circuit 25.

  Referring to FIG. 9A, at some point during operation, the input data interface unit 200 'generates a collective error signal ER indicating an error. As a result, the input driver 22 generates an error signal er indicating an error. In response to the error signal er, the enable signal generator 24-1 generates an enable signal EN (in this embodiment, the enable signal transitions to a logic “high”). As a result, the clock signal generator 24-2 generates the clock signal CCLK.

  In response to the transition of the enable signal EN to the logical value “high”, the D flip-flops DF31 to DF3m of the register 60 are not reset to “0” any more, and each pulse of the clock signal CCLK is changed to the D flip-flop. DF31 to DF3m shift the logic value “high” or “1” in series. Also, each of the pulses of the clock signal CCLK causes the D flip-flops DF41 to DF4m to store the first register input REG1 '. As a result, the second register input REG2 'output by the second register 62 is equal to the first register input REG1'. In the meantime, the three clock pulses of the clock signal CCLK shown in FIG. 9A are more clearly shown in FIG. 9B.

  When the enable signal EN is enabled, the selector 64 outputs the first register input REG1 '. The output of the selector 64 is a control signal CON. When the enable signal EN is enabled for the first time, the control signal CON is in a state where all the bits of the first register input REG1 'are "0". For example, all the NMOS transistors N3 included in each of the output drivers 16-1 to 16-n in FIG. 3A are turned off, and the output power of the output driver 16 is minimized. At this time, when the first register input REG1 ′ changes to a state including the logical value “high” in response to the clock signal CCLK, the NMOS transistors N3-1 to N3-m of the output drivers 16-1 to 16-n When turned on, the driving capability of the output driver 16 increases.

  In this embodiment, the NMOS transistors N3-1 to N3-m are sequentially turned on. However, the first register 60 can be configured such that the NMOS transistors N3-1 to N3-m are turned on by other procedures and / or other combinations. For example, one or more of the NMOS transistors N3-1 to N3-m can be turned on at a time. Further, as described above, the NMOS transistors N3-1 to N3-m can have different sizes and different driving capabilities. The structure in which the NMOS transistors N3-1 to N3-m are turned on is determined by different driving capabilities. In response to the enable signal EN, the first register 60 sets the driving capability to be larger than the minimum driving capability of the output drivers 16-1 to 16-n.

  The operation of the embodiment according to the present invention in the control circuit 25 has been described using the output driver structure shown in FIG. 3A. However, it will be understood that the present invention is not limited by this application alone. For example, the control circuit 25 can use the output driver structure shown in FIG. 3B. In this example, instead of resetting the D flip-flops DF10 to DF1m and shifting the logical value “high”, the D flip-flops DF10 to DF1m are set and shift the logical value “low”. This is because the driving transistor having the output driver structure in FIG. 3B is a PMOS transistor.

  Returning to FIG. 9B, in this example, after the third clock pulse of the clock signal CLK, the input data interface unit 200 'does not generate the collective error signal ER indicating an error. As a result, the input driver 22 outputs an error signal er indicating an error. In response to the clock signal CCLK, the control signal CON increases the driving capability of the output drivers 16-1 to 16-n. At some point, the output data is driven by the output drivers 16-1 to 16-n with high output power such that no error is detected by one of the error detectors 38-1 to 38-n. As a result, the collective error signal ER and the error signal er are generated in a state where no error is indicated.

  When the error signal er not indicating an error is received, the generation of the enable signal EN having the logical value “high” is interrupted (in this embodiment, the transition is made to the logical value “low”). As a result, the generation of the clock signal CCLK is interrupted, and the selector 64 outputs the second register input REG2 'as the control signal CON. As a result, the output drivers 16-1 to 16-n are driven by the value of the version of the control signal CON that generates the error signal er indicating no error. Such an operation is illustrated in FIG. 9B.

  By performing such a process in response to an error, the driving capabilities of the output drivers 16-1 to 16-n are variably controlled so as to minimize power consumption while ensuring stable and fast operation.

  FIG. 10 is a diagram showing still another embodiment of the drive control signal generator DCSG in FIG. 2 according to the present invention. In this embodiment, the drive control signal generator DCSG includes the drive control signal generator DCSG of FIG. 6 and the drive control signal generator DCSG of FIG. Each output of the drive control signal generator DCSG is connected to the selector 300. The selector 300 receives the enable signal EN generated by the enable signal generator 310. For example, when such an enable signal indicates an enable state, for example, when the logical value is “high”, the selector 300 outputs the control signal CON from the drive control signal generator DCSG of FIG. 6. When the enable signal EN does not indicate an enable state, for example, when the enable signal EN is a logical value “low”, the selector 300 outputs the control signal CON from the drive control signal generator DCSG of FIG.

  The enable signal generator 310 periodically generates an enable signal. For example, in one embodiment, enable signal generator 310 generates an enable signal that is synchronized with the enable signal generated by enable signal generator 24-1 of FIG. Alternatively, the enable signal generated by the enable signal generator 310 is used by the enable signal generator 24-1 of FIG. 5 to start generating the enable signal. However, unlike the enable signal generated by the enable signal generator 24-1 of FIG. 5, the enable signal generated by the enable signal generator 310 is received by the enable signal generator 24-1 of FIG. (Same) After a certain period in which the error signal er is received, a transition is made from the enabled state to the non-enabled state. Thereby, when the drive control signal generator DCSG of FIG. 6 switches from outputting the first register input REG1 to outputting the second register input REG2, it gives a time during which the state that is not an error can be stabilized. .

  When the selector 300 switches to outputting the control signal from the drive control signal generator of FIG. 8 by such an operation, the error signal er indicates a state that is not an error. As described above, the enable signal generator 24-1 in FIG. 5 is not erroneously switched to the operation in which the drive control signal generator DCSG in FIG. 6 enables the operation.

  This embodiment according to the present invention provides the advantages of both the embodiment of FIGS. The drive control signal generator DCSG of FIG. 6 and the drive control signal generator DCSG of FIG. 8 are commonly connected to circuits such as the input driver 22 and the ENCC 24. Therefore, such a commonly connected circuit can provide a common signal to the drive control signal generator DCSG of FIG. 6 and the drive control signal generator DCSG of FIG.

  FIG. 11 is a diagram illustrating a data output interface unit and a data input interface unit according to still another embodiment of the present invention. The embodiment of FIG. 11 is the same as the embodiment of FIG. 2 except that it further comprises a voltage control signal generator VCSG; 70 and a voltage generator 72. Therefore, only the structure and operation of the additional elements will be described here.

  The voltage control signal generator 70 has the same structure and operation as the drive control signal generator 26, and receives the same input from the clock signal generator 24 as the input received by the drive control signal generator 26. Thereby, the voltage control signal generator 70 generates the voltage control signal VCON in the same way that the drive control signal generator 26 generates the control signal CON according to the embodiment described above.

  The voltage generator 72 receives the voltage control signal VCON and supplies a power supply voltage to the parallel-serial converters 12-1 'to 12-n' based on the voltage control signal VCON. This provides the same power control merit to the output drivers 16-1 to 16-n to the parallel-serial converters 12-1 'to 12-n' as well.

  FIG. 12A is a diagram illustrating one embodiment of a voltage generator 72 according to the present invention. As shown, the resistor R3 is connected to the power supply voltage EVDD. The plurality of resistors R41 to R4m are connected in series to the resistor R3. Each of the plurality of NMOS transistors N4-1 to N4-m is connected in parallel with one of the plurality of resistors R41 to R4m. Each of the gates of the plurality of NMOS transistors N4-1 to N4-m receives one value of bits vc1B to vcmB obtained by inverting the bits vc1 to vcm of the voltage control signal VCON. As illustrated, the inverter INV inverts the voltage control signal VCON (vc1 to vcm) applied to the NMOS transistor N4.

  A node between the resistor R3 and the resistor R41 is connected to the inverting input of the comparator COM. The output of the comparator COM is connected to the gate of the PMOS transistor PD. The PMOS transistor PD has a source connected to the power supply voltage EVDD, and the drain is connected to the non-inverting input of the comparator COM. The drain of the PMOS transistor PD also functions as the output of the voltage generator 72.

  With this operation, the voltage control signal VCON controls the number of NMOS transistors N4-1 to N4-m that are turned on, thereby controlling the voltage input to the inverting input of the comparator COM. For example, the number of NMOS transistors N4 that are turned on decreases as the number of bits having a logical “high” level in the voltage control signal VCON increases. Therefore, the voltage input to the inverting input of the comparator COM is kept “high”. As a result, the comparator COM generates an output signal for turning on the PMOS transistor PD, and the output of the voltage generator 72 becomes the “high” level. The more NMOS transistors N4-1 to N4-m that are turned off, the lower the voltage applied to the comparator COM. Thereby, the output voltage of the voltage generator 72 decreases.

  FIG. 12B is a diagram showing still another embodiment of the voltage generator 72 according to the present invention. In this embodiment, the NMOS transistors N4-1 to N4-m in FIG. 12A are replaced with PMOS transistors P4-1 to P4-m. By using the PMOS transistors P4-1 to P4-m, the inverter INV of FIG. 12A is eliminated. However, the operation of the voltage generator 72 described in FIG. 12B is the same as that of the embodiment of FIG. 12A.

  FIG. 13 is a diagram illustrating a data output interface unit and a data input interface unit according to another embodiment of the present invention. The embodiment of FIG. 13 includes an output data interface unit 100 ″ in which the first device is connected to the input data interface unit 200 ″ of the second device, and the second device is connected to the input data interface unit 200 ″ of the first device. 11 is the same as the embodiment of FIG. 11 except that the output data interface unit 100 ″ is connected. In this embodiment, the device is not limited to including one of an input data interface unit and an output data interface unit. That is, a device (for example, the first device or the second device described above) may include one or more input data interface units and / or output data interface units.

  In the embodiment of FIG. 13, the data input interface unit and the data output interface unit of FIG. 11 are used. Instead, the data input interface unit and the data output interface unit of FIG. 2 are used. Can also be done.

  It is clear that the present invention described above can be implemented in various ways by various other methods. For example, in the embodiment in which the power of the circuit elements such as the output driver and the parallel-serial converter is variably controlled, the power control method of the present invention is not limited by the method of realizing such circuit elements. Instead, other circuit elements such as multiplexers can be applied to the method. Such changes are not considered to depart from the spirit of the invention. All such modifications are within the scope of the invention.

It is a figure which shows the data output interface part of the conventional semiconductor memory device, and the data input interface part of a memory control part. FIG. 3 is a diagram illustrating a data output interface unit and a data input interface unit according to an embodiment of the present invention. FIG. 3 shows an embodiment of the output driver of FIG. 2 according to the present invention. FIG. 3 shows an embodiment of the output driver of FIG. 2 according to the present invention. FIG. 3 shows an embodiment of the output driver of FIG. 2 according to the present invention. FIG. 3 shows an embodiment of the input driver of FIG. 2 according to the present invention. FIG. 3 shows an embodiment of the input driver of FIG. 2 according to the present invention. FIG. 3 shows an embodiment of the input driver of FIG. 2 according to the present invention. FIG. 3 illustrates the embodiment of the enable and clock signal generator of FIG. 2 according to the present invention. FIG. 3 is a diagram illustrating an embodiment of the drive control signal generator DCSG of FIG. 2 according to the present invention. FIG. 7 is a diagram illustrating waveforms generated by a control circuit including the drive control signal generator DCSG of FIG. 6 during operation. FIG. 7B illustrates not only the first register input REG1 and the second register input REG2 but also the register input selected by the selector during the operation of the embodiment of the control circuit shown in FIG. 7A. FIG. 6 is a diagram showing still another embodiment of the drive control signal generator DCSG in FIG. 2 according to the present invention. FIG. 9 is a diagram illustrating waveforms generated by a control circuit including the drive control signal generator DCSG of FIG. 8 during the operation of the embodiment. FIG. 9B illustrates the register inputs selected by the selector 54 as well as the first register input REG1 ′ and the second register input REG2 ′ during operation of the embodiment of the control signal 25 shown in FIG. 9A. FIG. 6 is a diagram showing still another embodiment of the drive control signal generator DCSG in FIG. 2 according to the present invention. FIG. 6 is a diagram illustrating a data output interface unit and a data input interface unit according to still another embodiment of the present invention. FIG. 12 illustrates an embodiment of the voltage generator of FIG. 11 according to the present invention. FIG. 12 illustrates an embodiment of the voltage generator of FIG. 11 according to the present invention. FIG. 6 is a diagram illustrating a data output interface unit and a data input interface unit according to still another embodiment of the present invention.

Explanation of symbols

10 Data Output Units 12-1 ′ to 12-n ′ Parallel to Serial Converter PSC
14 'clock generator 16-1 to 16-n output driver 20-1 to 20-n error detection code generator EDCG
25 control circuit 100 'data output interface unit 200' data input interface unit do1 ', do1B' to don ', donB' differential serial data D01 ', D01B' to D0n ', D0nB' differential output signal

Claims (48)

At least one circuit element for generating output data;
At least one control circuit that variably controls the power of output data generated by the circuit element based on feedback from a receiving-side semiconductor device that receives the output data;
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the control circuit periodically determines the power of the output data and controls the power of the output data based on the determined power. While determining the power of the output data, the control circuit decreases the power of the output data from an initial power value until an error signal indicating an error of the received output data is received from the receiving-side semiconductor device, 3. The semiconductor device according to claim 2, wherein the power of the output data is the power of the output data before the power of the output data that generated the error signal. The semiconductor device according to claim 3, wherein the control circuit performs control so as to decrease the power of the output data step by step. 4. The control circuit according to claim 3, wherein the control circuit generates a power control signal indicating power of the output data, and the circuit element generates the output data having power indicated by the power control signal. Semiconductor device. The control circuit includes:
A first storage device for storing an initial control signal indicating an initial power value and changing the stored control signal;
A second storage device for storing the control signal previously stored by the first storage device;
A selector that selectively outputs the control signal stored by one of the first storage device and the second storage device as the power control signal;
The semiconductor device according to claim 5, comprising:   The selector outputs the control signal stored in the first storage device until the error signal indicates that there is an error in the received output data, and then stored in the second storage device. 7. The semiconductor device according to claim 6, wherein the control signal is output. The control circuit ends power control of the periodic output data after the error signal indicates that there is an error in the output data, and the selector performs the second control until power control of the next output data. 8. The semiconductor device according to claim 7, wherein the control signal stored in the storage device is output, and then the control signal stored in the first storage device is output. 8. The semiconductor device according to claim 7, wherein the first storage device changes the stored control signal until the error signal indicates that there is an error in the received output data. The first storage device includes a first register that shifts a logical value and changes the control signal represented by the stored logical value;
The semiconductor device according to claim 6, wherein the second storage device includes a second register that stores a logical value stored in advance by the first storage device. The selector outputs the control signal stored in the first register until the error signal indicates that the received output data has an error, and then stores the control signal stored in the second register. 11. The semiconductor device according to claim 10, wherein a control signal is output. The circuit element includes a plurality of power supply elements,
The power supply device according to claim 11, wherein each of the plurality of power supply elements selectively supplies power to generate the output data based on a logical state of a logical value of each of the power control signals. Semiconductor device. The control circuit includes an enable signal generation circuit that periodically generates an enable signal so that power of the output data can be determined.
The semiconductor device according to claim 11, wherein the first register stores the initial power value in response to the enable signal. The control circuit includes a clock signal generation circuit that generates a clock signal in response to the enable signal,
The first register changes a stored logic value in response to the clock signal;
The semiconductor device according to claim 13, wherein the second register stores a logical value stored in the first register in response to the clock signal. The enable signal generation circuit generates the enable signal so that the power of the output data can be determined until the error signal is received,
The selector outputs the control signal stored in the first register while the enable signal allows the power determination of the output data, and the enable signal disables the power determination of the output data. 14. The semiconductor device according to claim 13, wherein the control signal stored in the second register is output during the period. The semiconductor device according to claim 1, wherein the control circuit performs power determination of output data in response to an error signal indicating that the received output data has an error. The control circuit increases the power of the output data from the initial power value until the error signal does not indicate that the output data has an error while determining the power of the output data. A semiconductor device according to 1. The semiconductor device according to claim 17, wherein the control circuit increases the power of the output data stepwise. The control circuit generates a power control signal indicating the power of the output data;
The semiconductor device according to claim 17, wherein the circuit element generates output data having power indicated by the power control signal. The control circuit stores an initial control signal indicating the initial power value and changes the stored control signal for a predetermined time;
A second storage device for storing the control signal stored in the first storage device;
A selector that selectively outputs the control signal stored in one of the first storage device and the second storage device as the power control signal based on the error signal;
The semiconductor device according to claim 19, further comprising: The selector outputs a control signal stored in the first storage device until the error signal indicates that the received output data has no error, and the control signal stored in the second storage device 21. The semiconductor device according to claim 20, wherein: The semiconductor device according to claim 21, wherein the control circuit ends power determination of the output data when the error signal indicates that the received output data has no error. The semiconductor device of claim 21, wherein the first storage device changes the stored control signal until the error signal indicates that the received output data has an error. 22. The semiconductor device according to claim 21, wherein the first storage device resets the initial control signal to store when the error signal indicates that the received output data has no error. . The first storage device includes a first register that changes a stored logic value so that a control signal expressed by the stored logic value changes.
21. The semiconductor device according to claim 20, wherein the second storage device includes a second register that stores the logical value stored by the first register. The selector outputs the control signal stored in the first register until the error signal indicates that there is no error in the received output data, and the control signal stored in the second register 26. The semiconductor device according to claim 25, wherein: The circuit element includes a plurality of power supply elements,
27. Each of the plurality of power supply elements selectively supplies power to generate the output data based on a logic state of a respective logic value in a power control signal. Semiconductor device. The control circuit includes an enable signal generating circuit that generates an enable signal to enable power determination of the output data when the error signal indicates that the received output data has an error;
27. The semiconductor device according to claim 26, wherein the first register stores the initial power value in response to the enable signal. The control circuit includes a clock generation circuit that generates a clock signal in response to the enable signal,
The first register shifts a stored logic value in response to the clock signal;
29. The semiconductor device according to claim 28, wherein the second register stores a logical value stored in the first register in response to the clock signal. The enable signal generating circuit generates the enable signal to enable power setting of the output data until the error signal indicates that the received output data is error free;
The selector outputs the control signal stored in the first register while the enable signal enables output data power determination, and the enable signal disables output data power determination. 29. The semiconductor device according to claim 28, wherein the control signal stored in the second register is output. The control circuit periodically performs the first output data power determination, and if the first output data power determination is not performed, the control circuit performs a second response in response to an error signal indicating that the received output data has an error. 2. The semiconductor device according to claim 1, wherein output data power is determined. The control circuit reduces the power of the output data from a first initial power value until the error signal indicates that there is an error in the received output data while making the first output data power determination. 32. The semiconductor device according to claim 31, wherein the power of the output data is the power of the output data before the power of the output data that generated the error signal. The control circuit increases the power of the output data from the second initial power value until the error signal indicates that there is no error in the received output data while performing the second output data power determination. A semiconductor device according to claim 32. The control circuit includes:
A first auxiliary control circuit for determining the first output data power;
A second auxiliary control circuit for determining the second output data power;
If the output of the first auxiliary control circuit is selected while the first output data power determination is periodic enable, and the first output data power determination is not periodic enable, the second auxiliary control circuit A selector to select the output;
The semiconductor device according to claim 33, further comprising: 35. The semiconductor device according to claim 34, wherein the selector receives a periodic enable signal instructing to select an output of the first auxiliary control circuit. The control circuit increases the power of the output data from the second initial power value until the error signal indicates that there is no error in the received output data while making the second output data power determination. 32. The semiconductor device according to claim 31, wherein: The semiconductor device according to claim 1, wherein the circuit element is an output driver. The semiconductor device according to claim 1, wherein the circuit element is a parallel-serial converter. The semiconductor device includes:
At least one parallel-serial converter for converting input parallel data to serial as a first circuit element;
At least one output driver for generating the output data based on the input data as a second circuit element;
A first control circuit that variably controls power based on feedback from a receiving-side semiconductor device;
A second control circuit that variably controls the power of the output data based on feedback from a receiving-side semiconductor device;
The semiconductor device according to claim 1, further comprising: 2. The semiconductor device according to claim 1, wherein the circuit element and the control circuit form part of a data output interface circuit of a memory device. A data output interface circuit for generating the output data, comprising: at least one circuit element for generating output data; and at least one control circuit for variably controlling the power of the output data based on feedback information;
A data input interface circuit that receives output data from the data output interface circuit and generates the feedback information;
The system characterized by comprising. 42. The system of claim 41, wherein the data input interface circuit includes at least one error detector that detects an error in the output data from the data output interface circuit. 43. The system of claim 42, wherein the data input interface circuit includes an error signal generator that generates the feedback information based on an output from the error detector. A memory device including the data output interface circuit;
A memory controller including the data input interface circuit;
43. The system of claim 42, further comprising: A memory controller including the data output interface circuit;
A memory device including the data input interface circuit;
43. The system of claim 42, further comprising: A generation step for generating output data;
A variable control step of variably controlling the power of the output data based on feedback from a receiving-side semiconductor device that receives the output data;
A method for variable control of power, comprising: The method according to claim 46, wherein in the variable control step, the power is variably controlled periodically. The method according to claim 46, wherein, in the variable control step, power is variably controlled in response to an error signal received from the receiving-side semiconductor device.

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