JP2007149901A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of measuring the displacement of an opening in a photoresist film with respect to an opening in an element isolation film. <P>SOLUTION: In this manufacturing method of the semiconductor device, the element isolation film 2 having the openings 2b, 2c is formed on a semiconductor substrate 1 of a first conductivity type. Then, a photosensitive film is formed on the semiconductor substrate 1 located in the openings 2b, 2c and on the element isolation film 2. This photosensitive film is exposed using a reticle and then is developed to form a mask film 51 having a mask opening 51b including part on the opening 2b, and the periphery thereof is formed on the element isolation film 2. Then, an impurity region 7b of a second conductivity type is formed in the semiconductor substrate 1 located in the opening 2b by introducing the impurity of the second conductivity type using the mask film 51 as a mask, and further a silicide film 8b is formed on the surface of the semiconductor substrate 1 located in the opening 2b, and the conductivity between the semiconductor substrate 2 located in the opening 2c and the silicide film 8b is measured. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device. In particular, the present invention relates to a method for manufacturing a semiconductor device and a semiconductor device capable of measuring a deviation amount of an opening of a photoresist film with respect to an opening of an element isolation film.

  7A and 7B are cross-sectional views for explaining a conventional method for manufacturing a semiconductor device. First, as shown in FIG. 7A, an element isolation film 102 is formed on a first conductivity type silicon substrate 101. The element isolation film 102 has an opening 102a. Next, a gate insulating film 103, a gate electrode 104, a second conductivity type low-concentration impurity region 106, and a sidewall 105 are formed in the opening 102a.

  Next, a photoresist film 120 is applied in the opening 102 a and on the element isolation film 102. Next, the photoresist film 120 is exposed using a reticle and then developed. As a result, an opening 120a is formed in the photoresist film 120 that includes the opening 102a and the periphery thereof inside. The reason why the opening 120a is also formed around the opening 102a is to absorb the positional deviation of the opening 120a with respect to the opening 102a.

  Next, a second conductivity type impurity is implanted into the silicon substrate 1 using the photoresist film 120 and the element isolation film 102 as a mask. As a result, a second conductivity type impurity region 107 to be the source and drain of the transistor is formed in the silicon substrate 101 located in the opening 102a.

  Thereafter, as shown in FIG. 7B, the photoresist film 120 is removed. Next, a metal film (eg, a titanium film: not shown) is formed over the entire surface including the impurity region 107 and the gate electrode 104, and heat treatment is performed. Thereby, a silicide film 108 a is formed on each surface of the two impurity regions 107, and a silicide film 108 b is formed on the surface of the gate electrode 104. Thereafter, the non-silicided metal film is removed.

  Thereafter, an interlayer insulating film 109 is formed. Further, a tungsten plug 110 located on the silicide film 108 a is embedded in the interlayer insulating film 109, and an Al alloy wiring 111 is formed on the interlayer insulating film 109. The Al alloy wiring 111 is connected to the tungsten plug 110.

  FIG. 8A is a cross-sectional view for explaining a case where the position of the opening 120a with respect to the opening 102a is deviated from the design position in the method for manufacturing the semiconductor device shown in FIG. In the example of this figure, a part of the photoresist film 120 is located in the opening 102a. When the second conductivity type impurity is implanted in this state, a region 101b in which no impurity is implanted is formed in the silicon substrate 101 located in the opening 102a.

  After that, when the silicide film 108a is formed as shown in FIG. 8B, the region 101b is electrically connected to the tungsten plug 110 and the Al alloy wiring 111 through the silicide film 108a. In this case, power applied to the Al alloy wiring 111 leaks to the main body of the silicon substrate 101 through the region 101b.

For this reason, it is necessary to prevent the position of the opening 120a with respect to the opening 102a from deviating from the design position. Conventionally, the occurrence of deviation has been suppressed by improving the positional accuracy of the reticle using alignment marks (see, for example, Patent Document 1).
JP 2001-251007 A (second paragraph)

  As described above, conventionally, the occurrence of misalignment is suppressed by using the alignment mark to improve the positional accuracy of the reticle. However, even when the positional accuracy of the reticle is high, the position of the opening of the photoresist film may deviate from the opening of the element isolation film. One of the causes is that the position of the opening of the element isolation film deviates from the design position.

  For this reason, it is necessary to actually measure the shift amount of the opening of the photoresist film with respect to the opening of the element isolation film, rather than simply aligning the reticle. However, conventionally, it has been difficult to measure the shift amount of the opening of the photoresist film with respect to the opening of the element isolation film.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device capable of measuring the amount of shift of the opening of the photoresist film with respect to the opening of the element isolation film. It is to provide.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film having a first opening and a second opening on a first conductivity type semiconductor substrate,
Forming a photosensitive film on the semiconductor substrate located in the first and second openings and on the element isolation film;
A step of forming a mask film having a mask opening including the first opening and the periphery thereof on the element isolation film by exposing the photosensitive film using a reticle and then developing the photosensitive film. When,
Forming a first second conductivity type impurity region in the semiconductor substrate located in the first opening by introducing a second conductivity type impurity using the mask film as a mask;
Forming a first silicide film on a surface of the semiconductor substrate located in the first opening;
Measuring conductivity between the semiconductor substrate located in the second opening and the first silicide film.

  In this method of manufacturing a semiconductor device, when the amount of displacement of the mask opening with respect to the first opening is smaller than the margin of the mask opening with respect to the first opening, the first silicide film is The semiconductor substrate located in the second opening is not electrically connected.

However, when the amount of positional deviation described above is larger than the amount of margin described above, a part of the semiconductor substrate located in the first opening is covered with the mask film. Therefore, a region where the second conductivity type impurity is not introduced is formed in part in the semiconductor substrate located in the first opening.
In this case, the first silicide film is electrically connected to the semiconductor substrate located in the second opening through the region into which the second conductivity type impurity is not introduced and the semiconductor body.

  Therefore, by measuring the continuity between the semiconductor substrate located in the second opening and the first silicide film, the amount of displacement of the mask opening with respect to the first opening can be reduced. It is possible to measure whether or not it is smaller than the margin amount of the mask opening with respect to the first opening.

  When the semiconductor substrate includes a plurality of regions in which semiconductor chips are formed and a dicing region that separates the plurality of regions in which the semiconductor chips are formed from each other, the first opening and the second opening The part is preferably located in the dicing region.

In the step of forming the element isolation film, a chip opening located in a region where the semiconductor chip is formed is formed, and in the step of forming the mask film, the mask film is formed on the chip opening and In the step of forming a chip mask opening located around the periphery and forming the first second conductivity type impurity region, a second second conductivity type impurity is formed in the semiconductor substrate located in the chip opening. In the step of forming a region and forming the first silicide film, a second silicide film may be formed on the surface of the semiconductor substrate located in the chip opening.
In this case, it can be determined whether or not the amount of positional deviation of the chip mask opening with respect to the chip opening is smaller than the margin amount of the mask opening with respect to the first opening.

  When formed as designed, the distance between the edge of the first opening and the edge of the mask opening is smaller than the distance between the edge of the chip opening and the edge of the mask opening of the chip. preferable. In this case, the distance between the edge of the first opening and the edge of the mask opening may be smaller than the distance between the edge of the chip opening and the edge of the chip mask opening in a plurality of directions. The distance between the edge of the chip opening and the edge of the chip mask opening in the first direction may be smaller. In the latter case, it can be determined that the displacement direction of the mask opening with respect to the first opening is the first direction.

  After the step of forming the element isolation film and before the step of measuring the conductivity, the method includes the step of forming a first conductivity type impurity region in the semiconductor substrate located in the second opening. Also good.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film having a first opening, a second opening, and a third opening on a first conductivity type semiconductor substrate,
Forming a photosensitive film on the semiconductor substrate located in each of the first to third openings and on the element isolation film;
The photosensitive film is exposed to light using a reticle and then developed, whereby a first mask opening including the first opening and its periphery inside, and the second opening and its surroundings. Forming a mask film on the element isolation film, each having a second mask opening including
By introducing a second conductivity type impurity using the mask film as a mask, the second conductive layer is introduced into each of the semiconductor substrate located in the first opening and the semiconductor substrate located in the second opening. Forming a type impurity region;
Forming a first silicide film on the surface of the semiconductor substrate located in the first opening, and forming a second silicide film on the surface of the semiconductor substrate located in the second opening; ,
Measuring conductivity between the semiconductor substrate located in the third opening and the first silicide film, and the semiconductor substrate located in the third opening and the second silicide film; Measuring the continuity between:
Comprising
When formed as designed, the distance between the edge of the first opening and the edge of the first mask opening is the distance between the edge of the second opening and the edge of the second mask opening. Less than distance.

Another method of manufacturing a semiconductor device according to the present invention includes an element isolation film having a first opening, a second opening, a third opening, and a fourth opening in a first conductivity type semiconductor substrate. Forming a step;
Forming a photosensitive film on the semiconductor substrate and the element isolation film located in each of the first to fourth openings;
The photosensitive film is exposed to light using a reticle and then developed, whereby a first mask opening including the first opening and its periphery inside, and the second opening and its surroundings. Forming a mask film on the element isolation film, each having a second mask opening including
By introducing a second conductivity type impurity using the mask film as a mask, the second conductive layer is introduced into each of the semiconductor substrate located in the first opening and the semiconductor substrate located in the second opening. Forming a type impurity region;
Forming a first silicide film on the surface of the semiconductor substrate located in the first opening, and forming a second silicide film on the surface of the semiconductor substrate located in the second opening; ,
Conductive resistance between the semiconductor substrate located in the third opening and the first silicide film, and the semiconductor substrate located in the fourth opening and the second silicide film, And measuring the conductivity between
When formed as designed, the distance between the edge of the first opening and the edge of the first mask opening is the distance between the edge of the second opening and the edge of the second mask opening. Less than distance.

  When formed as designed, the distance between the edge of the first opening and the edge of the first mask opening is such that the edge of the second opening and the second mask opening in a plurality of directions. The distance between the edge of the first opening and the edge of the first mask opening in the first direction may be smaller than the distance between the edge of the second opening and the edge of the second opening. It may be smaller than the distance of the edge of the second mask opening.

A semiconductor device according to the present invention includes a plurality of regions in which semiconductor chips are formed, and a first conductivity type semiconductor substrate including a dicing region that separates the plurality of regions from each other;
An element isolation film formed on the semiconductor substrate located in the dicing region and having first and second openings adjacent to each other;
A second conductivity type impurity region formed in the semiconductor substrate located in the first opening;
A silicide film formed on a surface of the semiconductor substrate located in the first opening;
A first pad connected to the silicide film;
A second pad connected to the semiconductor substrate located in the second opening;
Comprising
When formed as designed, the second conductivity type impurity region is formed on the entire surface of the semiconductor substrate located in the first opening.

Another semiconductor device according to the present invention includes a first conductivity type semiconductor substrate,
An element isolation film formed in the semiconductor substrate and having a first opening, a second opening adjacent to the first opening, and a third opening adjacent to the second opening; ,
A second conductivity type impurity region formed in each of the semiconductor substrate located in the first opening and the semiconductor substrate located in the second opening;
A first silicide film formed on a surface of the semiconductor substrate located in the first opening;
A second silicide film formed on the surface of the semiconductor substrate located in the second opening;
A first pad connected to the first silicide film;
A second pad connected to the second silicide film;
A third pad connected to the semiconductor substrate located in the third opening;
And the second conductivity type impurity region is formed on the entire surface of the semiconductor substrate located in each of the first and second openings.

Another semiconductor device according to the present invention includes a first conductivity type semiconductor substrate,
A first opening, a second opening, a third opening adjacent to the first opening, and a fourth opening adjacent to the second opening formed in the semiconductor substrate. An element isolation film having
A second conductivity type impurity region formed in each of the semiconductor substrate located in the first opening and the semiconductor substrate located in the second opening;
A first silicide film formed on a surface of the semiconductor substrate located in the first opening;
A second silicide film formed on the surface of the semiconductor substrate located in the second opening;
A first pad connected to the first silicide film;
A second pad connected to the second silicide film;
A third pad connected to the semiconductor substrate located in the third opening;
A fourth pad connected to the semiconductor substrate located in the fourth opening;
And the second conductivity type impurity region is formed on the entire surface of the semiconductor substrate located in each of the first and second openings.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views for explaining the semiconductor device manufacturing method according to the first embodiment. The semiconductor device manufactured according to the present embodiment includes a plurality of chip regions 1a each serving as a semiconductor chip, and a dicing region 1b that separates the semiconductor chips from each other. A transistor is formed in each chip region 1a, and a TEG is formed in the dicing region 1b. This TEG is for measuring the shift amount of the opening of the photoresist film with respect to the opening of the element isolation film.

  First, as shown in FIG. 1A, a silicon oxide film (not shown) and a silicon nitride film (not shown) are stacked in this order on a first conductivity type silicon substrate 1. Next, a photoresist film (not shown) is applied on the silicon nitride film. Next, the photoresist film is exposed using a reticle and then developed. Thereby, an opening pattern is formed in the photoresist film. Next, the silicon nitride film and the silicon oxide film are etched using the photoresist film as a mask. Thereby, an opening pattern is formed in the silicon nitride film and the silicon oxide film. Thereafter, the photoresist film is removed.

  Next, the silicon substrate 1 is thermally oxidized using the silicon nitride film as a mask. Thereby, an element isolation film 2 is formed on the silicon substrate 1. The element isolation film 2 has an opening 2a located in the chip region 1a and openings 2b, 2c, 2d located in the dicing region 1b. The openings 2a and 2d are adjacent to the opening 2c, respectively. The shapes and sizes of the openings 2a, 2b, 2d are preferably the same. Thereafter, the silicon nitride film and the silicon oxide film are removed.

  The positions of the openings 2a to 2d are determined by the position of the opening pattern formed in the photoresist film on the silicon nitride film. For this reason, when the position of the opening pattern is deviated, the positions of the openings 2a to 2d are also deviated, but the direction and amount of deviation of the openings 2a to 2d are the same. 1 and 2 show a case where the openings 2a to 2d are formed as designed.

  The element isolation film 2 may be embedded in a groove formed in the silicon substrate 1 by a trench isolation method. In this case, the groove of the silicon substrate 1 is formed by etching the silicon substrate 1 using the above silicon nitride film as a mask. For this reason, also in the trench isolation method, the positions of the openings 2a to 2d of the element isolation film 2 are determined by the position of the opening pattern formed in the photoresist film, and the displacement direction of the openings 2a to 2d and The shift amounts are the same.

  Next, the silicon substrate 1 is thermally oxidized. Thereby, the gate insulating film 3a is formed on the silicon substrate 1 located in the opening 2a. Thermal oxide films 3b, 3c, 3d are also formed on the silicon substrate 1 located in the openings 2b, 2c, 2d.

  Next, a polysilicon film is formed on the entire surface including the gate insulating film 3a by the CVD method. Next, a resist pattern (not shown) is formed on the polysilicon film, and the polysilicon film is etched using this resist pattern as a mask. As a result, the polysilicon film is patterned to form the gate electrode 4a located on the gate insulating film 3a. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 1B, a photoresist film 50 is applied on the entire surface including each of the thermal oxide films 3b to 3d, and the photoresist film 50 is exposed and developed. As a result, an opening 50 a located on and around the opening 2 a is formed in the photoresist film 50. Next, a second conductivity type impurity is implanted into the silicon substrate 1 using the photoresist film 50, the element isolation film 2, and the gate electrode 4a as a mask. As a result, two low-concentration impurity regions 6a of the second conductivity type are formed in the silicon substrate 1 located in the opening 2a.

  Thereafter, the photoresist film 50 is removed as shown in FIG. Next, a silicon oxide film is formed on the entire surface including on the gate electrode 4a, and this silicon oxide film is etched back. Thereby, the sidewall 5 is formed on the sidewall of the gate electrode 4a. In the etch back process, the thermal oxide films 3b to 3d are removed from the silicon substrate 1 located in the openings 2b to 2d.

  Next, as shown in FIG. 2A, a photoresist film 51 is applied on the element isolation film 2 and the openings 2a to 2d. Next, the photoresist film 51 is exposed using a reticle and then developed. As a result, an opening 51a located on and around the opening 2a, an opening 51b located on the opening 2b, and an opening 2d and an opening 51d located therearound are formed in the photoresist film 51. Is done.

When viewed from a direction substantially perpendicular to the substrate 1, the opening 51a is larger than the opening 2a, the opening 51b is larger than the opening 2b, and the opening 51d is larger than the opening 2d. When formed as designed, margins _{L 2} of the opening 51b and the opening portion 2b, the margin _{L 3} smaller than the opening 51d and the opening portion 2d. Margin _{L 3} is margin _{L 1} is smaller than the opening 51a and the opening portion 2a. Note that the margin L ₁ in the present embodiment, the minimum design rule.

  Note that the direction and amount of displacement of the openings 51a to 51d are the same. However, FIG. 2 shows a case where the openings 51a to 51d are formed as designed.

  Next, a second conductivity type impurity is introduced into the silicon substrate 1 using the photoresist film 51 and the element isolation film 2 as a mask. As a result, two second-conductivity type impurity regions 7a that serve as the source and drain of the transistor are formed in the silicon substrate 1 located in the opening 2a. In this way, a second conductivity type transistor is formed on the silicon substrate 1 located in the opening 2a.

  The second conductivity type impurity region 7b is also formed on the entire surface of the silicon substrate 1 located in the opening 2b, and the second conductivity type impurity region 7d is also formed on the entire surface of the silicon substrate 1 located in the opening 2d. Is done.

  Thereafter, the photoresist film 51 is removed as shown in FIG. Next, a photoresist film 52 is applied on the element isolation film 2 and the openings 2a to 2d. Next, the photoresist film 52 is exposed using a reticle and then developed. As a result, an opening 52a located on and around the opening 2c is formed in the photoresist film 52. Next, a first conductivity type impurity is introduced into the silicon substrate 1 using the photoresist film 52 as a mask. As a result, a first conductivity type impurity region 7c is formed in the silicon substrate 1 located in the opening 2c.

  Thereafter, the photoresist film 52 is removed as shown in FIG. Next, a metal film (for example, titanium film: not shown) is formed on the entire surface of the transistor, on each of the impurity regions 7b to 7d located in the openings 2b, 2c, and 2d and on the element isolation film 2 by, for example, sputtering. Form. Next, the silicon substrate 1 and the metal film are heat treated. Thus, a silicide film 8a is formed on the surface of the impurity region 7a of the transistor, and a silicide film 8f is formed on the surface of the gate electrode 4a. Silicide films 8b, 8c, 8d are formed on the surfaces of the impurity regions 7b, 7c, 7d, respectively. Thereafter, the non-silicided metal film is removed.

  Next, as shown in FIG. 2D, an interlayer insulating film 9 is formed on the transistor, the silicide films 8b to 8d, 8f, and the element isolation film 2 by the CVD method. Next, a photoresist film (not shown) is applied on the interlayer insulating film 9, and the photoresist film is exposed and developed. Thereby, an opening pattern is formed in the photoresist film. Next, the interlayer insulating film 9 is etched using this photoresist film as a mask. Thereby, connection holes 9a, 9b, 9c, 9d are formed in the interlayer insulating film 9. The connection hole 9a is formed on each of the two silicide films 8a, and the connection holes 9b to 9d are formed on the silicide films 8b to 8d, respectively. Thereafter, the photoresist film is removed.

  Next, a tungsten film is formed in the connection holes 9a to 9d and on the interlayer insulating film 9 by a CVD method, and the tungsten film located on the interlayer insulating film 9 is removed by an etch back or CMP method. Thereby, tungsten plugs 10a, 10b, 10c, and 10d are embedded in the connection holes 9a to 9d, respectively.

  Next, an Al alloy film is formed by sputtering on each of the tungsten plugs 10a to 10d and on the interlayer insulating film 9. Next, a photoresist film (not shown) is applied on the Al alloy film, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the Al alloy film. Next, the Al alloy film is etched using this resist pattern as a mask. Thereby, the Al alloy film is patterned, and Al alloy wiring 11a and Al alloy pads 11b, 11c, and 11d are formed. Two Al alloy wirings 11a are formed and pass over different tungsten plugs 10a. The Al alloy pads 11b to 11d are located on the tungsten plugs 10b to 10d, respectively.

Next, a voltage is applied between the Al alloy pads 11b and 11c. As described above, FIG. 2 shows a case where the openings 2a to 2d and the openings 51a to 51d are formed as designed. In this case, even if a voltage is applied between the Al alloy pads 11b and 11c, no current leaks.
Thus, Al alloy pad 11b, since no current flows between 11c mutual positional deviation amount of the opening 51a~51d for opening 2a~2d is less than the margin _{L 2} of the opening 51d and the opening portion 2d I understand that there is.

  3 and 4 are cross-sectional views illustrating a case where the positions of the openings 51a to 51d of the photoresist film 51 are shifted from the openings 2a to 2d of the element isolation film 2 by a certain value or more. As described above, the positions of the openings 2a to 2d of the element isolation film 2 are shifted by the same amount in the same direction. The positions of the openings 51a to 51d of the photoresist film 51 are shifted by the same amount in the same direction.

3 In the example shown (A), the shift amount of the position of the opening 51a~51d for opening 2a~2d is larger than the margin _{L 2} of the opening 51d and the opening 2d, the opening 51d and the opening portion 2d less than the margin _{L 3.} In this case, a part of the opening 2 b is covered with the photoresist film 51, but neither of the openings 2 a and 2 d is covered with the photoresist film 51. For this reason, the impurity region 7a is formed as designed. An impurity region 7d is formed on the entire surface of the silicon substrate 1 located in the opening 2d. However, a region 7f into which no impurity is introduced is formed in the silicon substrate 1 located in the opening 2b.

  In this case, as shown in FIG. 3B, when a voltage is applied between the Al alloy pads 11b and 11c, the tungsten plug 10b, the silicide film 8b, the region 7f, and the silicon are formed between the Al alloy pads 11b and 11c. Conduction is made through the main body of the substrate 1, the impurity region 7c, the silicide film 8c, and the tungsten plug 10c. On the other hand, even if a voltage is applied between the Al alloy pads 11c and 11d, the Al alloy pads 11c and 11d are not electrically connected to each other.

Therefore, the deviation amount of the opening 51a~51d for opening 2a~2d is larger than the margin _{L 2} of the opening 51b and the opening portion 2b, it is seen smaller than the margin _{L 3} of the opening 51d and the opening 2b.

In the example shown in each of FIGS. 4, positional deviation amount of the opening 51a~51d for opening 2a~2d is larger than the margin _{L 3} of the opening 51d and the opening 2d, the opening 51a and the opening portion 2a margin _{L 1} smaller. In this case, a part of the opening 2 b and a part of the opening 2 d are each covered with the photoresist film 51, but neither part of the opening 2 a is covered with the photoresist film 51. Therefore, the impurity region 7a is formed as designed. However, regions 7f and 7g into which impurities are not introduced are formed in the silicon substrate 1 located in the opening 2b and the silicon substrate 1 located in the opening 2d, respectively.

  In this case, as shown in FIG. 4B, when a voltage is applied between the Al alloy pads 11b and 11c, the tungsten plug 10b, the silicide film 8b, the region 7f, and the silicon are formed between the Al alloy pads 11b and 11c. Conduction is made through the main body of the substrate 1, the impurity region 7c, the silicide film 8c, and the tungsten plug 10c. Even when a voltage is applied between the Al alloy pads 11c and 11d, the tungsten alloy plug 11c, the silicide film 8c, the impurity region 7c, the main body of the silicon substrate 1 and the region 7g, Conduction is made through the silicide film 8d and the tungsten plug 10d.

Therefore, the positional deviation amount of the opening 51a~51d for opening 2a~2d It can be seen larger than the margin _{L 3} of the opening 51d and the opening portion 2d. Further, when the transistors located in the opening 2a can be confirmed to be operating correctly, shift amount, it can be seen less than the margin L ₁ of the opening 51a and the opening portion 2a.

Each of FIGS. 5, margins _{L 2} of the opening 51b for opening 2b, is a plan view for explaining a margin _{L 3} of the opening 51d for opening 2d. In FIG. 5A, the openings 2b, 2d, 51b, 51d are rectangular or square. The margin L ₂ are identical to each other in vertical and horizontal margin L ₃ are also identical to each other in vertical and horizontal.

On the other hand, in FIG. 5B, the openings 2b, 2d, 51b, 51d are rectangular or square. The margins L ₂ and L ₃ are small in a specific direction (right direction in the figure) and sufficiently large in other directions (up and down and left direction in the figure). In this way, in addition to the amount of displacement of the positions of the openings 51a to 51d with respect to the openings 2a to 2d, the displacement direction (left direction in the example of this figure) can also be detected.

  As described above, according to the first embodiment, it is possible to determine whether the Al alloy pads 11b and 11c are electrically connected to each other and whether or not the Al alloy pads 11c and 11d are electrically connected to each other. The amount of deviation of the openings 51a to 51d with respect to 2a to 2d can be accurately measured.

Also, the margin L ₂ between the opening 51b of the photoresist film 51 and the opening 2b of the element isolation film 2, and the margin L ₃ between the opening 51d and the opening 2d, respectively, and the margin L ₁ between the opening 51a and the opening 2a. Since it is made smaller, it is possible to detect a deviation amount that does not cause the transistor to be defective. Therefore, the deviation can be corrected before the deviation becomes large and the semiconductor chip becomes defective.

  Further, a combination of the opening of the element isolation film 2 and the opening of the photoresist film 51 located on the opening is added to the TEG, and the opening of the photoresist film 51 and the opening of the element isolation film 2 are added. (For example, when the above-described L1 is 0.25 μm, the margin is set in increments of 0.1 μm between 0 to 0.6 μm), whereby a photoresist film for the opening of the element isolation film 2 is formed. The amount of deviation of the 51 openings can be measured finely. Further, by widening the margin range, the deviation amount of the opening of the photoresist film 51 with respect to the opening of the element isolation film 2 can be measured in a wide range.

  When the above-described TEGs are provided at a plurality of locations on the silicon substrate 1, the yield of the semiconductor chips included in the silicon substrate 1 is statistically determined based on the number of TEGs whose deviation amount is equal to or greater than the reference value. You can also.

  FIG. 6 is a cross-sectional view for explaining the configuration of the semiconductor device according to the second embodiment. The semiconductor device according to the present embodiment is different from the semiconductor device formed according to the first embodiment in the following points. First, the opening 2d located in the dicing region 1b, the impurity region 7d, the silicide film 8d, the connection hole 9d, the tungsten plug 10d, and the Al alloy pad 11d are separated from the openings 2b and 2c.

  In the element isolation film 2, an opening 2e adjacent to the opening 2d is formed. Further, a first conductivity type impurity region 7e is formed in the silicon substrate 1 located in the opening 2e, and a silicide film 8e is formed on the surface of the impurity region 7e. In addition, a connection hole 9e located on the silicide film 8e is formed in the interlayer insulating film 9, and a tungsten plug 10e is embedded in the connection hole 9e. An Al alloy pad 11e connected to the tungsten plug 10e is formed on the interlayer insulating film 9.

  The impurity region 7e, the silicide film 8e, the connection hole 9e, the tungsten plug 10e, and the Al alloy pad 11e are the impurity region 7c, the silicide films 8a to 8d, the connection holes 9a to 9d, the tungsten plugs 10a to 10d, and the Al alloy wiring, respectively. It is formed in the same process as 11a.

  Since other configurations and forming methods are the same as those in the first embodiment, the same reference numerals are given and description thereof is omitted.

In this embodiment, it is the same as that of the first embodiment by examining whether or not the Al alloy pads 11b and 11c are electrically connected and whether or not the Al alloy pads 11d and 11e are electrically connected. Due to the action, it is possible to accurately measure the shift amounts of the openings 51a to 51e with respect to the openings 2a to 2e.
Therefore, the same effect as that of the first embodiment can be obtained by this embodiment.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

FIGS. 4A to 4C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the first embodiment. FIGS. (A)-(D) are sectional drawings for demonstrating the next process of FIG. (A), (B) is sectional drawing explaining the case where the position of opening part 51a-51d with respect to opening part 2a-2d has shifted | deviated more than a fixed value. (A), (B) is sectional drawing explaining the case where the position of opening part 51a-51d with respect to opening part 2a-2d has shifted | deviated more than a fixed value. (A), (B) is a plan view for explaining a margin _{L 3} of the opening 51d for margin _{L 2,} the opening 2d of the opening portion 51b for opening 2b. Sectional drawing for demonstrating the structure of the semiconductor device which concerns on 2nd Embodiment. (A), (B) is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device. (A), (B) is sectional drawing for demonstrating the problem in the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 ... Silicon substrate, 1a ... Chip area | region, 1b ... Dicing area | region, 2,102 ... Element isolation film, 2a-2e, 102a ... Opening part, 3a, 103 ... Gate insulating film, 3b-3d ... Thermal oxide film, 4a, 104 ... gate electrodes, 5, 105 ... sidewalls, 6a, 106 ... low concentration impurity regions, 7a-7e, 107 ... impurity regions, 7f, 7g, 101b ... regions where no impurities are introduced, 8a-8f, 108a, 108b ... Silicide film, 9, 109 ... Interlayer insulating film, 9a-9e ... Connection hole, 10a-10e, 110 ... Tungsten plug, 11a, 111 ... Al alloy wiring, 11b-11e ... Al alloy pad, 50-52, 120 ... Photoresist film, 50a, 51a to 51e, 52a ... Opening

Claims (14)

Forming an element isolation film having a first opening and a second opening on a first conductivity type semiconductor substrate;
Forming a photosensitive film on the semiconductor substrate located in the first and second openings and on the element isolation film;
A step of forming a mask film having a mask opening including the first opening and the periphery thereof on the element isolation film by exposing the photosensitive film using a reticle and then developing the photosensitive film. When,
Forming a first second conductivity type impurity region in the semiconductor substrate located in the first opening by introducing a second conductivity type impurity using the mask film as a mask;
Forming a first silicide film on a surface of the semiconductor substrate located in the first opening;
Measuring the conductivity between the semiconductor substrate located in the second opening and the first silicide film;
A method for manufacturing a semiconductor device comprising: The semiconductor substrate includes a plurality of regions in which semiconductor chips are formed and a dicing region that separates the plurality of regions in which the semiconductor chips are formed;
The method for manufacturing a semiconductor device according to claim 1, wherein the first opening and the second opening are located in the dicing region. In the step of forming the element isolation film, a chip opening located in a region where the semiconductor chip is formed,
In the step of forming the mask film, a chip mask opening located on and around the chip opening is formed in the mask film,
In the step of forming the first second conductivity type impurity region, a second second conductivity type impurity region is formed in the semiconductor substrate located in the chip opening,
3. The method of manufacturing a semiconductor device according to claim 2, wherein in the step of forming the first silicide film, a second silicide film is formed on a surface of the semiconductor substrate located in the chip opening.   When formed as designed, a distance between an edge of the first opening and an edge of the mask opening is smaller than a distance of an edge of the chip opening and an edge of the chip mask opening. 4. A method for manufacturing a semiconductor device according to 3.   When formed as designed, the distance between the edge of the first opening and the edge of the mask opening is the distance between the edge of the chip opening and the edge of the chip mask opening in a plurality of directions. The method for manufacturing a semiconductor device according to claim 4, which is smaller.   When formed as designed, the distance between the edge of the first opening and the edge of the mask opening is the distance between the edge of the chip opening and the edge of the chip mask opening in the first direction. The method for manufacturing a semiconductor device according to claim 4, which is smaller than the distance.   A step of forming a first conductivity type impurity region in the semiconductor substrate located in the second opening after the step of forming the element isolation film and before the step of measuring the conductivity. Item 7. A method for manufacturing a semiconductor device according to any one of Items 1 to 6. Forming an element isolation film having a first opening, a second opening, and a third opening on a first conductivity type semiconductor substrate;
Forming a photosensitive film on the semiconductor substrate located in each of the first to third openings and on the element isolation film;
The photosensitive film is exposed to light using a reticle and then developed, whereby a first mask opening including the first opening and its periphery inside, and the second opening and its surroundings. Forming a mask film on the element isolation film, each having a second mask opening including
By introducing a second conductivity type impurity using the mask film as a mask, the second conductive layer is introduced into each of the semiconductor substrate located in the first opening and the semiconductor substrate located in the second opening. Forming a type impurity region;
Forming a first silicide film on the surface of the semiconductor substrate located in the first opening, and forming a second silicide film on the surface of the semiconductor substrate located in the second opening; ,
Measuring conductivity between the semiconductor substrate located in the third opening and the first silicide film, and the semiconductor substrate located in the third opening and the second silicide film; Measuring the continuity between:
Comprising
When formed as designed, the distance between the edge of the first opening and the edge of the first mask opening is the distance between the edge of the second opening and the edge of the second mask opening. Manufacturing method of semiconductor device smaller than distance. Forming an element isolation film having a first opening, a second opening, a third opening, and a fourth opening on a first conductivity type semiconductor substrate;
Forming a photosensitive film on the semiconductor substrate and the element isolation film located in each of the first to fourth openings;
The photosensitive film is exposed to light using a reticle and then developed, whereby a first mask opening including the first opening and its periphery inside, and the second opening and its surroundings. Forming a mask film on the element isolation film, each having a second mask opening including
By introducing a second conductivity type impurity using the mask film as a mask, the second conductive layer is introduced into each of the semiconductor substrate located in the first opening and the semiconductor substrate located in the second opening. Forming a type impurity region;
Forming a first silicide film on the surface of the semiconductor substrate located in the first opening, and forming a second silicide film on the surface of the semiconductor substrate located in the second opening; ,
Conductive resistance between the semiconductor substrate located in the third opening and the first silicide film, and the semiconductor substrate located in the fourth opening and the second silicide film, Measuring the continuity between:
Comprising
When formed as designed, the distance between the edge of the first opening and the edge of the first mask opening is the distance between the edge of the second opening and the edge of the second mask opening. Manufacturing method of semiconductor device smaller than distance.   When formed as designed, the distance between the edge of the first opening and the edge of the first mask opening is such that the edge of the second opening and the second mask opening in a plurality of directions. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device manufacturing method is smaller than a distance between edges of the portion.   When formed as designed, the distance between the edge of the first opening in the first direction and the edge of the first mask opening is the edge of the second opening in the first direction. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the distance is smaller than a distance between edges of the second mask opening. A first conductivity type semiconductor substrate comprising a plurality of regions in which semiconductor chips are formed, and a dicing region that separates the plurality of regions from each other;
An element isolation film formed on the semiconductor substrate located in the dicing region and having first and second openings adjacent to each other;
A second conductivity type impurity region formed in the semiconductor substrate located in the first opening;
A silicide film formed on a surface of the semiconductor substrate located in the first opening;
A first pad connected to the silicide film;
A second pad connected to the semiconductor substrate located in the second opening;
Comprising
When formed as designed, the second conductivity type impurity region is formed over the entire surface of the semiconductor substrate located in the first opening. A first conductivity type semiconductor substrate;
An element isolation film formed in the semiconductor substrate and having a first opening, a second opening adjacent to the first opening, and a third opening adjacent to the second opening; ,
A second conductivity type impurity region formed in each of the semiconductor substrate located in the first opening and the semiconductor substrate located in the second opening;
A first silicide film formed on a surface of the semiconductor substrate located in the first opening;
A second silicide film formed on the surface of the semiconductor substrate located in the second opening;
A first pad connected to the first silicide film;
A second pad connected to the second silicide film;
A third pad connected to the semiconductor substrate located in the third opening;
When the semiconductor device is formed as designed, the second conductivity type impurity region is formed on the entire surface of the semiconductor substrate located in each of the first and second openings. A first conductivity type semiconductor substrate;
A first opening, a second opening, a third opening adjacent to the first opening, and a fourth opening adjacent to the second opening formed in the semiconductor substrate. An element isolation film having
A second conductivity type impurity region formed in each of the semiconductor substrate located in the first opening and the semiconductor substrate located in the second opening;
A first silicide film formed on a surface of the semiconductor substrate located in the first opening;
A second silicide film formed on the surface of the semiconductor substrate located in the second opening;
A first pad connected to the first silicide film;
A second pad connected to the second silicide film;
A third pad connected to the semiconductor substrate located in the third opening;
A fourth pad connected to the semiconductor substrate located in the fourth opening;
When the semiconductor device is formed as designed, the second conductivity type impurity region is formed on the entire surface of the semiconductor substrate located in each of the first and second openings.

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