JP2007149222A - Semiconductor memory and memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory and a memory system in which high speed read-out can be performed by shortening a read-out time of data, and high reliability can be held. <P>SOLUTION: The semiconductor memory is provided with a memory cell array 11a, a cell array 11b for parity, a sense amplifier 14a with a latch function, a sense amplifier 14b for parity, an error detection/correction circuit 16 which performs error detection of sense amplifier output data for each read-out cycle, in which when an error is detected, data after error correction is generated, while, an error detection flag is generated and it is output to the outside of a chip, and a selector 17 which is controlled by the error detection flag and in which data after error correction and data output from the sense amplifier and before error correction are selected, and they are output to the outside of the chip as a memory output. And when the error detection flag is received, the sense amplifier does not latch main body data being newly detected and amplified, but latches continuously data of the main body detected and amplified hitherto. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory and a memory system, and more particularly to a memory high-speed reading system equipped with an ECC (Error Correction Code), and is used for a memory system such as a memory embedded microcomputer.

  In some cases, the memory portion becomes a defective product due to miniaturization of the processing technology of the semiconductor memory or the memory-embedded microcomputer or an accidental defect in the processing process. When high reliability of the memory unit is required in the market, a memory having an ECC function is generally used. An ECC function-equipped memory requires a redundant path and a redundant circuit that correct memory errors and correct read data to correct data. When writing data to the memory in the ECC function-equipped memory, parity data (parity bits) for error correction is generated and written in addition to the write data. When reading data, write data and parity data are read, and final data after error correction by a redundant circuit is output. At this time, the redundant time for error correction is excessively applied to the memory not equipped with the ECC function, and this causes an increase in the read time and consequently a decrease in the maximum operating frequency of the entire system. Yes.

  For example, a conventional ECC function-equipped memory that detects 1-bit error and corrects 1-bit for 32-bit read data, and outputs a 32-bit output at the I / O (input / output) terminal of the sense amplifier after the read address is input. A total of 38 bits of 6-bit output for ECC parity correction are output. The syndrome circuit receives the 38-bit output and generates a 6-bit syndrome output (A to F). The error detection / correction circuit receives the 6-bit syndrome output and the 32-bit output of the sense amplifier, and outputs 32-bit data corrected by 1-bit error and 1-bit.

  A memory error does not occur every time it is read, and the probability of occurrence is extremely low, and varies depending on the memory capacity and usage conditions. Nevertheless, in the conventional memory with ECC function, the read data of the cell array passes through the path of the syndrome calculation circuit and the error detection / correction circuit for each read, so that the read access is slowed by the delay of this path. As a result, the performance of the entire system is reduced.

  In general, in the process of defect selection inspection during the manufacture of a memory, the initial defective product of the memory is not put on the market by performing the parity bit inspection for error correction without using the ECC function. .

In Patent Document 1, in a nonvolatile semiconductor memory equipped with an ECC function, read data before correction is output simultaneously with the generation of a syndrome, and an error status signal indicating whether or not there is an error after the generation of the syndrome is output. Thus, it is disclosed that corrected read data is output in accordance with the presence or absence of an external request.
JP 2000-305861 A

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to provide a semiconductor memory and a memory system capable of shortening data read time and maintaining high reliability.

  A semiconductor memory according to a first aspect of the present invention includes a memory cell array that stores a plurality of bits of main data as a unit, and a parity cell array that stores parity data corresponding to the main data at the same row address as the memory cell array. A sense amplifier that latches main body data read from the memory cell array based on a system clock and an address, and continues latching the previous main body data without latching new main body data when an error detection flag is received; A parity sense amplifier for detecting and amplifying parity data read from the parity cell array based on the system clock and address, and output data of the sense amplifier and output data of the parity sense amplifier for each read cycle. Sind Syndrome calculation circuit that outputs the calculation result data of multiple bits, and error detection based on the output data of the sense amplifier and the output data of the syndrome calculation circuit, and error correction if an error is detected An error detection / correction circuit that generates later data and generates the error detection flag after a required error detection time, supplies the error detection flag to the sense amplifier, and outputs the error detection flag to the outside of the chip, and the error detection flag. And a selector that is controlled and selects data after error correction generated by the error detection / correction circuit and data before error correction output from the sense amplifier, and outputs the data as memory output to the outside of the chip.

  A memory system according to a second aspect of the present invention includes a semiconductor memory according to the first aspect of the present invention, an address is supplied to the semiconductor memory, data read control is performed, and output data of the semiconductor memory is captured. When the error detection flag is received, it is recognized that a memory error has occurred in the semiconductor memory, the memory output data for the previously supplied address is determined to be error data, and the data has already been captured. And a CPU having a function of controlling the memory output data to be discarded and to fetch the memory output data after error correction after one cycle.

  A semiconductor memory according to a third aspect of the present invention includes a memory cell array that stores a plurality of bits of main data as a unit, and a parity cell array that stores parity data corresponding to the main data at the same row address as the memory cell array. The main body data read from the memory cell array is latched based on the system clock and the address. When an error detection flag supplied from the outside of the semiconductor memory is received, the new main body data is not latched and the previous main body data is not latched. A sense amplifier for continuing latching; and a parity sense amplifier for detecting and amplifying parity data read from the parity cell array based on the system clock and address, and output data and parity sense amplifier of the sense amplifier Output data And outputs it to the outside.

  The memory system according to the fourth aspect of the present invention is based on the semiconductor memory according to the third aspect of the present invention and the output data of the sense amplifier and the output data of the parity sense amplifier for each read cycle of the semiconductor memory. Syndrome calculation circuit that outputs the calculation result data of multiple bits, error detection based on the output data of the sense amplifier and the output data of the syndrome calculation circuit, and error correction if an error is detected An error detection / correction circuit that generates later data and generates the error detection flag after a required error detection time, supplies the error detection flag to the sense amplifier, and outputs the error detection flag to the outside of the chip, and the error detection flag. Controlled and error-corrected data generated by the error detection / correction circuit. And a selector for selectively deriving data before error correction output from the sense amplifier and outputting the data to the outside of the chip as a memory output, and supplying an address to the semiconductor memory to perform data read control, When having received the error detection flag having a function to capture the output, recognize that a memory error has occurred in the semiconductor memory, determine that the memory output data for the previously supplied address is error data, A CPU having a function of controlling to discard memory output data that has already been captured and to fetch memory output data after error correction after one cycle.

  According to the semiconductor memory and the memory system of the present invention, it is possible to shorten the data reading time, enable high-speed reading, and maintain high reliability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a semiconductor memory and a memory system using the semiconductor memory according to the first embodiment of the present invention. In this example, 1-bit error detection / detection is performed on 32-bit read data in the semiconductor memory. A read system block for performing 1-bit correction is shown.

  In the memory system shown in FIG. 1, a semiconductor memory 10 is a flash memory equipped with an ECC function, and 20 is a CPU. Compared with the flash memory equipped with the ECC function, the flash memory 10 is provided with (1) a selector 17 and selects the sense amplifier output data (data before error correction) and the data after error correction using ECC. (2) An error detection flag is output from the error detection / correction circuit 16, for example, a Hi level when there is a memory error, and a Low level when there is no memory error. The difference is that it is output to the CPU 20 outside the memory and the selector 17 and the sense amplifier 14a with a latch function are controlled by the error detection flag. The sense amplifier with a latch function is, for example, a sense amplifier / latch circuit having 32-IO.

  That is, in the ECC function-equipped memory 10, the memory cell array 11a stores main data of a plurality of bits, in this example, 32 bits, as a unit, and the parity cell array 11b (denoted as a parity array in the figure) corresponds to the main data. Data for parity correction (6-bit parity data in this example) is stored.

  The row decoder 12, the column decoder 13a, and the parity column decoder 13b select memory cells of the memory cell array 11a and the parity cell array 11b according to an address signal input from the outside of the memory chip (CPU 20). At this time, the memory cell array 11a and the parity cell array 11b are selected by the same row address.

  The sense amplifier 14a is controlled so as to detect and amplify main body data read from the memory cell array 11a and latch it, and to continue latching data when receiving an error detection flag supplied separately. For example, the parity sense amplifier 14b having 6-IO detects and amplifies 6-bit parity data read from the parity array 11b.

  The syndrome calculation circuit 15 performs a syndrome calculation based on the output data of the sense amplifier 14a and the output data of the parity sense amplifier 14b, and outputs the calculation result as 6-bit data (A to F).

  The error detection / correction circuit 16 performs error detection based on the output data of the sense amplifier 14a and the output data of the syndrome calculation circuit 15, and has a function of generating data after error correction when an error is detected. A detection flag is generated, and the error detection flag is supplied to the sense amplifier 14a and output to the CPU 20 outside the memory chip.

  The selector 17 inputs the data after error correction generated by the error detection / correction circuit 16 and the data before error correction output from the sense amplifier 14a, and selects and outputs two inputs according to the error detection flag. . In this case, normally, the data before error correction output from the sense amplifier 14a is selected and output to the CPU 20, and when the error detection flag is received, the data after error correction generated by the error detection / correction circuit 16 is received. Is output to the CPU 20.

  The CPU 20 controls the ECC function-equipped flash memory 10 to perform data writing / reading. When the CPU 20 receives an error detection flag, the CPU 20 performs control as described later.

  FIGS. 2A and 2B are timing charts showing an example of a read operation of the memory with the ECC function shown in FIG. 1 (when there is no memory error / when there is an error). When an address input (for example, address A_n) is determined by the system clock at the time of reading, the reading operation starts, and the data at address A_n is read as a 32-bit output from the sense amplifier 14a through a required reading time from the activation timing of the system clock. It is. At this time, a total of 38 bits are output, that is, the 32-bit output of the sense amplifier 14a and the 6-bit output of the parity sense amplifier 14b. The syndrome calculation circuit 15 receives and calculates 38-bit data and generates a 6-bit syndrome output (A to F).

  The error detection / correction circuit 16 receives the 32-bit output (read data) of the sense amplifier 14a and the 6-bit output of the syndrome calculation circuit 15, and performs 1-bit error and 1-bit correction on the read data. Here, error detection / correction on the sense amplifier output is always performed regardless of the presence or absence of a memory error.

  As shown in FIG. 2A, when a 1-bit error is not detected by the error detection / correction circuit 16, that is, when there is no memory error, the error detection flag is at a low level, and the selector 17 is a sense amplifier. The output (32Bit-IO) is selected as the memory output Dout_n. At this time, since the sense amplifier output is directly selected without performing error detection / correction in the error detection / correction circuit 16, high-speed reading is possible, and the frequency of the system clock can be made higher than before. Note that the sense amplifier output can be directly captured by the unique internal clock, and the data can be held in the internal clock cycle.

  On the other hand, as shown in FIG. 2B, when the error detection / correction circuit 16 detects a 1-bit error and outputs 1-bit corrected 32-bit data, that is, when there is a memory error, With the error error detection / correction processing for the sense amplifier output Sout_n read out after a required read time from the activation timing of the system clock, it takes time to detect the error, that is, one cycle period of the system clock. A delay occurs until the error detection flag is established (Hi level). In this case, the memory output Dout_n and the sense amplifier output data Sout_n are error data Dout_n: NG and Sout_n: NG, respectively. Then, the selector 17 is switched and controlled to select the data Dout_n ECCn after the error correction by the error detection / correction circuit 16 according to the Hi level of the error detection flag, and the sense for the next address A_n + 1 supplied from the CPU 20 is controlled. Control is performed so that the amplifier output data Sout_n + 1 is not latched by the sense amplifier 14a. In addition, since the error detection flag has already been output to the next address A_n + 1, the CPU 20 recognizes that there is a memory error based on the Hi level of the error detection flag, and the memory output Dout_n for the previous address A_n is It is determined that the error data is Dout_n: NG, and control is performed so that the already fetched Dout_n: NG data is discarded and the error-corrected data Dout_n ECCn is fetched (read again). At this time, the CPU 20 further stops outputting the next address A_n + 2, and re-enters the address (current address) A_n + 1 next to the address A_n where the memory error output has occurred. This is the same operation as issuing a wait instruction.

  As a result, the memory 10 reads the re-entry address A_n + 1. Thereafter, the operation as described above is performed on the progressively proceeding addresses. That is, when the error detection flag becomes Hi level, the CPU 20 discards the erroneous data output Dout_n: NG read at high speed and selects the data Dout_n ECCn after the low-speed error correction by the error detection / correction circuit 16. The output delay is a penalty of only one minimum clock (system clock).

  FIG. 3 simply shows the flow of write data during a write operation to the ECC function-equipped memory 10 in FIG. When writing data in the memory, the write data is taken into the check bit generation circuit 31 to generate parity data (parity bits) for error correction, the write data is written into the memory cell array 11a, and the parity bits are written into the parity cell array 11b. Write.

  As described above, according to the semiconductor memory shown in FIG. 1, a redundant path for error correction is provided for each read in order to correct an error in a memory having a very low frequency in an ECC function-equipped memory in which high reliability is required. It is possible to improve the point of transit. In other words, if it is assumed that the frequency of memory failures is extremely low, select normal bypassing data that does not pass through redundant paths in the memory chip (path that directly outputs the sense amplifier output) for normal data. For defective data that occurs very rarely, data after error correction (data that has passed through a redundant path in the memory chip) is read. As a result, it is possible to shorten the time (calculation) through the redundant path and to perform high-speed reading. At this time, a penalty of a one-cycle wait period occurs, but the maximum operating frequency of the entire system is improved, so that the performance of the entire memory system shown in FIG. 1 can be improved.

<Second Embodiment>
FIG. 4 shows a memory system using the flash memory 10a according to the second embodiment of the present invention. This memory system differs from the memory system according to the first embodiment described above with reference to FIGS. 1 to 3 in the configuration of the flash memory 10a. That is, the syndrome calculation circuit 15, the error detection / correction circuit 16, and the selector 17 are mounted in a semiconductor chip (a CPU chip in this example) different from the memory chip. The flash memory 10a outputs a 32-bit body data output and a 6-bit parity data output to the CPU 20a, and controls a latch operation by an error detection flag input from the error detection / correction circuit 16 to the sense amplifier 14a.

  With such a configuration, the configuration of the flash memory 10a can be simplified. In addition, by installing the syndrome calculation circuit 15 and the like in the CPU chip (or another IP chip), it is possible to flexibly cope with the design specifications. In addition, it is possible to cope with fine timing adjustment for an error detection flag (memory error determination flag).

1 is a block diagram showing a semiconductor memory and a memory system using the same according to a first embodiment of the present invention. 2 is a timing chart showing an example of a read operation of the ECC function-equipped memory in FIG. 1. The figure which shows simply the flow of the write data at the time of the write-in operation | movement with respect to the ECC function mounting memory in FIG. The block diagram which shows the memory system using the flash memory which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Flash memory equipped with ECC function, 11a ... Memory cell array, 11b ... Parity cell array, 12 ... Row decoder, 13 ... Column decoder, 14a ... Sense amplifier, 14b ... Parity sense amplifier, 15 ... Syndrome calculation circuit, 16 ... Error Detection / correction circuit, 17 ... selector, 20 ... CPU.

Claims (5)

A memory cell array for storing multi-bit body data as a unit;
A parity cell array for storing parity data corresponding to the body data at the same row address as the memory cell array;
A sense amplifier that latches main body data read from the memory cell array based on a system clock and an address and continues to latch the previous main body data without latching new main body data when receiving an error detection flag;
A parity sense amplifier for detecting and amplifying parity data read from the parity cell array based on the system clock and address;
A syndrome calculation circuit for performing a syndrome calculation based on the output data of the sense amplifier and the output data of the parity sense amplifier for each read cycle, and outputting a plurality of bits of calculation result data; and
Error detection is performed based on the output data of the sense amplifier and the output data of the syndrome calculation circuit. When an error is detected, data after error correction is generated and the error detection flag is generated after a required error detection time. An error detection / correction circuit for supplying the error detection flag to the sense amplifier and outputting the error detection flag to the outside of the chip;
A selector that is controlled by the error detection flag, selects data after error correction generated by the error detection / correction circuit and data before error correction output from the sense amplifier, and outputs the data as a memory output outside the chip; ,
A semiconductor memory comprising: A semiconductor memory according to claim 1;
The semiconductor memory has a function of supplying an address to the semiconductor memory to perform data read control and fetching the output data of the semiconductor memory. When the error detection flag is received, a memory error has occurred in the semiconductor memory. And the memory output data corresponding to the previously supplied address is determined to be error data, and the memory output data that has already been fetched is discarded and the memory output data after error correction after one cycle is fetched. CPU,
A memory system comprising: A memory cell array for storing multi-bit body data as a unit;
A parity cell array for storing parity data corresponding to the body data at the same row address as the memory cell array;
The main body data read from the memory cell array is latched based on the system clock and address, and when the error detection flag supplied from the outside of the semiconductor memory is received, the new main body data is not latched and the previous main body data is latched. Sense amplifier that continues,
A parity sense amplifier that senses and amplifies parity data read from the parity cell array based on the system clock and address;
A semiconductor memory, wherein output data of the sense amplifier and output data of a parity sense amplifier are output to the outside. A semiconductor memory according to claim 3;
A syndrome calculation circuit for performing a syndrome calculation based on the output data of the sense amplifier and the output data of the parity sense amplifier for each read cycle of the semiconductor memory, and outputting a plurality of bits of calculation result data;
Error detection is performed based on the output data of the sense amplifier and the output data of the syndrome calculation circuit. When an error is detected, data after error correction is generated and the error detection flag is generated after a required error detection time. An error detection / correction circuit for supplying the error detection flag to the sense amplifier and outputting the error detection flag to the outside of the chip;
A selector that is controlled by the error detection flag, selects data after error correction generated by the error detection / correction circuit and data before error correction output from the sense amplifier, and outputs the data as a memory output outside the chip; ,
It has a function of supplying an address to the semiconductor memory, performing data read control, and taking in the output of the selector. When receiving the error detection flag, it recognizes that a memory error has occurred in the semiconductor memory. A CPU having a function of determining that the memory output data corresponding to the previously supplied address is error data, discarding the already fetched memory output data, and fetching the memory output data after error correction after one cycle; ,
A memory system comprising:   When the CPU performs control to discard the already fetched memory output data and fetch the memory output data after error correction, the CPU further stops outputting the next address, and sets the address of the memory error output to the semiconductor memory. 5. The memory system according to claim 2, wherein control is performed such that a next address (current address) is reentry into the semiconductor memory and reread is performed.

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