TWI482014B - Memory with dynamic error detection and correction - Google Patents

Description

Memory with dynamic error detection and correction

The present invention relates to memory devices and systems that include error correction code logic.

The memory technology used in integrated circuit memory is being developed toward the use of smaller and smaller technology nodes, and has an increasingly larger capacity memory array in a single integrated circuit chip. As the technology of memory cells evolves, the boundaries of the sensed data become tight. In addition, the ability of the memory cell to preserve data due to the interference of the memory cell itself and the memory cell state caused by the high speed and large number of accesses of adjacent memory cells is also limited by this tighter boundary.

In order to solve the problems caused by the tight boundary and memory cell interference caused by the evolution of memory cell size and density, error correction codes embedded in the integrated circuit memory have been widely used in the industry. Hamming code is a well-known error correction code type that can be used to provide single bit error correction and double bit error detection of protected data. Single bit detection may not be sufficient in some memory technologies. In this case, a multi-bit error correction code technique such as a BCH code can be used. However, using BCH codes consumes a lot of hardware resources, and its error correction capability is still limited.

Accordingly, it would be desirable to provide an improved error correction code technique that can reduce the hardware resources consumed by the technology in an integrated circuit while at the same time increasing the performance of its error correction.

The techniques described herein provide an improved error correction code technique that can be embedded in an integrated circuit memory device using an error correction table. This error correction table contains items that are generated when an error is detected and updated while performing a data read operation. For subsequent reads, the items in this table integrate the data output from this array with the correction bits before the data is entered into the error correction code logic without inserting a write or update operation. The error correction code logic is used. To add the error correction code to the corresponding data to generate error check data.

This error correction form can be referred to as a "dynamic" error correction form because it is used to temporarily correct errors in the material protected by the error correction code (ECC). This error correction code (ECC) may be in this material. Occurs between writes or updates. In addition, this table is "dynamic" and is also automatically changed during subsequent read operations between data writes or updates. The error correction table is used using this error because, for example, the "read disturb" caused by the repeated operation of the read operation causes the error accumulation of the deterioration of the memory cell state to be recorded and corrected.

Other objects and advantages of the present invention will be described in conjunction with the drawings in the following embodiments and the scope of the claims.

To further illustrate the various embodiments, embodiments of the present invention are provided with Figures 1 through 10 of the drawings. The drawings are a part of the disclosure of the present invention, and are mainly used to explain the embodiments, and the operation of the embodiments may be explained in conjunction with the related description of the specification. With reference to such content, those of ordinary skill in the art should be able to understand other possible embodiments and advantages of the present invention.

Figures 1 and 2 show the logical structure of the basic error correction code (ECC) applied to the memory system. Figure 1 shows a memory 20, which may be an integrated circuit memory with error correction code (ECC) logic to control the corresponding data stream during a read operation. The data addressed to the memory 20 during a read operation, the addressed data is transferred to a buffer 22 and error correction code (ECC) logic 21, and the error correction code (ECC) associated with the addressed material is also transmitted to Error Correction Code (ECC) Logic 21. The addressed data includes, for example, a set of data for a page or other multi-byte data, and an error correction code (ECC) is calculated based on the set of data. This error correction code (ECC) logic 21 determines whether one or more errors are included in the addressed data and whether one or more of the detected errors can be corrected. The number of errors in the error check data for a given application and whether it can be corrected is determined by the type of error correction code (ECC) used. If the error can be corrected, the correction data generated from the error correction code (ECC) logic 21 will be combined with the address data in the buffer 22 having the logic 23 that merges the addressed data with the corrected data. This error check block with the corrected data merge is then provided as an output.

Figure 2 shows this memory 20, which may be an integrated circuit memory with error correction code (ECC) logic to control the corresponding data stream during a read operation. When a data is written to an operation of a block of the memory 20, the data to be written is transferred to a buffer 22. Usually in a parallel manner, error correction code (ECC) logic 21 calculates an error correction code (ECC) that will be stored in association with this material. The data from the buffer 22 and the error correction code (ECC) from the error correction code (ECC) logic 21 are stored in the memory 20.

Error Correction Code (ECC) Logic 21 shown in Figures 1 and 2 And buffer 22 can be configured in a memory system in many different implementations. For example, error correction code (ECC) logic 21 and buffer 22 may be implemented using an operating system of a host processor. In addition, error correction code (ECC) logic 21 and buffer 22 can be implemented in a memory control device that is typically associated with other memory devices for controlling memory 20. In other embodiments, error correction code (ECC) logic 21 and buffer 22 may be embedded within an integrated circuit having a memory array.

Figure 3A shows a representation of an error correction code (ECC) system similar to that shown in Figures 1 and 2, in which case the data is written and read before being updated or overwritten by new data. Take multiple times. For this case, the number of reads is reflected along the horizontal axis, and the number of errors in a given read block is reflected along the vertical axis. As described earlier, in many modern memory technologies, read operations can interfere with data stored in addressed memory cells or this data can accumulate errors over time because of other sources of interference in this memory cell technology. Or the relationship of characteristics. Figure 3A shows that in a series of read operations, the number of errors detected in the addressed data can reach the upper limit of the error correction code (ECC) logic associated with the addressed data. If the upper limit reaches the number deployed by a memory system, the memory becomes unreliable.

Figure 3B shows a simplified schematic of what is going on in multiple reads. In Figure 3B, the series begins a stylized operation 30 (or write operation). Thereafter, a read operation 31 is performed on the data written in the stylization operation. A series of read operations 32, 33, 34, 35, 36, 37 with a time distribution interval of arbitrarily selected are then performed. In this example, a single bit error was detected while reading 32. This error correction code (ECC) logic can correct this error so the correct data is passed Send to the host. At the subsequent read 33, the same single bit error was detected. After a period of time, the next read 34, three bit errors were detected, including the original single bit error and the extra two bit errors. This error correction code (ECC) logic may be able to correct these three bit errors, or may exceed the upper limit of this error correction code (ECC) logic, if it has sufficient depth. Figure 3B shows that the same three bit errors are still detected when the next read 35. After a period of time, the next read 36, four bit errors were detected, including the original three bit errors and an additional one bit error. Similarly, the next read 37 still detects the same four bit errors. Thus, Figure 3B shows the number of errors accumulated during a series of read operations, as shown in Figure 3A.

Figure 4A is a diagram similar to Figure 3A, however, which is the result of using the techniques described herein. In particular, in a series of read operations after stylization, the program can be continuously continued without updating or overwriting the data without accumulating the error beyond the upper limit of the error correction code (ECC) logic.

Figure 4B shows a comparison chart similar to Figure 3B. In Figure 4B, the results of using the techniques described herein are shown in comparison with Figure 3B, which would encounter the same bit error condition as described in Figure 3B. This series begins with a stylized operation 40, after which a first read operation 41 is performed. A series of read operations 42, 43, 44, 45, 46, 47 are then performed. In this example, a single bit error is detected by Error Correction Code (ECC) logic upon reading 42. This error correction code (ECC) logic can correct this error, so the correct material is provided. In addition, an error correction table will be specifically described below, in which a content addressable memory is applied. (CAM), writes an address that includes the address data and identifies the detected error. At the next read 43, this error correction table is used to correct previously detected errors before applying them to error correction code (ECC) logic. Therefore, at the second read 43, no error is detected in the error correction code (ECC) logic. At the next read 44, two bit errors are detected, which are different from the ones that have been corrected using the error correction table. In this example, error correction code (ECC) logic can be used to correct the errors for these two bits, and two new items are generated for the two newly detected errors in the error correction table. At the next read 45, no errors were detected in the Error Correction Code (ECC) logic because the error correction table has been used to correct the errors of the two bits. Finally, a single bit error was detected while reading 46. This error can be corrected using Error Correction Code (ECC) logic and a new item will be generated in the error correction form. No error was detected at the next read 47. Thus, using the techniques described herein, even if a new error occurs, a series of read operations can continue without exceeding the upper limit of the error correction code (ECC) system.

Fig. 5 shows an intent of a block circuit 100 using the above-described error detection table. The integrated circuit 100 includes a memory array 200. An input/output buffer 201 includes circuitry for receiving and transmitting data and address signals and communicating with external devices such as a memory controller or a host processor. A control input/output block 202 includes circuitry for receiving and transmitting control signals for communicating with external devices, including, for example, wafer enable signals, write enable signals, and clock signals, and the like. A command decoder 203 is coupled to the input/output buffer 201 and the control input/output block 202, which detects and causes the execution of commands at the time of memory operation, including read commands and write commands. In some technologies The write commands include stylized and erase commands. This command decoder 203 is coupled to row (X) decoder 204 and column (Y) selector 205 to access this memory array 200. The sense amplifier 206 is coupled to the memory array 200 via a column selector 205. The integrated circuit 100 also has a controller 210.

The controller 210 can include one or more state mechanisms, scratchpad files, and other logic circuitry for operationally performing functions including reading and writing memory. The controller can be implemented using one or more proprietary logic circuits, a programmable gate array circuit, a programmable processor and its associated software, or a combination of the above. In some embodiments, a portion of the controller functions can be implemented outside of the integrated circuit 100, for example, hardware or software associated with the memory controller or host processor.

The integrated circuit 100 also includes an error correction code (ECC) layer 207, as shown in this example diagram, coupled to the input/output buffer 201. This error correction code (ECC) layer 207 includes error correction code (ECC) logic and buffers as shown in Figures 1 and 2, and provides an integrated error correction code (ECC) logic for the integrated circuit. It must be noted that in some applications, certain functions of the error correction code (ECC) layer 207 may be implemented outside of the integrated circuit 100, for example, hardware associated with the memory controller or host processor. Or software.

A error correction table 208 is also included in the integrated circuit 100. The error correction table 208 in this example is implemented using the error correction table 208. The input to table 208 includes the address of the address bit, which in this example includes the row address and column address output by command decoder 203. In addition, the input to table 208 also includes a bit address from the error correction code (ECC) layer 207 for detecting and correcting the erroneous address data. The error correction table 208 output is a match signal, which will One of the logic inputs labeled as Mutual Exclusions or Gates (XOR) is applied to this figure, which will merge the correction errors from the error correction table 208 with the data provided by the sense amplifier 206, thus dynamically correcting one with the table 208 Corresponding to the error in the location data of the project.

In an example implementation, each of the set of sense amplifiers 206 can be associated with a particular bit address in the address data. This table 208 can be logically or physically segmented and thus includes segments associated with each sense amplifier. This table 208 can also be configured to transmit its match signal for each segment. A mutex or gate can be associated with each sense amplifier that is coupled to a corresponding match signal from the table. In other examples, the addressed data from the sense amplifier 206 can be transmitted sequentially through the integration logic, which will apply the bit correction to the appropriate bit address.

Figure 6 shows a schematic diagram of the configuration of an error correction table 250 stored using a content addressable memory (CAM). The table shown in Figure 6 includes a plurality of items. This table 250 is a data structure stored in a content addressable memory (CAM), such that the input is compared with the content in each item, and the output of each item is logically ORed, like a symbol. A match signal is provided on line 252 as indicated by 251. Each item in this table includes a "correct/incorrect" flag FL indicating whether the corresponding item is being used and is currently correct or not. This FL flag is set by the logic in controller 210 or other logic in the integrated circuit when generating the entries for this table. Each item in this table includes a data address, which in this example contains the row and column addresses of each addressed data set. This data address can be used by the control logic in the controller or other logic circuits in the integrated circuit, using the data stored in the register of the command decoder 203, or in the column decoding. The data in the register of the device 204 and the row decoder 203 for. In addition, each item in this table includes a one-bit address to identify the error that will be corrected by this form. This bit address can be provided by the error correction code (ECC) logic of the error correction code (ECC) layer 207 of the device upon detection of an error.

This table 208 can contain one or more items for each block address to allow for multiple bit corrections for a series of reads. The size of this table can be chosen when designing this integrated circuit based on the cost of implementing the table (which will increase according to the size of the table) and the error rate performance characteristics expected by the device (eg, bit error rate BER).

This table can contain fewer items than the rows of data supplied by a particular sense amplifier in this array. Therefore, it may happen that the form is not enough. In this case, the controller 210 may include logic to decide whether to abandon the old project and use the newly generated project coverage. For example, the logic in the controller can identify block data (eg, pages) of the item with the most bit errors in the table. Items related to these pages can be set to be incorrect. When an item of a given material is set to be incorrect, the logic in controller 210 can generate a signal to perform an update in response to the affected page being immediately or when available resources are available. Alternatively, the logic in the controller can identify the page with the item with the least bit error in the table. Because it is assumed that subsequent reads of these pages are less likely to occur before the overlay, or that the error correction code (ECC) logic can still have the ability to update such errors on subsequent reads, the items associated with these pages can be Set to incorrect.

Figure 7 shows an integrated circuit 100 similar to Figure 5, in which like elements are referred to by like reference numerals and will not be described again. In the integrated circuit 101, the logic that integrates the error corrected using the table 208 with the data read via the sense amplifier 206 is labeled as a multiplexer, wherein the error value from the table 208 is provided as a multiplexer. First An input, while data from sense amplifier 206 is provided as a second input to multiplexer 219. The match signal MATCH from table 208 provides a selection input as multiplexer 219. In this mutual exclusion gate (XOR) embodiment, each sense amplifier in the group of sense amplifiers 206 that read the data can be paired with a multiplexer. The items in this table can be logically or physically segmented to provide a match signal to each multiplexer based on the detected bit address.

Both Figure 5 and Figure 7 show an integrated circuit embodiment including a memory array storing data and error correction codes (ECC) at addressable locations, including, for example, the use of error correction codes in the wafer. (ECC) logic previously determined at least one data location having one or more errors; a content addressable memory CAM comprising an item storing a previously determined address of at least one data location having one or more errors And placing logic between the memory array and the error correction code (ECC) logic data path to use the content addressable memory CAM to correct errors in the addressed data prior to using error correction code (ECC) logic.

Figure 8 is a flow chart showing the operation associated with a read operation using logic on integrated circuits 100, 101, including logic in controller 210, command decoder 203, and errors. Correction code (ECC) layer 207 and the like. The first step includes determining whether the integrated circuit receives a command (301)? This logic circuit, as indicated by the loop, waits to receive a command. In the next step, this logic determines the type of command received (302). For simplicity of description, if the command is not a read command, then the logic branches to perform other functions (312). If the command is a read command, then the logic causes access to the addressed data in the memory array (303). In addition, this logic causes access to this error correction table using the block address. (304). This logic determines whether the correct item for the addressed data is found in the table (305). If the decision is the correct one, the project from the form is integrated with the data to correct the addressed information. Thereafter, or if the correct item is not found in the table of step 305, the logic continues to supply the corrected addressing data to the error correction code logic. This error corrects the code logic and then outputs the corrected error check block (308). This logic determines if there are any corrected errors (309) in the error checking block, for example, by receiving a signal from Error Correction Code (ECC) logic. If there is a corrected error, a new item is generated in the table for the block location of the identified error (310). If there are no corrected errors in step 309, then this logic can branch to perform other functions (314).

Figure 9 is a flow diagram showing the operation associated with a write or update operation, which is implemented using logic on integrated circuits 100, 101, which includes logic circuitry in controller 210, command decoder 203, and Error Correction Code (ECC) layer 207 and the like. The first step includes determining whether the integrated circuit receives a command (351)? This logic circuit, as indicated by the loop, waits to receive a command. In the next step, the logic determines the type of command received (352). For the sake of simplicity, if the command is not a write or update command, the logic branches to perform other functions. If the command is a write or update command, then the logic causes access to the addressed data in the memory array (353). In addition, this logic causes access to this error correction table using the block address (354). This logic determines whether the correct item for the addressed data is found in the table (355). If the correct item is not found in the table in step 305, the process of managing and writing or updating the related form is completed. If the correct item is found in the block address, the item will be discarded (356) by setting it incorrectly or not, which can be achieved by setting the FL flag in Figure 5. Alternatively, this project can be done by erasing the entire project or Set to its default value to discard.

Figure 10 is a flow diagram showing the operation associated with generating a new item in a table, which is implemented using logic on integrated circuits 100, 101, which includes logic in controller 210, command decoder 203. And error correction code (ECC) layer 207 and so on. The first step includes determining whether the integrated circuit receives a command to generate a new item (381)? This logic, as indicated by the loop, waits to receive a command to generate a new item. Such a signal may be generated by an error correction code (ECC) layer 207 when one or more errors are detected in the addressed data. In the next step, this logic determines if there is space available in this table (382). If there is space available, then the flow proceeds to step 384 to write a new item. Whether there is space available can be determined by scanning the FL flag to see if there is any flag indicating that there is an unused item. If there is no space available, this logic decides to overwrite an item. One technique that decides to cover a project is to determine the block address with the fewest items in the table and select one of these items. Another technique for selecting a destination is to reset the item to be overwritten, causing the logic to rescan the table to find a flag indicating that there is an unused item.

The techniques described herein greatly improve the reliability of the memory by using error correction code (ECC) techniques. In addition, error correction code (ECC) efficiency can be optimized using an error correction table implemented by the application content addressable memory CAM. The hardware burden associated with this technology is very small and can be extended to the design of error correction code (ECC) systems that detect and correct only one or a few bits in the addressed data. Therefore, an error correction code (ECC) system designed to correct a single bit error can be used to correct many errors during a series of reads without the need to insert a write or update operation. When this error correction code (ECC) system is designed to correct multiple bit errors, the technical capabilities described here can be further extended to enable The ability to correct a large number of errors when reading a series.

The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above examples are merely exemplary and are not intended to limit the scope of the patent. For those skilled in the art, the related art can be modified and combined easily according to the scope of the following patent application.

20‧‧‧ memory

21‧‧‧Error Correction Code Logic

22‧‧‧ buffer

100, 101‧‧‧ integrated circuits

200‧‧‧Array

201‧‧‧Input/Output Buffer

202‧‧‧Control input/output

203‧‧‧Command decoder

204‧‧‧X decoder

205‧‧‧Y selector

206‧‧‧Sense Amplifier

207‧‧‧Error correction code layer

208‧‧‧Form (content can be addressed to memory)

210‧‧‧ Controller

Figure 1 shows a simplified block diagram of the combined memory system and error correction code (ECC) during a read operation.

Figure 2 shows a simplified block diagram of the combined memory system and error correction code (ECC) during a read operation.

Figure 3A shows how the upper limit of the error correction code (ECC) can be exceeded in a series of read operations in accordance with conventional techniques.

Figure 3B shows a simplified schematic of the errors that cannot be corrected in the multiple reads after a stylized operation.

Figure 4A shows the prevention of exceeding the upper limit of the error correction code (ECC) in a series of read operations in accordance with the teachings of the present invention.

Figure 4B shows a schematic diagram of how the technique of the present invention can be used to prevent exceeding the upper limit of the error correction code (ECC) in a multiple read after a stylized operation.

Figure 5 shows an intent of a block using the integrated circuit of the error detection table described above.

Figure 6 shows a schematic diagram of the configuration of an error correction table stored using a content addressable memory (CAM).

Figure 7 shows an intent to replace the integrated circuit with one of the error detection tables described above.

Figure 8 is a diagram showing the integrated circuit described here for control by one Flowchart related to the read operation of the logic execution.

Figure 9 is a flow diagram showing the integration circuit described herein for performing a write or update operation performed by control logic.

Figure 10 is a flow diagram showing the integrator circuit described herein producing the items in the error correction table described herein.

Claims (20)

A method of operating a memory storing data and error correction codes in an addressable location, comprising: storing a plurality of items in a table, the items being identifiable and storing one or more addressable addresses in the memory An error in the data in the location; reading data from a particular addressable location in the memory; and using the form to correct a stored in the particular addressable location before using the error correction code storing the data The error in this information. The method of claim 1, wherein the data stored in the particular addressable location comprises a data set comprising a plurality of bits, and the error correction code is calculated for the data set. The method of claim 1, wherein the form includes a data structure stored in a content addressable memory. For example, the method of claim 1 of the patent scope further includes clearing items related to the written materials in the form. For example, the method of claim 1 further includes updating the data in the memory, and clearing the items in the table related to the updated data. The method of claim 1, further comprising: after using the form to correct an error in the data, providing the data and the error correction code to the error correction code logic, and providing the error correction code logic After error checking data of. For example, the method of claim 1 is further included before the reading, using the error correction code logic to identify an error stored in the memory, and generating a recognized error in the table. project. For example, the method of applying for the scope of patent item 7 includes, if the form is already full, overwriting an existing item with the generated item. For example, the method of claim 8 of the patent scope further includes selecting one of the existing items using parameters determined by the items in the table. An integrated circuit comprising: a memory array for storing data and error correction codes at addressable locations, including using error correction codes to determine data stored in one or more locations with one or more errors; A table memory stores a table including a plurality of items for use in an addressable location determined to store data having one or more errors; and a logic associated with the memory Executing in the reading of a particular addressable location, the form is used to correct an error in the material stored in the particular addressable location prior to using the error correction code corresponding to the material. The integrated circuit of claim 10, wherein the data stored in the specific addressable location comprises a data set comprising a plurality of bits, and the error correction code is calculated for the data set. The integrated circuit of claim 10, wherein the table memory comprises a content addressable memory. For example, the integrated circuit of claim 10 includes a logic for clearing items in the table related to the materials to be written. For example, the integrated circuit of claim 10 of the patent application further includes logic for clearing the item corresponding to the updated material in response to the update of the memory. For example, the integrated circuit of claim 10 further includes an error correction code logic in the integrated circuit, and a logic for generating a destination logic in the table when the error correction code logic recognizes an error. . For example, the integrated circuit of claim 10 further includes: an error correction code logic is provided in the integrated circuit; and the corrected data using the table and the error correction code associated with the data are provided to the error Correct the code logic and use the error correction code logic to provide logic for the error checked data. For example, the integrated circuit of claim 10 includes: an error correction code logic in the integrated circuit, and logic for generating an item in the table when the error correction code logic recognizes an error, and Use the parameters determined by the items in the table to select the logic for replacing one of the existing items. The integrated circuit of claim 10, wherein the logic for correcting an error using an item in the table includes a mutual exclusion or gate having a first input and the table An output connection and a second input are coupled to an output of a sense amplifier of the array. The integrated circuit of claim 10, wherein the logic for correcting an error using an item in the table comprises a multiplexer having a first input coupled to an output of the table, and a A second input is coupled to an output of a sense amplifier of the array; and a select control signal coupled to an output of the table. An integrated circuit comprising: a memory array for storing data and error correction codes at addressable locations, including at least one location determined by the error correction code having one or more errors; An addressable memory, comprising: an item for storing an address corresponding to the at least one location of the data determined to have one or more errors; error correction code logic; and a logic disposed on the memory array The error corrects a data path between the code logic to correct an error in the addressed data using the content addressable memory prior to using the error correction code logic.