JP2007141364A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which suppresses the extension of access time for reading desired data with respect to an address input. <P>SOLUTION: The semiconductor memory device 100 includes: a ROM circuit 1 for storing necessary memory data and parity data for correcting errors of the memory data; a defective address storage circuit 2 for storing a defective address which is an address of an error-determined memory data among the memory data; an ECC circuit 5 for correcting the error of the error-determined memory data and generating saving data relevant to the defective address, based on the parity data; a data holding circuit 6 for storing the saving data; an address matching circuit 7 for comparing an input address with the defective address; and a switching circuit 9 for switching between the data output of the ROM circuit 1 and the data output of the data holding circuit 6. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device that relieves data in a ROM (Read Only Memory) circuit determined to be an error.

  2. Description of the Related Art Conventionally, some semiconductor memory devices that store desired data include an ECC (Error Correcting Code) circuit that has a function of checking and correcting errors in stored data.

  In this conventional semiconductor memory device, the ECC circuit generates an error correction bit of input write data, and the error correction bit is stored in the memory array together with the write data. When data is read, the ECC circuit checks and corrects the data based on the data read from the memory array and the error correction bit, and outputs correct data (see, for example, Patent Document 1).

However, depending on the above-described prior art, the ECC circuit needs to operate for error correction when reading data, and a delay occurs due to the data signal passing through the ECC circuit, so that the data for reading desired data can be read. There was a problem of long access time.
Japanese Patent Laid-Open No. 8-31196 (page 3-5, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can suppress an increase in access time for reading desired data in response to an address input.

A semiconductor memory device according to one embodiment of the present invention includes:
ROM circuit in which necessary memory data and parity data for error correction of the memory data are stored;
A defective address storage circuit that stores a defective address that is an address of the memory data determined to be an error in the memory data;
An ECC circuit that corrects an error of the memory data determined to be an error based on the parity data and generates repair data corresponding to the defective address;
A data holding circuit for storing the relief data generated by the ECC circuit;
An address matching circuit for comparing the input address inputted for reading the memory data and the defective address;
According to the comparison of the address matching circuit, when the input address and the defective address match, the relief data corresponding to the defective address is output, and when the input address does not match the defective address, A switching circuit that switches between the data output of the ROM circuit and the data output of the data holding circuit so as to output the memory data corresponding to the input address;
It is characterized by having.

  According to the semiconductor memory device of one embodiment of the present invention, it is possible to provide a semiconductor memory device capable of suppressing an increase in access time for reading desired data with respect to an address input.

  The semiconductor memory device according to the embodiment of the present invention, for example, corrects data that has been determined as an error among data stored in a ROM circuit that is a nonvolatile memory circuit, and corrects the error-corrected data ( Relief data) is held in the data holding circuit, and in response to the address input, normal data is output from the ROM circuit or error-corrected data (relief data) is appropriately output from the data holding circuit, and the data read access time It is possible to suppress the increase in the length.

  Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a main part of a semiconductor memory device according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the semiconductor memory device 100 stores necessary memory data that should be stored in the memory data area 1a and stores parity data for error correction of the memory data in the parity data area 1b. ROM circuit 1 that has been read out, a defective address storage circuit (Fuse Box) 2 that stores a defective address (specified by fuse data) that is an address of memory data determined to be an error in the memory data, and this defective address storage circuit 2 The fuse data holding circuit 3 that holds the fuse data output from the memory and whether or not there is memory data determined as an error based on the fuse data output from the fuse data holding circuit 3, that is, whether relief is necessary And a repair determination circuit 4 for determining whether or not.

  Further, the semiconductor memory device 100 performs error correction on the memory data determined to be an error based on the parity data and generates the repair data corresponding to the defective address, and the repair data generated by the ECC circuit 5. The data holding circuit 6 to be stored, the address matching circuit 7 for comparing the input address inputted for reading the memory data with the defective address held by the fuse data holding circuit 3, and the comparison result of the address matching circuit 7 are held. A switching holding circuit 8 and a switching circuit 9 that switches between the data output of the ROM circuit 1 and the data output of the data holding circuit 6 based on the output of the switching holding circuit 8 are provided.

  The memory data area 1a of the ROM circuit 1 has an N-bit ROM input / output (I / O). On the other hand, the number of parity bits is defined so that a desired error correction of the memory data can be performed, and the parity area 1b Has parity input / output (I / O) of M (≦ N) bits.

  The defective address storage circuit 2 is composed of a non-volatile memory circuit such as a metal fuse (Metal-Fuse) or an anti-fuse (Anti-Fuse) which is normally in an insulated state and is connected by applying a write voltage. Yes. The defective address storage circuit 2 stores a defective address of memory data in the ROM circuit 1 in which a failure is detected by an external failure detection circuit (not shown). For example, when the defective address storage circuit 2 is a metal fuse, the metal fuse is melted and stored as fuse data.

  The repair determination circuit 4 outputs the result of determining whether or not the repair is necessary to the ROM circuit 1. When the repair is necessary, the ROM circuit 1 outputs the memory data and the parity data to the ECC circuit 5. To do.

  The ECC circuit 5 stores the memory data (normal output N) when the power is turned on, that is, after the power is turned on to the system of the semiconductor memory device 100 and there is an address input for reading the memory data stored in the ROM circuit 1. Bit) and parity data (parity output M bits) are received from the ROM circuit 1, the memory data is error-corrected based on the parity data, and repair data corresponding to the defective address is generated. Note that the operation of generating relief data by the ECC circuit 5 is performed only once at the time of power-on.

  As described above, the data holding circuit 6 stores N-bit relief data generated by the ECC circuit 5. The data holding circuit 6 is composed of a volatile memory circuit such as a data flip-flop (D-F / F) or SRAM (Static Random Access Memory).

  Here, for example, the ECC circuit 5 and the data holding circuit 6 can be constructed as either a hard macro or a soft macro by defining them as an external circuit or a built-in circuit. “External” refers to the functions of IP (Intellectual Property) on the SoC (System On a Chip) chip, using the logic area inside the chip. If you are. “Built-in” refers to a case where a SoC chip realizes a desired function internally with reference to the mounted IP.

  The switching circuit 9 outputs the relief data corresponding to the defective address when the input address and the defective address match by the comparison of the address matching circuit 7, and when the input address and the defective address do not match, The switching operation is performed so that the memory data corresponding to the input address is output. The switching circuit 9 is constituted by a multiplexer (MUX), for example.

  As described above, in the normal operation of reading data, when reading the memory data, only the ROM circuit 1 is accessed, and the access time is prevented from passing through the ECC circuit 5.

  Since the normal read path and the repaired read path are designed separately, the address matching circuit 7 can switch the read path to read the data in the shortest path, thereby shortening the access time. It becomes possible to do.

  Here, the operation including the ECC processing of the semiconductor memory device 100 having the above configuration will be described below.

  FIG. 2 is a flowchart for explaining the operation of the ECC process of the semiconductor memory device according to the first embodiment which is an aspect of the present invention.

  As shown in FIG. 2, the initial state is a state in which the system of the semiconductor memory device 100 is turned off. First, the system is turned on (step S1).

  Next, in order to set the logic of the system of the semiconductor memory device 100 back to the initial and confirm, this system is reset (step S2), and after this step S2, the reset of the system is released (step S3).

  Next, the fuse data is transferred from the defective address storage circuit 2 to the fuse data holding circuit 3 (step S4).

  Next, the repair determination circuit 4 determines whether or not the memory data stored in the ROM circuit 1 needs repair based on the fuse data held by the fuse data holding circuit 3 (step S5).

  If it is determined in this step S5 that the repair is necessary, the ROM circuit 1 receives the output of the repair determination circuit 4, reads out the memory data and the parity data, and outputs them to the ECC circuit 5 (step S6). ).

  After this step S6, the ECC circuit 5 performs error correction based on the input memory data and parity data, and generates repair data corresponding to the defective address (ECC processing). (Step S7).

  After this step S7, the data holding circuit 6 stores the relief data generated by the ECC circuit 5. (Step S8).

  After this step S8, or when the relief determination circuit 4 determines that no relief is required in step S5, a normal operation of reading data based on the address input is executed (step S9), and the semiconductor memory device 100 A series of operations is completed.

  Here, the normal operation (step S9) for reading data based on the address input after the ECC processing will be described in detail.

  FIG. 3 is a flowchart showing a normal operation after the ECC process of the semiconductor memory device according to the first embodiment which is an aspect of the present invention.

  As shown in FIG. 3, first, in order to read the memory data stored in the ROM circuit 1, an address is input to the address matching circuit 7 from an external device, for example (step S91).

  Next, the address matching circuit 7 compares the defective address held in the fuse data holding circuit 3 with the inputted address, and outputs the comparison result to the switching holding circuit 8 (step S92).

  If the input address and the defective address do not match according to the comparison of the address matching circuit 7, the ROM circuit 1 receives the comparison result and outputs the memory data corresponding to the input address, and the switching circuit 9 The memory data output from the ROM circuit 1 is output as a data output based on the comparison result held in the switching holding circuit 8 (step S93).

  On the other hand, when the input address and the defective address coincide with each other by the comparison of the address matching circuit 7, the switching circuit 9 selects the repair data corresponding to the defective address based on the comparison result held in the switching holding circuit 8. The output is switched so as to be output (step S94).

  The relief data corresponding to the defective address held in the data holding circuit is output as output data by the switching operation of the switching circuit 9 in step S94 (step S95).

  As described above, according to the semiconductor memory device of the present embodiment, the error-corrected data (relief data) is retained while correcting the data determined to be an error among the data stored in the ROM circuit. In response to address input, normal data is appropriately output from the ROM circuit or error-corrected data (relief data) is output from the data holding circuit to suppress an increase in data read access time. can do.

It is a top view which shows the structure of the principal part of the semiconductor memory device based on Example 1 which is 1 aspect of this invention. 6 is a flowchart for explaining an operation of the semiconductor memory device according to the first embodiment which is an aspect of the present invention; 6 is a flowchart showing a normal operation after ECC processing of the semiconductor memory device according to the first embodiment which is an aspect of the present invention;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ROM circuit 1a Memory data area 1b Parity data area 2 Defective address storage circuit 3 Fuse data holding circuit 4 Relief judgment circuit 5 ECC circuit 6 Data holding circuit 7 Address matching circuit 8 Switching holding circuit 9 Switching circuit 100 Semiconductor memory device

Claims (5)

ROM circuit in which necessary memory data and parity data for error correction of the memory data are stored;
A defective address storage circuit that stores a defective address that is an address of the memory data determined to be an error in the memory data;
An ECC circuit that corrects an error of the memory data determined to be an error based on the parity data and generates repair data corresponding to the defective address;
A data holding circuit for storing the relief data generated by the ECC circuit;
An address matching circuit for comparing the input address inputted for reading the memory data and the defective address;
According to the comparison of the address matching circuit, when the input address and the defective address match, the relief data corresponding to the defective address is output, and when the input address does not match the defective address, A switching circuit that switches between the data output of the ROM circuit and the data output of the data holding circuit so as to output the memory data corresponding to the input address;
A semiconductor memory device comprising:   The ECC circuit corrects an error of the memory data determined to be an error based on the parity data when power is turned on to generate repair data corresponding to the defective address, and the generated repair data is stored in the data holding circuit. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is stored.   3. The semiconductor memory device according to claim 2, wherein the operation of generating the relief data by the ECC circuit is only once at the time of power-on.   4. The semiconductor memory device according to claim 1, wherein the data holding circuit is configured by a data flip-flop (D-F / F) or an SRAM (Static Random Access Memory).   5. The semiconductor memory device according to claim 1, wherein the defective address storage circuit is constituted by a metal fuse or an antifuse.

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