JP2007141312A - Read-out circuit of semiconductor memory apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a read-out circuit of a semiconductor memory apparatus in which read-out operation speed can be increased and the number of reference cells for read-out operation can be decreased, in a multi-level type semiconductor memory apparatus. <P>SOLUTION: The circuit is the read-out circuit of the semiconductor memory apparatus in which a memory cell current is supplied to a selection memory cell selected as a read-out object out of a plurality of memory cells included in a memory cell array from a load circuit through a bit line, read-out voltage is generated by current-voltage-converting a read-out current flowing in the selection memory cell in accordance with a memory state of the selection memory cell, and both voltage are compared by a differential type circuit of which the differential input is read-out voltage and reference voltage, The differential type circuit is constituted so that a circuit property for input of a read-out voltage side can be varied in accordance with the number of memory states being able to take. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device such as a flash EEPROM using a multi-value technology capable of storing data of 2 bits or more in one memory cell.

  In general, a read circuit of a semiconductor memory device supplies a current to a memory cell in which information is stored, and compares a current flowing through the memory cell (memory cell current) with a reference current (reference current). The information written in the memory cell is read by determining whether the memory cell current is larger or smaller than the reference current. As described above, the method of reading information by comparing the memory cell currents is called a current sensing method.

  For example, in a so-called binary semiconductor memory device in which 1-bit information is stored in one memory cell, as shown in FIG. 8B, the memory cell current flowing through the memory cell is large. Since there are two states (corresponding to information “1”) and a small state (corresponding to information “0”), by setting the value of the reference current to an intermediate value between the two states, 1 Bit information can be read. Actually, in the current sense system, each of the memory cell current and the reference current is subjected to current-voltage conversion, and the respective voltages are compared.

  In recent years, in order to increase the storage capacity and reduce the manufacturing cost of a semiconductor chip, a multi-value type semiconductor memory device capable of storing information of 2 bits or more in one memory cell has been manufactured.

For example, in a multilevel semiconductor memory device that stores 2-bit information in one memory cell, there are four states that the memory cell current can take as shown in FIG. By setting three types of reference currents between the data area distributions of the respective currents, 2-bit information can be read. Similarly, in a multi-level semiconductor memory device that stores n-bit information in one memory cell, there are 2 ⁿ types of states that can be taken by the memory cell current value, and the reference current value is (2 ⁿ −1). Information can be read by setting the type.

  As can be seen from FIGS. 8A and 8B, when reading 2-bit data, it is necessary to compare three kinds of currents. In general, in a multivalued semiconductor memory device, a binary value is used. Compared with a semiconductor memory device of a type, it is necessary to perform a large number of current comparisons in order to extract information stored in memory cells. For this reason, there is a possibility that the read time is delayed in the multi-value type semiconductor memory device.

  In view of these circumstances, several methods have been proposed for reading data from a multilevel semiconductor memory device. As one of them, first, a time division sensing method is disclosed in which current comparison is performed based on a reference current having an intermediate value, and current comparison is performed for another state according to the result (for example, Patent Document 1). reference).

  Hereinafter, with respect to this time-division sensing method, an operation when reading data of the multilevel semiconductor memory device storing 2-bit information shown in FIG. 8A will be described with reference to FIG.

  FIG. 9 is a circuit diagram showing a schematic configuration example of a time division sensing read circuit J100 in a conventional semiconductor memory device. In FIG. 9, the read circuit J100 using the time-division sensing method obtains a read current (memory cell current) by applying a voltage to the drain (drain electrode) of the selected memory cell J7 that is a memory cell from which data is read. A current load circuit J1 and a current load circuit J2 for obtaining any one of the three reference cells J810 to J830 are provided. Here, a current mirror type circuit configuration is illustrated as the load current circuit, but the configuration of the current load circuit is not particularly limited.

  A sense line J9 is connected between the drain of the selected memory cell J7 and the current load circuit J1, and a reference line J10 is connected to the current load circuit J2. The NMOS transistors J131 and J132 connected to the sense line J9 and the reference line J10 are for limiting the drain voltage of the selected memory cell J7 and the reference cell, and apply a bias voltage generated in the internal circuit to the gate. Accordingly, an object of the present invention is to suppress deterioration of retained data due to voltage application at the time of reading by setting the drain voltages of the selected memory cell J7 and the reference cell J8 below a certain value.

  Several stages of NMOS transistors for selecting a bit line are inserted between the NMOS transistors J131 and J132 and the selected memory cell J7 and reference cell J8. The number of stages of these bit line selection transistors is determined by the storage capacity of the storage device, the array configuration of the memory cell array, and the like.

  The sense line J9 and the reference line J10 are connected to an input part of a sense amplifier J3 for amplifying and outputting a voltage difference between the sense line J9 and the reference line J10. The output section of the sense amplifier J3 is connected to a first data latch circuit J4 that latches the first sense result and a second data latch circuit J5 that latches the second sense result. The output data J11 from the first data latch circuit J4 is connected to the reference selection circuit J6, and the reference selection circuit J6 receives the reference cells J810 to J830 based on the output data J11 from the first data latch circuit J4. It is configured to be switched and connected to the reference line J10.

  Next, a data read operation from the selected cell J7 in the time-division sensing read circuit J100 configured as described above will be described.

  First, in order to perform the first read operation, the reference cell selection circuit J6 selects the reference cell J810 and applies an appropriate voltage to the gate (gate electrode) and the drain (drain electrode) of the reference cell J810. A reference current flowing through the reference cell J810 is generated. A reference voltage is generated on the reference line J10 due to the current balance between the reference current and the PMOS transistor constituting the current load circuit J2.

  On the other hand, by applying an appropriate voltage to the gate (gate electrode) and drain (drain electrode) of the selected cell J7, a memory cell current flowing through the selected cell J7 is generated. A reference voltage generated on the reference line J10 is applied to the gate of the PMOS transistor that constitutes the current load circuit J1. As a result, the current load circuits J1 and J2 behave as current mirror circuits. That is, the current capability of the current load circuit J1 is controlled by the selected reference cell J810 and the current load circuit J2. Thus, a sense voltage (read voltage) is generated on the sense line J9 due to the current balance between the current load circuit J1 whose current capability is controlled and the selected cell J7 whose current driving capability changes depending on the storage state.

  The potential difference between the sense voltage and the reference voltage generated in this way is amplified and output by the sense amplifier J3, and the output result is stored in the first data latch circuit J4 as the first read result. Here, the reference current of the reference cell J810 selected by the reference cell selection circuit J6 at the time of the first reading is the data region “01” and “10” among the three reference currents shown in FIG. The reference current value “M” is obtained. In general, the reference cells J810 to J830 have the same structure as that of the memory cell so that an appropriate reference current can be obtained, and the characteristics can be obtained by strictly adjusting the threshold voltage.

  Subsequently, the reference cell selection circuit J6 switches the reference cell J810 to the reference cell J820 or the reference cell J830 based on the first read result stored in the first data latch circuit J4. At this time, when the first read result stored in the first data latch circuit J4 is “0”, the reference cell J820 is switched, and when the first read result is “1”, the reference is read. Switch to cell J830.

  Here, the reference cell J820 is for obtaining a reference current value “H” between the data areas “00” and “01” among the three reference currents shown in FIG. The cell J830 is for obtaining a reference current value “L” between the data areas “10” and “11”.

  Thereafter, the second read operation is performed similarly to the first read operation, and the second read result is stored in the second data latch circuit J5. As described above, 2-bit data stored in one memory cell J7 can be obtained. Similarly, when n-bit information is stored in one memory cell, the n-bit information can be read by performing the read operation at least n times by using the time-division sensing method.

  According to this time-division sensing method, since multi-bit information can be read out by at least one sense amplifier, it is possible to minimize the chip area occupied by the sense circuit, current consumption required instantaneously, and the like. It is.

  Next, the principle of converting the memory cell current and the reference current when using this read circuit into a sense voltage and a reference voltage will be described with reference to FIG. In the following description, the expression voltage-current characteristic is used, which all represents the characteristic of the current flowing between the drain and source with respect to the voltage applied between the drain and source of the transistor.

  In the case of the time-division sensing method, first, the reference current value between the data regions “01” and “10” among the three reference currents shown in FIG. 8A by the reference cell selection circuit J6 in the first read operation. The reference cell J810 that obtains “M” is selected. The voltage-current characteristic of the reference cell J810 is as shown by I (refmj) as shown in FIG. Further, the voltage-current characteristic of the PMOS transistor J2, which is the current load circuit of the reference cell J8, becomes I (pj2). Accordingly, the reference voltage output to the reference line J10 during the first read operation is V (refmj) determined by the stable points (intersections in the figure) of the two currents I (refmj) and I (pj2). On the other hand, as shown in FIG. 9, since the PMOS transistors J1 and J2 are configured to have the same characteristics by the current mirror operation, the voltage-current characteristics of the PMOS transistor J1 which is a current load circuit is I (pj1_m). It becomes like this. Here, I (pj1_m) is characterized by a characteristic that it intersects with an intersection of I (refmj) of the reference cell J810 and I (pj2) of the PMOS transistor J2 which is a current load circuit of the reference cell.

  On the other hand, the voltage-current characteristics when the selected memory cell is in the states of Data 00, 01, 10, and 11 in FIG. 8A are I (j00), I (j01), and I (j10) in FIG. , I (j11) respectively. As shown in FIG. 8A, when there are a plurality of memory cells, the memory cell group has a distribution width in each data state. Here, a voltage-current characteristic of an intermediate value in each state is taken as an example.

  The sense voltage of the sense line J9 is determined by the stable points of the PMOS transistor J1 and the memory cell J7. That is, the outputs V (mj00) of I (pj1_m) and I (j00), I (pj1_m) and I (j01), I (pj1_m) and I (j10), I (pj1_m) and I (j11) in FIG. ), V (mj01), V (mj10), or V (mj11) is output as a sense voltage.

  In this way, the reference voltage is output to the reference line J10, the sense voltage is output to the sense line J9, and they are input to the sense amplifier J3. As shown in FIG. 10A, the sense voltages V (mj00) and V (mj01) of Data00 and 01 are higher than the reference voltage V (refmj) of the reference cell J810, and the sense voltage V (mj10) of Data10 and 11 is used. , V (mj11) is lower than the reference voltage V (refmj). Here, it is assumed that the sense amplifier J3 outputs 0 if the sense voltage is higher than the reference voltage, and conversely the sense amplifier J3 outputs 1 if the sense voltage is lower than the reference voltage. . Therefore, in the first read operation, 0 is output if the selected memory cell is in the Data00, 01 state, and 1 is output if it is in the Data10, 11 state. In this manner, the memory cell state can be limited from the four states to the two states by the first read operation. The data output in the first read operation is held by the first data latch circuit J4 and output as output data J11.

  The output data J11 is input to the reference cell selection circuit J6. This is because the result of the first read operation is reflected to select the reference cell used during the second read operation. When the output in the first read operation is 0, that is, when the data of the selected memory cell is 00 or 01, the reference cell selection circuit J6 uses the Data00 to determine these two states in the second read operation. And the memory cell current between Data01, that is, the reference cell J820 in the H state of FIG. 8A is selected. On the other hand, when the output of the first read operation is 1, that is, when the data of the selected memory cell is 10 or 11, in the second read operation, in order to determine the two states, an intermediate between Data 10 and Data 11 The memory cell current, that is, the reference cell J830 in the L state in FIG. 8A is selected. As shown in FIG. 9, reference cell selection is performed by reference cell selection signals J811, J821, and J831. The reference cell selection circuit J6 selects J811 during the first read operation, and selects J821 when the result of the first read operation is 0 and J831 when the result is 1 during the second read operation.

  Next, the operation during the second read operation will be described. First, a case where the result of the first read operation is “0” will be described.

  When the result of the first read operation is “0”, the reference cell J820 in the H state in FIG. 8A is used in the second read operation. As shown in FIG. 10B, the voltage-current characteristic of the reference cell J820 is as I (refhj). The reference cell J820 in the H state has less current flow than the reference cell J810 in the M state used in the first read operation, but the voltage-current of the PMOS transistor J2 that is the current load circuit of the reference cell The characteristic is I (pj2) as in the first read operation. Therefore, the reference voltage output to the reference line J10 during the second read operation is V (refhj) determined by the stable points (intersections in the figure) of the two currents I (refhj) and I (pj2). . On the other hand, since the PMOS transistors J1 and J2 are configured to have the same characteristics by the current mirror operation, the voltage-current characteristics of the PMOS transistor J1, which is a current load circuit, are I (pj1_h). Here, I (pj1_h) indicates a characteristic that intersects with an intersection of I (refhj) of the reference cell J820 and I (pj2) of the PMOS transistor J2 that is a current load circuit of the reference cell.

  Further, since the state of the selected memory cell when the result of the first read operation is “0” is either Data00 or Data01, the voltage-current characteristic of the memory cell is I ( j00) and I (j01) only need to be considered. That is, only the output by I (pj1_h) and I (j00), I (pj1_h) and I (j01) in FIG.

  When the selected memory cell is Data00, the voltage-current characteristic indicates I (j00) in FIG. 10B, and the sense voltage is the voltage of the PMOS transistor J1 which is a current load circuit indicated by I (pj1_h) − V (hj00), which is a stable point with respect to the current characteristics, is output. On the other hand, when the selected memory cell is Data01, the voltage-current characteristic indicates I (j01) in FIG. 10B, and the sense voltage of the PMOS transistor J1 which is a current load circuit indicated by I (pj1_h). V (hj01) which is a stable point with the voltage-current characteristic is output. As shown in FIG. 10B, the sense voltage V (hj00) of Data00 is higher than the reference voltage V (refhj), and the sense voltage V (hj01) of Data01 is lower than the reference voltage V (refhj). . Here, the sense amplifier J3 is configured to output 0 if the sense voltage is higher than the reference voltage, and conversely, if the sense voltage is lower than the reference voltage, the sense amplifier J3 outputs 1. If it is in the state of Data00, 0 is output. Conversely, if it is in the state of Data01, 1 is output.

  As a result, when the selected memory cell is Data00, the result of the first read operation is 0, the result of the second read operation is 0, and when the selected memory cell is Data01, the result of the first read operation is 0. The result of the second read operation is 1, and information can be read correctly.

  Next, a case where the result of the first read operation is “1” will be described.

  When the result of the first read operation is “1”, the reference cell J830 in the L state in FIG. 8A is used in the second read operation. As shown in FIG. 10C, the voltage-current characteristic of the reference cell J830 is I (refflj). The reference cell J830 in the L state flows more current than the reference cell J810 in the M state used in the first read operation, but the voltage-current of the PMOS transistor J2 that is the current load circuit of the reference cell The characteristic is I (pj2) as in the first read operation. Therefore, the reference voltage output to the reference line J10 during the second read operation is V (refflj) determined by the stable points (intersections in the figure) of the two currents I (refflj) and I (pj2). . On the other hand, since the PMOS transistors J1 and J2 are configured to have the same characteristic by the current mirror operation, the voltage-current characteristic of the PMOS transistor J1 which is a current load circuit is as I (pj1_l). Here, I (pj1_l) indicates a characteristic that intersects with an intersection of I (reflj) of the reference cell J830 and I (pj2) of the PMOS transistor J2 that is a current load circuit of the reference cell.

  Further, since the state of the selected memory cell when the result of the second read operation is “1” is either Data 10 or Data 11, the voltage-current characteristics of the memory cell are I ( Only j10) and I (j11) need be considered. That is, only the output by I (pj1_l) and I (j00), I (pj1_h) and I (j01) in FIG.

  When the selected memory cell is Data10, the voltage-current characteristic indicates I (j10) in FIG. 10C, and the sense voltage is the voltage of the PMOS transistor J1 which is a current load circuit indicated by I (pj1_l) − V (lj10) which is a stable point with the current characteristic is output. On the other hand, when the selected memory cell is Data11, the voltage-current characteristic indicates I (j11) in FIG. 10C, and the sense voltage of the PMOS transistor J1 which is a current load circuit indicated by I (pj1_l). V (hj11), which is a stable point with the voltage-current characteristic, is output. As shown in FIG. 10C, the sense voltage V (lj10) of Data10 is higher than the reference voltage V (refflj), and the sense voltage V (lj11) of Data11 is lower than the reference voltage V (refflj). . Here, the sense amplifier J3 is configured to output 0 if the sense voltage is higher than the reference voltage, and conversely, if the sense voltage is lower than the reference voltage, the sense amplifier J3 outputs 1. If it is in the state of Data10, 0 is output. Conversely, if it is in the state of Data11, 1 is output.

  As a result, when the selected memory cell is Data 10, the result of the first read operation is 1, and the result of the second read operation is 0. When the selected memory cell is Data 11, the result of the first read operation is 1. The result of the second read operation is 1, and information can be read correctly.

  Next, the operation of the readout circuit J100 will be described along the timing of control pulses input to the readout circuit J100. Actually, a read operation is performed by inputting an address or a chip control signal to the semiconductor memory device. When a read operation is started, an address signal decoding process for selecting a memory cell corresponding to a specified address from a plurality of memory cell groups arranged in a grid is executed in the semiconductor memory device. Various control pulses are generated in order to efficiently operate various circuits in the semiconductor memory device. Of these control pulses, only typical pulses for controlling the read circuit J100 will be described here.

  Here, FIG. 11 shows timing waveforms of the control pulse, the voltage level of the sense line J9, and the voltage level of the reference line J10 input to the read circuit J100. The read operation of the read circuit J100 performs a series of precharge, bit line drive, sense amplifier control, and data latch operations according to the number of bits of the memory cell. Therefore, for example, when 2 bits of data can be held in one memory cell, it is necessary to perform these series of read operations twice. When n bits of data can be held, these series of read operations are performed. n times are required. Each operation will be described in order below.

  First, when the first precharge control pulse is generated, the read circuit J100 keeps the bit line connected to the memory cell constant for the memory cell corresponding to the address input to the semiconductor memory device. The operation to raise the voltage is performed. This period is called a first precharge period. In order to perform this operation, as shown in FIG. 12, the read circuit J100 may be provided with a precharge circuit J14 and a bit line equalizing transistor J15. The precharge circuit J14 is used to rapidly charge the bit line having a large load when the bit line load is large and greatly affects the access time with respect to the current supply capability of the current load circuits J1 and J2 for reading. The The equalizing transistor J15 is used to make the voltage level constant when precharging the bit lines of the selected memory cell and the reference cell. In terms of timing, there is no problem with the control timing of the precharge circuit J14 and the equalizing transistor J15 at the same time. Therefore, the same control pulse is input here, but in order to control each individually, individual control pulses are used. You may enter it.

  Between the end of the first precharge control pulse and the generation of the first sense control pulse, the sense line J9 and the reference line J10 are connected to the memory cell and current load circuit shown in FIG. And charging / discharging is performed toward the voltage level of the stable point of a reference cell and a current load circuit. This period is called a first bit line driving period. For example, if the sense amplifier J3 is a differential amplifier circuit such as a current mirror circuit, an erroneous determination may occur due to the offset of the sense amplifier if the voltage level between the sense line and the reference line does not exceed a certain level. . Of course, if the voltage level of the sense line and the reference line is more than a certain level while the sense amplifier J3 is operating, a correct determination can be finally made. However, at this time, current consumption and output due to charge / discharge of the sense amplifier output There is a risk of causing a time delay for inversion. On the other hand, if the sense amplifier J3 is a latch type sense amplifier, the sense amplifier output is fixed at the same time as the generation of the sense control pulse, and there is a problem that data cannot be determined thereafter. Accuracy is required.

  When the first sense control pulse after the first bit line driving period is generated, the sense amplifier J3 compares the voltage levels of the sense line and the reference line and outputs data. This period is called a first sense period. During the sensing period, the sense data is output from the sense amplifier J3. Until the sense data latch release pulse is generated, the first data latch circuit J4 and the second data latch circuit J5 store the previously read sense data. Alternatively, when the data latch circuit is initialized at the time of reading, the initialization data is held, and the sense data is not output from the reading circuit J100. Thereafter, when a sense data latch release pulse is generated in a state where the second read determination pulse is not generated, the first sense data is output from J11 via the first data latch circuit J4, and the output system circuit and reference cell Input to the selection circuit J6. When the sense data latch release pulse ends, the first data latch circuit J4 holds the data from the sense amplifier J3, and the output J11 does not change even if the output of the sense amplifier J3 subsequently changes. Thereafter, the sense control pulse ends, and the first read operation ends.

  Thereafter, when the second read determination pulse is generated, the read circuit J100 performs the second read operation. In the second read, the reference cell selection circuit J6 reflects the result of the first read, that is, the first data output J11, and switches the reference cell from the M state to the H state or the L state.

  When the second reading is started, a precharge control pulse is generated again. This period is called a second precharge period. In this period, the bit line that has been charged / discharged in the first read is held again at a constant voltage level before driving the bit line, so that there is no difference between the first read operation and the second read operation. Is the purpose. At this time, using the precharge circuit J14 and the equalizing transistor J15 in the same manner as in the first precharge period, the bit line is driven in a shorter time than when the memory cell and the current load circuit or the reference cell and the current load circuit alone are driven. Precharge is possible.

  Between the end of the second precharge control pulse and the generation of the second sense control pulse, the sense line J9 and the reference line J10 are memory cells shown in FIG. 10B or 10C from the precharge voltage level. And charge and discharge toward the voltage level at the stable point of the reference load cell and the current load circuit. This period is called a second bit line driving period. The purpose of this period is the same as that of the first bit line driving period. Since the reference cell is switched from the M state to the H state or the L state at the time of the second reading, if the H state is selected for the reference cell, the voltage level of the reference line is relative to the first voltage level. If the L state is selected, the voltage level of the reference line is slightly lower than the first voltage level.

  When the second sense control pulse after the second bit line driving period is generated, the sense amplifier J3 compares the voltage levels of the sense line J9 and the reference line J10 and outputs data. This period is called a second sense period. During the sense period, sense data is output from the sense amplifier J3, but until the sense data latch release pulse is generated, the second data latch circuit J5 uses the previously read sense data or the data latch circuit at the time of reading. In the case of initialization, initialization data is held, and sense data is not output from the read circuit J100. Thereafter, when the sense data latch release pulse is generated in a state where the second read determination pulse is generated, the second sense data is output from J12 via the second data latch circuit J5 and input to the output system circuit. . When the sense data latch release pulse ends, the second data latch circuit J5 holds the data from the sense amplifier J3, and the output J12 does not change even if the output of the sense amplifier J3 changes thereafter. Thereafter, the sense control pulse ends, and the second read operation ends.

  When 2-bit data can be held in one memory cell, the read operation may be performed twice. Therefore, after the second read, the read circuit returns to the standby state, and the read operation is completed.

Japanese Patent Laid-Open No. 2004-63018

  A readout circuit using a time-division sensing method that sequentially compares currents in a time-division manner described in Patent Document 1 reads out quaternary data from one memory cell by controlling using the control pulse. Is possible. However, in the case of the time-division sensing method described in Patent Document 1, since it is necessary to switch the reference cell J8 at the second read time, it is necessary to charge / discharge the bit line of the switched reference cell J8. In addition, when the voltage of the reference line changes, the current load capability of the current load circuit J1 whose reference line is input to the gate changes, thereby charging the bit line of the memory cell J7 connected to the current load circuit J1. Discharging is required again.

  Furthermore, a larger problem is that the sense line transitions to a high voltage at the time of the first read as in Data01, but the sense line transitions to a low voltage at the time of the second read, or the first time as at Data10. In the read operation, the sense line transitions to a low voltage, but in the second read operation, conversely, the sense line transitions to a high voltage. is there.

  In a large-capacity semiconductor memory device, in order to reduce the chip size, many memory cells are connected to one bit line for efficient use of area, and the parasitic capacitance may be about 1 pF. is there. On the other hand, since the charge / discharge current of the bit line by each memory cell and the current load circuit is about 5 to 10 μA in the multi-value flash EEPROM, it takes a very long time to charge / discharge the bit line (assuming 1 pF) When a bit line having a parasitic capacitance of 5 μA is driven with a current of 5 μA, a time of 20 ns is required to obtain an amplitude of 0.1 V). Furthermore, when the read operation must be executed a plurality of times to read data of one memory cell as in the time-division sensing method, the influence becomes larger and the access time is greatly delayed. It becomes.

In addition, when performing multi-level reading in which n-bit data is held in one memory cell, (2 ⁿ −1) types of reference cells are required, but the setting of reference cells is generally a test before shipment. Since this is sometimes performed, the test time increases due to the increase in the number of reference cells, resulting in an increase in test cost.

  The present invention has been made in view of the above problems, and an object of the present invention is to increase the speed of a read operation and reduce the number of reference cells for reading in a multilevel semiconductor memory device. Another object of the present invention is to provide a read circuit for a semiconductor memory device.

  In order to achieve the above object, a read circuit of a semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cells, and a selected memory cell selected as a read target from a load circuit to a memory via a bit line. A cell current is supplied, a read current flowing through the selected memory cell is subjected to current-voltage conversion according to a storage state of the selected memory cell to generate a read voltage, and the read voltage and the reference voltage are used as a differential input. A read circuit of a semiconductor memory device that compares the two voltages with a differential circuit, wherein the differential circuit changes a circuit characteristic with respect to an input on the read voltage side in accordance with the number of states that the storage state can take. The first feature is that it can be configured.

  In the read circuit of the semiconductor memory device according to the first feature, the differential circuit includes a first NMOS transistor, and a plurality of second NMOS transistors having different current capabilities connected to the gate of the first NMOS transistor. A current mirror circuit, the gate and drain of the first NMOS transistor are connected to the drain of the first PMOS transistor to which the reference voltage is input, and the read voltage is input to each drain and gate of the second NMOS transistor. The drain of the second PMOS transistor is connected, and the source of each of the second NMOS transistors is connected to the drain of the characteristic control NMOS transistor to switch the characteristic control NMOS transistor on and off, Load characteristics for the drain current of the 2PMOS transistor is a second feature that varies as the circuit characteristics.

  In the read circuit of the semiconductor memory device according to the first feature, the differential circuit includes a first PMOS transistor, and a plurality of second PMOS transistors having different current capacities connected to the gate of the first PMOS transistor. A current mirror circuit, the gate and drain of the first PMOS transistor are connected to the drain of the first NMOS transistor to which the reference voltage is input, and the read voltage is input to each drain and gate of the second PMOS transistor. The drain of the second NMOS transistor is connected, and the source of each of the second PMOS transistors is connected to the drain of the characteristic control PMOS transistor, and the on / off of the characteristic control PMOS transistor is switched. Load characteristics for the drain current of the 2NMOS transistor to a third feature that varies as the circuit characteristics.

  The read circuit of the semiconductor memory device according to the second or third feature outputs a control signal for changing the circuit characteristics on the read voltage side a plurality of times according to the number of states, and outputs the control signal for the second and subsequent times. A fourth feature is that a control signal output circuit that is determined according to the output of the differential circuit with respect to the control signal output once before is provided.

  According to the present invention, a differential circuit using a read voltage and a reference voltage as a differential input can change circuit characteristics with respect to an input on the read voltage side in accordance with the number of states that a memory cell can take. Therefore, in comparison with the conventional time-division sensing method, the voltage of the node with a lighter parasitic load is displaced so that the voltage of the sense line and the reference line affected by the parasitic load of the bit line is not displaced. Thus, it is possible to shorten the charge / discharge time in each read operation of the time-division sensing method. As a result, it is possible to increase the access time for the memory cell.

Conventionally, (2 ⁿ −1) types of reference cells are required when performing n-bit multilevel reading. However, according to the present invention, reading can be performed with one type of reference cells. Since the reference cells are set at the time of the test before shipment, the test time can be shortened and the test cost can be reduced by reducing the number of reference cells.

  Hereinafter, embodiments of a read circuit of a semiconductor memory device according to the present invention (hereinafter, abbreviated as “the circuit of the present invention” as appropriate) will be described with reference to the drawings.

  In this embodiment, the read operation of the nonvolatile semiconductor memory device will be described. However, the circuit of the present invention is applicable to general semiconductor memory devices adopting a current sensing method for reading, and is nonvolatile. It is not limited to a semiconductor memory device or a volatile semiconductor memory device. Only the portion related to the read operation will be described, and the description of the write circuit, erase circuit, control circuit, etc. will be omitted.

  First, the configuration of the circuit of the present invention will be described with reference to FIG. Here, FIG. 1 is a schematic circuit diagram showing a configuration example of a readout circuit H100 which is a circuit of the present invention.

  In FIG. 1, a read circuit H100 selects a memory cell H7 as a read target from a plurality of memory cells included in the memory cell array via a bit line H141 selected by a bit line selection transistor H151, and the memory cell H7 The memory cell current flowing through the memory cell is subjected to current-voltage conversion to obtain a sense voltage (corresponding to a read voltage) of the sense line H9. Similarly, the reference cell H8 is selected via the bit line H142 selected by the bit line selection transistor H152, and the memory cell current flowing in the reference cell H8 is converted from current to voltage to obtain the reference voltage of the reference line H10. Then, the data stored in the memory cell H7 is read out by comparing the sense voltage of the sense line H9 and the reference voltage of the reference line H10. The NMOS transistors H131 and H132 connected to the sense line H9 and the reference line H10 are for limiting the drain voltage of the memory cell and the reference cell. By applying a bias voltage generated in the internal circuit to the gate, An object of the present invention is to suppress deterioration of retained data due to voltage application at the time of reading by setting drain voltages of a memory cell and a reference cell to a certain value or less.

  Next, a current load circuit (corresponding to a load circuit) will be described. The current load circuit uses a PMOS transistor in this embodiment, but this is not particularly limited to a PMOS transistor, and any element such as an NMOS transistor or a resistance element such as a well resistor may be used in the present invention. There is no effect. The PMOS transistor H1, which is a current load circuit of the memory cell H7, has a source connected to the power supply, a gate connected to the reference line H10, and a drain connected to the sense line H9. The PMOS transistor H2, which is a current load of the reference cell, has a source connected to the power supply and a gate and a drain connected to the reference line H10.

Next, the circuit configuration of the current mirror circuit (corresponding to a differential circuit) H101 will be described.
The sense line H9 is input to the gate of the PMOS transistor H203, the reference line H10 is input to the gate of the PMOS transistor H202, and a power source is connected to the sources of the PMOS transistors H203 and H202.

  The drain of the PMOS transistor H202 is connected to the gate and drain of the NMOS transistor H201. Further, the source of the NMOS transistor H201 is connected to the drain of the NMOS transistor H200. The source of the NMOS transistor H200 is grounded. The NMOS transistor H200 is used for controlling the current mirror circuit H101, and the current mirror circuit H101 operates when a high level (power supply voltage level) signal is input to the gate.

  The drain of the PMOS transistor H203 is connected to the drains of the NMOS transistors H211, H221, and H231. The gates of the NMOS transistors H211, H221, and H231 are connected to the gate and drain of the NMOS transistor H201. The sources of the NMOS transistors H211, H221, and H231 are connected to the drains of the corresponding NMOS transistors H210, H220, and H230, respectively. The NMOS transistors H211, H221, and H231 function in the same manner as the reference cells for multi-level reading used in the prior art. For example, by changing the gate width, the NMOS transistors H211, H221, and H231 have different current characteristics, respectively. In the system, multi-value reading can be performed by selectively switching on and off these NMOS transistors.

  The sources of the NMOS transistors H210, H220, and H230 are grounded. Control signals H212, H222, and H232 output from a current mirror switching circuit (corresponding to a control signal output circuit) H6 are input to the gates of the NMOS transistors H210, H220, and H230, respectively, and the NMOS transistor transistors H211, H221, H231 can be selected.

  The read current data H11 is input to the current mirror switching circuit H6, and the NMOS transistors H211, H221, and H231 are selected according to the read data H11 in order to execute the time division sensing method.

  The output H14 of the current mirror circuit H101 can be used as the output of the sense amplifier if the amplitude of the output voltage is sufficient, but in this embodiment, the outputs H14 and H15 of the current mirror circuit H101 are used. A case where the output signal is further amplified using the sense amplifier H3 will be described as an example.

  The output H14 from the current mirror circuit H101 is connected to the drain of the PMOS transistor H203, and the other output H15 is connected to the drain of the PMOS transistor H202. The sense amplifier H3 receives the output H14 and the output H15, and operates the sense amplifier H3 using the output H15 as a reference voltage, thereby determining and amplifying the voltage of the output H14. The output of the sense amplifier H3 is input to the output system circuit via the first data latch circuit H4 and the second data latch circuit H5, but there is no difference from the conventional semiconductor memory device thereafter. Here, since the current mirror circuit H3 is provided between the sense line H9 and the reference line H10 and the sense amplifier H3 as compared with the conventional technique, when the sense amplifier H3 having the same configuration as the conventional one is used, the sense amplifier The output of H3 outputs data inverted with respect to the data held in the memory cell. Therefore, as shown in FIG. 1, the data of the sense amplifier H3 is inverted by the inverter and input to the first data latch circuit H4 and the second data latch circuit H5. Even if the output of the sense amplifier H3 is not inverted by an inverter, it is inverted inside the first data latch circuit H4 and the second data latch circuit H5, or is inverted by an output system circuit. Also good.

Next, the operation principle of the read circuit H100 of this embodiment will be described.
First, by applying appropriate voltages to the gate and drain of the reference cell H8, a reference current flowing through the reference cell H8 is generated. A reference voltage is generated on the reference line H10 due to the current balance between the reference current and the PMOS transistor H2 constituting the current load circuit. In this embodiment, the value of the reference current is set to the middle of Data01 and Data10 shown in FIG. 2, that is, the M state of the prior art by adjusting the threshold voltage.

  On the other hand, by applying an appropriate voltage to the gate and drain of the memory cell H7, a memory cell current flowing through the memory cell H7 is generated. Here, since the reference voltage generated in the reference line H10 is applied to the gate of the PMOS transistor H1 constituting the current load circuit, the current load circuits H1 and H2 behave as a current mirror circuit, and the current load circuit The current capability of H1 is controlled by the reference cell H8 and the current load circuit H2. A sense voltage is generated on the sense line H9 due to the current balance between the current load circuit H1 whose current capability is controlled in this way and the selected cell H7 whose current driving capability changes depending on the storage state.

  The potential difference between the sense voltage and the reference voltage generated in this way is determined by the current mirror circuit H101. The potential difference of the output from the current mirror circuit is amplified and output by the sense amplifier H3, and the output is held in the first data latch circuit H4 as output data H11. Here, if the read operation for obtaining the output data H11 is the first read operation, the NMOS transistor H211 selected by the current mirror switching circuit H6 during the first read operation has the same characteristics as the NMOS transistor H201, and the NMOS transistor A current mirror operation is performed by the transistors H211 and H201.

  Subsequently, the current mirror switching circuit H6 switches the control signal H212 to the control signal H222 or the control signal H232 based on the output data H11 held in the first data latch circuit H4 by the first read operation. As a result, the NMOS transistor H211 is switched to the NMOS transistor H221 or H231 in the current mirror circuit H101.

  At this time, if the result of the first read operation held in the first data latch circuit H4 is “0”, the NMOS transistor in the current mirror circuit H101 is switched from H211 to H221, and the first read is performed. When the operation result is “1”, the NMOS transistor in the current mirror circuit H101 is switched from H211 to H231. Here, the NMOS transistor H221 determines the data areas “00” and “01” shown in FIG. 2, and the NMOS transistor H231 determines the data areas “10” and “11” shown in FIG. It is.

  Thereafter, the second read operation is performed as in the first read operation, and the output data H12 is stored in the second data latch circuit H5 as a result of the second read operation. As described above, 2-bit data stored in one memory cell H7 can be obtained as output data H11 and H12. Similarly, when n-bit information is stored in one memory cell, the n-bit information can be read by performing the sensing operation at least n times when the time-division sensing method is used.

  Next, the read principle when the read circuit H100 is used will be described with reference to FIGS.

  FIG. 3 shows voltage-current characteristics of the reference cell H8, the PMOS transistors H1 and H2 of the current load circuit, and the memory cell H7. The reference cell H8 corresponds to I (ref), the PMOS transistor H2 of the current load circuit of the reference cell H8 corresponds to I (ph2), the PMOS transistor H1 of the current load circuit of the memory cell H7 corresponds to I (ph1), and The memory cell H7 has I (00), I (01), I (10), and I (11) for data “00”, “01”, “10”, and “11”. Each corresponds.

  The reference voltage output to the reference line H10 during the read operation is V (ref) determined by the stable points (intersections in the figure) of the two currents I (ref) and I (ph2). On the other hand, a reference line H10 is connected to the gate of the PMOS transistor H1, and the PMOS transistors H1 and H2 are configured to have the same characteristics by performing a current mirror operation. For this reason, I (ph1) indicating the voltage-current characteristics of the PMOS transistor H1 has a major characteristic that it shows a characteristic that intersects with the intersection of I (ref) of the reference cell H8 and I (ph2) of the PMOS transistor H2.

  Subsequently, the operation of the sense line H9 will be described. As shown in FIG. 2, when there are a plurality of memory cells, the memory cell group has a distribution width in each data state, so naturally the voltage-current characteristic also has a width in each data state. However, here, the voltage-current characteristic of the intermediate value of each state is given as an example.

  The sense voltage of the sense line H9 is determined by the stable points of the PMOS transistor H1 and the memory cell H7. That is, according to the storage state of the memory cell H7, the intersection of I (ph1) and I (00), the intersection of I (ph1) and I (01), the intersection of I (ph1) and I (10) in FIG. , I (ph1) and I (11) are determined by one of the intersections, and each of the outputs V (00), V (01), V (10), and V (11) is the sense voltage of the sense line. Is output as

  In this way, the reference voltage is output to the reference line H10, the sense voltage is output to the sense line H9, and they are input to the current mirror circuit H101.

  Depending on the sense voltage, the voltage-current characteristics of the PMOS transistor H203 of the current mirror circuit H101 become I (p00), I (p01), I (p10), and I (p11) in FIG. Depending on the voltage, the voltage-current characteristic of the PMOS transistor H202 becomes I (pref). Since the sense voltage decreases in the order of V (00), V (01), V (10), and V (11), the current of the PMOS transistor H203 to which the voltage is input is I (p00), I It increases in the order of (p01), I (p10), and I (p11). Since the reference voltage V (ref) is between V (01) and V (10), the current I (pref) of the PMOS transistor H201 is between I (p01) and I (p10).

  The voltage-current characteristic of the NMOS transistor H201 becomes I (n201), and V (refmh) is output to the drain (node H15) of the PMOS transistor H202 due to the stable point with the current I (pref) of the PMOS transistor H201. The On the other hand, since the NMOS transistor H211 has the same characteristics as the NMOS transistor H201, the voltage-current characteristic intersects with the intersection of I (pref) and I (n201) like I (n211).

  As a result, the output voltages V (mh00) and V (mh01) output to the drain (node H14) of the PMOS transistor H203 when the memory cell H7 is Data00, 01 as shown in FIG. The output voltages V (mh10) and V (mh11) when the memory cell H7 is Data10 and 11 are lower than the voltage V (refmh) and higher than the reference voltage V (ref). In this embodiment, the sense amplifier H3 outputs “0” if the sense voltage is higher than the reference voltage, and conversely outputs “1” if the sense voltage is lower than the reference voltage. ing. Therefore, if the selected memory cell H7 is in the Data00, 01 state, the output of the sense amplifier H3 in the first read operation is “1”, and conversely if it is in the Data10, 11 state, the output of the sense amplifier H3. Becomes “0”. In this manner, the state of the memory cell H7 can be limited from 4 states to 2 states by the first read operation. The data output in the first read operation is inverted by the inverter and input to the first data latch circuit H4. The first data latch circuit H4 holds 0 in the case of Data00, 01, holds 1 in the case of Data10, 11, and further outputs the held data as output data H11.

  The output data H11 is input to the current mirror switching circuit H6. This is because the result of the first read operation is reflected during the second read operation, and the NMOS transistor used in the current mirror circuit H101 in the second read operation is switched from H211 to H221 or H231. When the output data H11 of the first data latch circuit H4 is “0”, that is, when the selected memory cell H7 is in the state of Data00 or 01, in order to determine these two states in the second read operation, The NMOS transistor used in the current mirror circuit H101 is switched from H211 to H221. The NMOS transistor H221 has a smaller current supply capability (about 2/3 times) than the NMOS transistor H211 so that Data00 and 01 can be distinguished. On the other hand, when the output data H11 of the first data latch circuit H4 is “1”, that is, when the selected memory cell H7 is in the state of Data 10 or 11, in the second read operation, these two states are discriminated. The NMOS transistor used in the current mirror circuit H101 is switched from H211 to H231. The NMOS transistor H231 has a higher current supply capability (about 1.5 times) than the NMOS transistor H211 so that the data 10 and 11 can be distinguished. As shown in FIG. 1, since the switching of the NMOS transistor is performed by selecting the selection signals H212, H222, and H232 (one of them is set to the high level), the current mirror switching circuit H6 performs the first read operation. H212 is selected at the time, and at the time of the second read operation, H222 is selected if the output data H11 in the first read operation is “0”, and H232 is selected if it is “1”.

  Next, the case where the output data H11 is “0” in the first read operation in the second read operation will be described.

  When the output data H11 is “0” in the first read operation, the NMOS transistor used in the current mirror circuit H101 is switched from H211 to H221 during the second read operation. As shown in FIG. 4B, the voltage-current characteristic of the NMOS transistor H221 has a current supply capability smaller than that of I (n211) as I (n221). Since the state of the memory cell is either Data00 or 01, the voltage-current characteristics of the memory cell need only consider I (p00) and I (p01) in FIG. That is, only the output determined by the intersection of I (n221) and I (p00) and the intersection of I (n221) and I (p01) in FIG.

  When the selected memory cell is Data00, the voltage-current characteristic of the PMOS transistor H203 of the current mirror circuit H101 indicates I (p00) in FIG. 4B, and the output voltage is the voltage-current of the NMOS transistor H221. V (hh00), which is a stable point with the characteristic I (n221). On the other hand, when the selected memory cell is Data01, the voltage-current characteristic of the PMOS transistor H203 of the current mirror circuit H101 indicates I (p01) in FIG. 4B, and the output voltage is the voltage of the NMOS transistor H221. -V (hh01) which is a stable point with the current characteristic I (n221). Therefore, as shown in FIG. 4B, the sense voltage V (hh00) of Data00 is lower than the reference voltage V (refmh), and the sense voltage V (hh01) of Data01 is higher than the reference voltage V (refmh). become. Here, the sense amplifier H3 outputs “0” if the sense voltage H14 is higher than the reference voltage H15, and conversely outputs “1” if the sense voltage H14 is lower than the reference voltage H15. Therefore, if the selected memory cell H7 is in the Data00 state, the output of the second read operation is “1”. Conversely, if the selected memory cell H7 is in the Data01 state, the output is “0”. The output of the second read operation output in this way is inverted by the inverter and input to the second data latch circuit H5. The second data latch circuit H5 holds “0” in the case of Data00, holds “1” in the case of Data01, and further outputs the held data as output data H12.

  As a result, when the memory cell H7 is Data00, the output data H11 of the first read operation is “0”, the output data H12 of the second read operation is “0”, and the memory cell H7 is Data01. The output data H11 for the first read operation is “0” and the output data H12 for the second read operation is “1”, so that data can be output correctly.

  Subsequently, a case where the output data H11 is “1” in the first read operation in the second read operation will be described.

  When the output data H11 is “1” in the first read operation, the NMOS transistor used in the current mirror circuit H101 is switched from H211 to H231 during the second read operation. As shown in FIG. 4C, the voltage-current characteristic of the NMOS transistor H231 has a current supply capability higher than that of I (n211) as in I (n231). Since the state of the memory cell is either Data 10 or 11, the voltage-current characteristics of the memory cell need only take into account I (p10) and I (p11) in FIG. That is, only the output determined by the intersection of I (n231) and I (p10) and the intersection of I (n231) and I (p11) in FIG.

  When the selected memory cell is Data10, the voltage-current characteristic of the PMOS transistor H203 of the current mirror circuit H101 indicates I (p10) in FIG. 4C, and the output voltage is the voltage-current of the NMOS transistor H231. V (lh10) which is a stable point with the characteristic I (n231) is obtained. On the other hand, when the selected memory cell is Data11, the voltage-current characteristic of the PMOS transistor H203 of the current mirror circuit H101 indicates I (p11) in FIG. 4C, and the output voltage is the voltage of the NMOS transistor H231. -V (lh11) which is a stable point with the current characteristic I (n231). Therefore, as shown in FIG. 4C, the sense voltage V (lh10) of Data10 is lower than the reference voltage V (refmh), and the sense voltage V (lh11) of Data11 is higher than the reference voltage V (refmh). become. Here, the sense amplifier H3 is configured to output 0 if the sense voltage H14 is higher than the reference voltage H15, and conversely, if the sense voltage H14 is lower than the reference voltage H15, 1 is output. If the memory cell H7 is in the state of Data10, the output of the second read operation is 1, and conversely, if it is in the state of Data11, the output of the second sense is 0. The output of the second read operation output in this way is inverted by the inverter and input to the second data latch circuit H5. The second data latch circuit H5 holds 0 in the case of Data10, holds 1 in the case of Data11, and further outputs the held data as output data H12.

  As a result, when the memory cell H7 is Data10, the output data H11 of the first read operation is 1, the output data H12 of the second read operation is 0, and when the memory cell H7 is Data11, the first read operation The output data H11 is 1, and the output data H12 of the second read operation is 1, so that the data can be output correctly.

  Next, the operation of the readout circuit H100 using this principle will be described along the timing of control pulses input to the readout circuit H100.

  Actually, a read operation is performed by inputting an address or a chip control signal to the semiconductor memory device. When a read operation is started, an address signal decoding process for selecting a memory cell corresponding to a specified address from a plurality of memory cell groups arranged in a grid is executed in the semiconductor memory device. Various control pulses are generated in order to efficiently operate various circuits in the semiconductor memory device. Of these control pulses, only typical pulses for controlling the read circuit H100 will be described here.

  Here, FIG. 5 shows timing waveforms of the control pulse input to the read circuit H100, the voltage level of the sense line H9, the reference line H10, and the voltage level of the output H14 of the current mirror circuit H101. The read circuit H100 performs a series of read operations by sense amplifier control and data latch after precharge and bit line drive. Therefore, for example, when 2 bits of data can be held in one memory cell, it is necessary to perform the sense amplifier control and data latch operations twice. When n bits of data can be held, these operations are performed n times. It is necessary to do it once. Each operation will be described in order below.

  First, when a precharge control pulse is generated, during that time, the read circuit H100 applies the bit line connected to the memory cell to the memory cell corresponding to the address input to the semiconductor memory device. The operation to raise to a certain voltage is performed. This period is called a precharge period. In order to perform this operation, as shown in FIG. 6, a precharge circuit H17 or a bit line equalizing transistor H16 may be provided in the read circuit. The precharge circuit H17 is used to rapidly charge a heavily loaded bit line when the bit line load is large and has a large influence on the access time with respect to the current supply capability of the current load circuits H1 and H16 for reading. . The equalizing transistor H16 is used to keep the voltage level constant when precharging the bit lines of the memory cell and the reference cell. In terms of timing, there is no problem with the control timing of the precharge circuit H17 and the equalizing transistor H16 at the same time, so the same control pulse is input here. However, in order to individually control each of the control pulses, You may enter it.

  Between the end of the precharge control pulse and the generation of the sense control pulse, the sense line H9 and the reference line H10 are driven from the precharge voltage level by the memory cell, current load circuit, reference cell, and current load circuit shown in FIG. Charging and discharging is performed toward the voltage level of the stable point. This period is called a bit line driving period. The current mirror circuit H101 may cause an erroneous determination due to an offset if there is no difference between the voltage level of the sense line and the reference line beyond a certain level. Of course, if there is a certain level difference between the voltage levels of the sense line H9 and the reference line H10 while the current mirror circuit H101 is operating, the final determination can be made correctly, but the output of the current mirror circuit H101 at that time There is a risk of current consumption due to charging / discharging and time delay required for output inversion.

  When a sense control pulse is generated after the bit line drive period, the current mirror circuit H101 compares the voltage levels of the sense line H9 and the reference line H10 and outputs output data H14 and H15. The sense amplifier H3 to which the output data H14 and H15 are input outputs sense data. A period from when the sense control pulse is generated until the first sense data is latched is referred to as a first sense period. During the sensing period, the first sense data is output from the sense amplifier H3, but until the sense data latch release pulse is generated, the first data latch circuit H4 receives the previously read sense data or at the time of reading. When the first data latch circuit H4 is initialized, the initialization data is held, and the first sense data is not output from the read circuit H100. Thereafter, when a sense data latch release pulse is generated in a state where the second read determination pulse is not generated, the first sense data is output as output data H11 via the first data latch circuit H4, and the output system circuit and current Input to the mirror switching circuit H6. Thereafter, when the sense data latch release pulse ends, the first data latch circuit H4 holds the first sense data from the sense amplifier H3, and the output data H11 does not change even if the output of the sense amplifier H3 changes thereafter. The first read operation is completed.

  When shifting from the first reading to the second reading, the current mirror switching circuit H6 reflects the result of the first reading, that is, the output data H11, and the NMOS transistor used in the current mirror circuit H101 is changed from H211. Switch to H221 or H231.

  When the NMOS transistor of the current mirror circuit H101 is switched, the current mirror circuit H101 outputs data according to the principle of FIG. 4B or 4C, and the sense amplifier H3 to which the output is input receives the second sense data. Is output. A period from when the NMOS transistor of the current mirror circuit H101 is switched from H211 to H221 or H231 until the sense control pulse ends is referred to as a second sense period. During the second sense period, the second sense data is output from the sense amplifier H3. However, until the sense data latch release pulse is generated, the second data latch circuit H5 reads or reads the previously read sense data. Sometimes, when the second data latch circuit H5 is initialized, the initialization data is held, and the sense data is not output from the read circuit H100. Thereafter, when the sense data latch release pulse is generated in a state where the second read determination pulse is generated, the second sense data is output as the output data H12 via the second data latch circuit H5, and is output to the output system circuit. Entered. When the sense data latch release pulse ends, the second data latch circuit H5 holds the data from the sense amplifier H3, and the output data H12 does not change even if the output of the sense amplifier H3 changes thereafter. Thereafter, the sense control pulse ends, and the second read operation ends.

  In this embodiment, since it is assumed that 2-bit data can be held in one memory cell, the read operation may be performed twice. After the second read, the read circuit returns to the standby state, and the read operation is performed. The operation is complete.

  In this embodiment, when switching the characteristics of the current mirror circuit H101, three types of NMOS transistors H211, H221, and H231 are used. By selecting H211 and H221 at the same time, the same function as H231 can be provided. If possible, the area can be reduced by removing the NMOS transistor H231.

<Another embodiment>
Next, another embodiment of the circuit of the present invention will be described.

  In the present embodiment, a current mirror circuit H101C having a configuration different from that of the above embodiment will be described with reference to FIG.

  The sense line H9 is input to the gate of the NMOS transistor H303, the reference line H10 is input to the gate of the NMOS transistor H302, and the sources of the NMOS transistors H303 and H302 are grounded.

  The drain of the NMOS transistor H302 is connected to the gate and drain of the PMOS transistor H301. Further, the source of the PMOS transistor H301 is connected to the drain of the PMOS transistor H300. A power source is connected to the source of the PMOS transistor H300. The PMOS transistor H300 is used for controlling the current mirror circuit H101, and the current mirror circuit H101C operates when a low level (ground voltage level) signal is input to the gate.

  The drain of the NMOS transistor H303 is connected to the drains of the PMOS transistors H311, H321, and H331. The gates of the PMOS transistors H311, H321, and H331 are connected to the gate and drain of the PMOS transistor H301. The sources of the PMOS transistors H311, H321, and H331 are connected to the drains of the PMOS transistors H310, H320, and H330, respectively. The PMOS transistors H311, H321, and H331 function in the same manner as the multilevel read reference cell used in the prior art, as in the above embodiment. For example, by changing the gate width, different current characteristics are obtained. By providing this, multi-value reading can be performed by selectively switching on and off these PMOS transistors in the time-division sensing method.

  The sources of the PMOS transistors H310, H320, and H330 are connected to the power source. Control signals H212B, H222B, and H232B output from the current mirror switching circuit H6 are input to the gates of the PMOS transistors H310, H320, and H330, respectively, so that the PMOS transistor transistors H311, H321, and H331 can be selected at the time of reading. Yes.

  The current mirror circuit H101C in FIG. 7 is complementary to the current mirror circuit H101 shown in FIG. 1, and therefore the circuit operation is exactly the same except that the signal polarity is reversed. .

FIG. 6 is a circuit diagram showing a configuration example of a read circuit of a semiconductor memory device according to the present invention Distribution diagram showing relationship between memory cell current and data area in multi-level semiconductor memory device 6 is a graph showing voltage-current characteristics of a memory cell current and a reference current and a current load circuit in a read circuit of a semiconductor memory device according to the present invention. 6 is a graph showing voltage-current characteristics of a current mirror circuit in a read circuit of a semiconductor memory device according to the present invention. Timing chart of each control pulse and each output data of read circuit of semiconductor memory device according to the present invention FIG. 6 is a circuit diagram showing a configuration example of a precharge circuit and an equalize circuit used in a read circuit of a semiconductor memory device according to the present invention. The circuit diagram which shows the structure of another embodiment of the read-out circuit of the semiconductor memory device based on this invention Distribution diagram showing relationship between memory cell current and data area in multilevel semiconductor memory device, and distribution diagram showing relationship between memory cell current and data region in binary semiconductor memory device A circuit diagram showing an example of a configuration of a read circuit of a semiconductor memory device according to the prior art The graph which shows the voltage-current characteristic of the memory cell current in the read-out circuit of the semiconductor memory device concerning a prior art, a reference current, and a current load circuit Timing chart of each control pulse and output data of read circuit of semiconductor memory device according to prior art FIG. 6 is a circuit diagram showing a configuration example of a precharge circuit and an equalize circuit used in a read circuit of a semiconductor memory device according to a conventional technique

Explanation of symbols

H100: Read circuit J100 of the semiconductor memory device according to the present invention J100: Read circuit H101 of the semiconductor memory device according to the prior art: Current mirror circuit H101C: Current mirror circuit H1, H2, J1, J2: PMOS transistor H3, J3: Sense amplifier H4, J4: first data latch circuit H5, J5: second data latch circuit H6: current mirror switching circuit H7, J7: memory cells H8, J810, J820, J830: reference cells.
H141, H142, J141, J142: Bit lines H16, H131, H132, H151, H152, H200, H201, H202, H203, H210, H220, H230, H211, H221, H231, H300, H301, H302, H303, H310, H320, H330, H311, H321, H331, J15, J131, J132: Transistors H17, J14: Precharge circuit J6: Reference cell selection circuit

Claims (4)

A memory cell current is supplied from a load circuit to a selected memory cell selected as a reading target among a plurality of memory cells included in the memory cell array via a bit line, and the selected memory is selected according to a storage state of the selected memory cell. A read circuit of a semiconductor memory device that generates a read voltage by performing current-voltage conversion on a read current flowing through a cell, and compares the two voltages with a differential circuit that uses the read voltage and a reference voltage as a differential input. And
The read circuit of a semiconductor memory device, wherein the differential circuit is configured to be able to change a circuit characteristic with respect to an input on the read voltage side in accordance with the number of states that the storage state can take.   The differential circuit includes a current mirror circuit including a first NMOS transistor and a plurality of second NMOS transistors having different current capacities connected to the gate of the first NMOS transistor, and the gate of the first NMOS transistor, A drain and a drain of a first PMOS transistor to which the reference voltage is input are connected to the gate, each drain of the second NMOS transistor is connected to a drain of a second PMOS transistor to which the read voltage is input to the gate, and The source of each second NMOS transistor is connected to the drain of the characteristic control NMOS transistor, and the on / off of the characteristic control NMOS transistor is switched, so that the negative current with respect to the drain current of the second PMOS transistor is reduced. Read circuit for a semiconductor memory device according to claim 1, characteristic, characterized in that the varying as the circuit characteristics.   The differential circuit includes a current mirror circuit including a first PMOS transistor and a plurality of second PMOS transistors having different current capacities connected to the gate of the first PMOS transistor, and the gate of the first PMOS transistor, The drain and the drain of the first NMOS transistor to which the reference voltage is input are connected to the gate, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to which the read voltage is input, and the drain The source of each second PMOS transistor is connected to the drain of the characteristic control PMOS transistor, and the on / off of the characteristic control PMOS transistor is switched, so that the negative current with respect to the drain current of the second NMOS transistor is reduced. Read circuit for a semiconductor memory device according to claim 1, characteristic, characterized in that the varying as the circuit characteristics.   A control signal for changing the circuit characteristics on the read voltage side is output a plurality of times in accordance with the number of states, and the output of the differential circuit with respect to the control signal output the control signal for the second and subsequent times one time before 4. The read circuit for a semiconductor memory device according to claim 2, further comprising a control signal output circuit that is determined in accordance with the control signal output circuit.