JP2007141138A - Information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus that can capture the state at a moment when a CPU without any debugging function fails. <P>SOLUTION: A first CPU unit 1 has a debugging function of debugging programs executed by a CPU 11 and a CPU 21, and a second CPU unit 2 does not have any debugging function. A debugging data extraction part 211 of the second CPU unit 2 extracts data to be debugged, and a debugging data transmission part 224 transmits the data extracted by the debugging data extraction part 211 to the first CPU unit 1. A debugging data reception part 154 of the first CPU unit 1 receives the data transmitted by the debugging data transmission part 224, and a debugging execution part 112 executes the debugging function over the data received by the debugging data reception part 154. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus in which a plurality of CPU units including a CPU that executes a program and a memory that stores the program are connected to be communicable with each other.

  In information processing apparatuses such as printer apparatuses, copiers, and facsimile apparatuses that are already widely used, a plurality of CPUs are frequently operated in recent years to control the apparatuses. These CPUs are usually connected by a bus or a serial interface. In order to debug firmware operating on each of these CPUs, generally, hardware resources for debugging are mounted on each CPU. For this purpose, for example, it is common to use a CPU having an on-chip debugging function for each CPU, or to provide a socket for connecting an ICE (in-circuit emulator), which is a debugging device, to each CPU. In addition, a means for communicating with an external device is provided in each CPU.

  Also, a memory that can be read from and written to by the CPU is provided for each CPU, data transfer between the memories is performed by DMA (direct memory access), and a control unit controlled by one CPU is monitored by a control unit controlled by the other CPU A method has also been proposed.

  For example, Patent Document 1 discloses a controller unit including a first memory for both reading and writing, a control unit that controls a control target based on data in the first memory, and a first communication unit for monitoring. A monitoring unit including a second memory for both reading and writing, a monitoring unit for monitoring data in the second memory, and a second communication unit for monitoring; a direct memory access unit provided in the controller unit; A monitoring device for a controller unit having The monitoring device of the controller unit transfers the data in the first memory of the controller unit to the first communication unit by the direct memory access unit, and transfers the data from the first communication unit to the second communication unit. Further, the data is transferred to the second memory of the monitoring unit, the monitoring unit monitors the temporal change of the data in the first memory based on the transferred data, and the second memory is based on the monitoring result. The updated data is updated, the updated data is transferred from the second communication unit to the first communication unit, and further transferred from the first communication unit to the first memory by the direct memory access unit.

  Further, when the debugging function is provided in each CPU as described above, hardware resources for debugging are required. Therefore, the hardware resources are surely reflected in the cost, and this cost is particularly high in the information processing apparatus targeted for the low end. The increase is unacceptable. Accordingly, it is conceivable that the first CPU of the plurality of CPUs is provided with a debugging function, and the second CPU is not provided with a debugging function. In this case, the debugging means for debugging the firmware of the second CPU is limited to the ICE, but it is necessary to prepare an expensive socket in order to use the ICE, and it is not possible to equip a socket for each of a plurality of mass production boards. It was difficult in terms of cost. If there is no such debugging means, it takes a lot of time to find out the true cause even if a problem occurs during design, manufacturing, or user use, which is a disadvantage for both manufacturers and users. There was a problem.

  Therefore, an information processing system including a plurality of CPUs including a first CPU having a debugging function and a second CPU not having a debugging function, and the first CPU and the second CPU cooperatively operate by communication. In the apparatus, a remote debugging method has been proposed in which a communication protocol for debugging a second CPU is included in the communication protocol, and the second CPU is debugged using the debugging function of the first CPU.

Further, in the information processing apparatus having the above hardware configuration, the communication protocol includes information for directly executing a subroutine of a firmware operating on the second CPU in the communication protocol for debugging the second CPU having no debugging function. Remote debugging methods have been proposed.
Japanese Patent No. 3027062

  However, in the remote debugging method described above, the contents of the RAM and the like after the failure of the firmware of the second CPU is only acquired and confirmed using the debugging function of the first CPU. For this reason, it does not have a function for automatically displaying states with state transitions that are considered to be most effective for software debugging, and it is difficult to capture the state at the moment when a malfunction of a CPU that does not have a debugging function occurs. there were.

  The present invention has been made to solve the above-described problem, and an object thereof is to provide an information processing apparatus capable of capturing the state at the moment when a malfunction of a CPU having no debugging function occurs. It is.

  An information processing apparatus according to the present invention is an information processing apparatus in which a plurality of CPU units including a CPU that executes a program and a memory that stores the program are connected to be communicable with each other, and each of the plurality of CPU units includes A first CPU unit having a debugging function for debugging a program executed by the CPU; and a second CPU unit not having the debugging function. The second CPU unit extracts data used for debugging. Extracting means, and data transmitting means for transmitting the data extracted by the extracting means to the first CPU unit, wherein the first CPU unit receives the data transmitted by the data transmitting means Debugging using data receiving means and data received by the data receiving means And a execution means for executing ability.

  According to this configuration, the information processing apparatus includes a first CPU unit having a debugging function for debugging a program executed by each CPU included in the plurality of CPU units, and a second CPU unit having no debugging function. It has. Then, in the second CPU unit, data used for debugging is extracted, and the extracted data is transmitted to the first CPU unit. In the first CPU unit, data transmitted from the second CPU unit is received, and a debugging function is executed using the received data.

  Therefore, since data used for debugging is automatically extracted and transmitted to the first CPU unit in the second CPU unit that does not have the debugging function, the moment when the malfunction of the CPU that does not have the debugging function occurs. The state can be captured.

  In the information processing apparatus, it is preferable that the extraction unit extracts data used for debugging by executing an output function for outputting data used for debugging from the program.

  According to this configuration, since the data used for debugging is extracted by executing the output function for outputting the data used for debugging from the program, the output function described in the program is executed in advance. Thus, data used for debugging can be easily extracted.

  In the information processing apparatus, the second CPU unit includes a storage unit that stores data extracted by the extraction unit, a determination unit that determines whether data is stored in the storage unit, When the determination means determines that data is stored in the storage means, it further comprises an interrupt signal transmission means for transmitting an interrupt signal to the first CPU unit, wherein the first CPU unit An interrupt signal receiving means for receiving an interrupt signal transmitted by the transmitting means, and a data request signal for requesting data is transmitted to the second CPU unit when the interrupt signal is received by the interrupt signal receiving means. Data request signal transmission means, and the second CPU unit includes the data request signal. A data request signal receiving means for receiving the data request signal transmitted by the transmitting means; and a reading means for reading the data stored in the storage means when the data request signal is received by the data request signal receiving means. Further, it is preferable that the data transmission unit transmits the data read by the reading unit to the first CPU unit.

  According to this configuration, when the second CPU unit stores the extracted data in the storage unit, determines whether or not the data is stored in the storage unit, and determines that the data is stored in the storage unit An interrupt signal is transmitted to the first CPU unit. When the interrupt signal transmitted by the second CPU unit is received by the first CPU unit, a data request signal for requesting data is transmitted to the second CPU unit. Subsequently, in the second CPU unit, when the data request signal transmitted by the first CPU unit is received, the data stored in the storage unit is read, and the read data is the first data It is transmitted to the CPU unit.

  Therefore, when debugging data is stored in the storage means, an interrupt signal is transmitted from the second CPU unit to the first CPU unit, so that the first CPU unit always monitors the second CPU unit. This is unnecessary, and the second CPU unit can be debugged only when debugging data is extracted in the second CPU unit.

  In the above information processing apparatus, the first CPU unit further includes command receiving means for receiving a command transmitted by an external device, and the command includes the first CPU unit and the second CPU unit. The first CPU unit includes information designating which one to debug, and when the command includes information for debugging the first CPU unit, the data request signal transmitting means sends a data request It is preferable to further include first setting means for setting not to transmit a signal.

  According to this configuration, the first CPU unit receives a command transmitted by the external device. This command includes information for designating which of the first CPU unit and the second CPU unit to debug. In the first CPU unit, when the command includes information for debugging the first CPU unit, the data request signal is not transmitted by the data request signal transmitting means.

  Therefore, when debugging the first CPU unit, even if an interrupt signal from the second CPU unit is received, the data request signal is not transmitted, and the debugging data is not transmitted from the second CPU unit. The debugging data in the first CPU unit and the debugging data in the second CPU unit are not output at the same time, and only the first CPU unit can be debugged.

  In the above information processing apparatus, the first CPU unit further includes command receiving means for receiving a command transmitted by an external device, and the command includes the first CPU unit and the second CPU unit. Information for specifying which one to debug, and when the command includes information for debugging the first CPU unit, the second CPU unit outputs an interrupt signal from the interrupt signal transmitting means. It is preferable to further include second setting means for setting so as not to transmit.

  According to this configuration, the first CPU unit receives a command transmitted by the external device. This command includes information for designating which of the first CPU unit and the second CPU unit to debug. In the second CPU unit, when the command includes information for debugging the first CPU unit, the interrupt signal is not transmitted by the interrupt signal transmitting means.

  Therefore, when debugging the first CPU unit, the interrupt signal is not transmitted from the second CPU unit, and the debug data is not transmitted from the second CPU unit. Therefore, the debug data in the first CPU unit is not transmitted. And debugging data in the second CPU unit are not output at the same time, and only the first CPU unit can be debugged.

  In the above information processing apparatus, the information processing apparatus is an image forming apparatus that forms an image, and the first CPU unit includes a control unit that controls the entire image forming apparatus, and the second CPU The CPU unit preferably includes an engine control unit that controls a drive source built in the image forming apparatus.

  According to this configuration, even if the CPU unit is built in the apparatus like an engine control unit that controls a drive source built in the image forming apparatus and is difficult to directly debug by connecting an external device. Debugging can be performed via a control unit that controls the entire image forming apparatus that can be easily connected to an external device.

  According to the present invention, since data used for debugging is automatically extracted and transmitted to the first CPU unit in the second CPU unit that does not have the debugging function, there is a problem with the CPU that does not have the debugging function. The state of the moment when it occurs can be captured.

  Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an outline of the hardware configuration of an image forming apparatus which is an example of an information processing apparatus according to the present invention and a PC (personal computer) connected thereto. The image forming apparatus 10 is, for example, a printer, a copier, a facsimile machine, or the like. In the present embodiment, the image forming apparatus 10 is described as an example of an information processing apparatus. However, the present invention is not particularly limited thereto, and can be applied to an information processing apparatus other than the image forming apparatus 10.

  The image forming apparatus 10 is an embedded apparatus that is controlled by two CPUs (Central Processing Units) 11 and 21 that are connected by communication and operate in cooperation. The image forming apparatus 10 includes a first CPU unit 1 and a second CPU unit 2. The first CPU unit 1 includes a CPU 11, a ROM (read only memory) 12, a RAM (random access memory) 13, an operation panel unit 14, a communication unit 15, and a communication unit 16. The CPU 11, ROM 12, RAM 13, operation panel unit 14, communication unit 15 and communication unit 16 are connected by a local bus. The second CPU unit 2 includes a CPU 21, a communication unit 22, a ROM 23 and a RAM 24. The CPU 21, the communication unit 22, the ROM 23, and the RAM 24 are connected by a local bus.

  The first CPU unit 1 and the second CPU unit 2 are communicably connected by connecting the communication unit 15 and the communication unit 22. These communication units 15 and 22 are, for example, serial communication interfaces, and communicate by serial communication. This may be a bus connection, for example. In addition to the first and second CPU units 1 and 2, the image forming apparatus 10 includes a group of components that are connected to the CPU units 1 and 2 and controlled by the CPUs 11 and 21 to execute an image forming function (for example, a copy function). Here, it is not shown and description is omitted.

  When the information processing apparatus is an image forming apparatus, the first CPU unit 1 is a controller (control unit) that controls the entire image forming apparatus, for example, and the second CPU unit 2 is controlled by the first CPU unit 1, for example. An engine control unit that controls a motor (drive source) that drives a roller, a clutch, and the like built in the image forming apparatus. In this case, even if it is a CPU unit that is difficult to debug directly by connecting a PC, such as an engine control unit that controls a drive source built in the image forming apparatus, the PC is connected. It is possible to debug through the control unit that controls the entire image forming apparatus that is relatively easy to do. The second CPU unit 2 may be a post-processing device that is controlled by, for example, the first CPU unit 1 and performs post-processing (sorting processing, stapling processing, etc.) of paper on which images have been formed.

  A PC 3 is connected to the image forming apparatus 10 via a communication unit 16 as a terminal for a user to operate a debugging function. The PC 3 mainly includes a CPU 31, a communication unit 32, a RAM 33, an HDD 34, a display device 35, and an input device 36. Hereinafter, the components of the first and second CPU units 1 and 2 and the PC 3 will be described.

  The CPU 11 executes a program stored in the ROM 12 and controls the image forming apparatus 10 in cooperation with the CPU 21 to perform image formation and the like. The communication unit 16 is for connecting the PC 3 and is, for example, a serial communication interface. The ROM 12 is a memory for storing a program executed by the CPU 11. This program includes firmware for controlling the image forming apparatus 10 and a debugger program for providing a debugging function. The RAM 13 is a memory for giving a temporary work area or the like to the CPU 11. The operation panel unit 14 is used by a user to input an operation instruction to the image forming apparatus 10, and includes a display unit such as a liquid crystal display and operation key units such as a numeric keypad and a start key. Instead of the PC 3, the operation panel unit 14 may be used for the debugging function. The communication unit 15 is for connecting to the communication unit 22 of the second CPU unit 2, for transmitting and receiving inter-processor communication messages between the CPU units 1 and 2, and for the CPU 11 and CPU 21 to operate in cooperation, etc. Used for. The communication unit 16 is, for example, a serial communication interface for connecting to the communication unit 32 of the PC 3.

  The CPU 21 executes a program stored in the ROM 23 and controls the image forming apparatus 10 in cooperation with the CPU 11 to perform image formation. The communication unit 22 is connected to the communication unit 15 and is used for transmitting and receiving inter-processor communication messages between the CPU units 1 and 2 and for the CPU 11 and the CPU 21 to operate in cooperation. The ROM 23 is a memory for storing a program executed by the CPU 21. Unlike the first CPU unit 1, this program does not include a debugger program but includes only firmware. The RAM 24 is a memory for providing a temporary work area or the like to the CPU 21. The RAM 24 includes a transmission buffer and a change status buffer which will be described later.

  The CPU 31 executes a program in the RAM 33. The communication unit 32 is, for example, a serial communication interface for connecting to the communication unit 16 of the first CPU unit 1. Through this communication interface, a debug command is transmitted from the PC 3 to the first CPU unit 1 and a reply to the debug command is performed in the reverse path. The RAM 33 is a main storage device for temporarily storing a part executed by the CPU 31 among programs stored in the HDD 34. An HDD (Hard Disk Drive Device) 34 is an external storage device that stores programs executed by the CPU 31. The display device 35 is composed of a liquid crystal display device, for example, and is used as a display user interface of the PC 3. The input device 36 includes, for example, a keyboard and a mouse, and is used as an input interface for the PC 3.

  Here, programs executed by the CPU 11 of the first CPU unit 1, the CPU 21 of the second CPU unit 2, and the CPU 31 of the PC 3 will be described. Programs executed by the CPU 31 are mainly a PC-side debugger program and an OS (operating system). The OS is software that mediates between application software (including a PC-side debugger program) executed on the PC 3 by basic software of the PC 3 and hardware of the PC 3. The PC-side debugger program is application software that runs on the PC 3, and is activated / terminated by the user using the input device 36 and operated. The user designates a debug command as an operation of the PC-side debugger program and which of the first CPU unit 1 and the second CPU unit 2 to debug. Further, the user can check the execution result of the debug command displayed on the display device 35.

  The programs executed by the CPU 11 are first CPU unit side firmware and first CPU unit side debugger program. The first CPU unit side firmware is a program for controlling the image forming apparatus 10, that is, the first CPU unit 1 and the second CPU unit 2, and is a program to be debugged (program to be debugged). The first CPU unit side debugger program is a program that performs processing for debugging the first CPU unit side firmware executed by the CPU 11 and the second CPU unit side firmware executed by the CPU 21. When the image forming apparatus 10 is activated, the first CPU unit side debugger program is activated. The first CPU unit-side debugger program activates the first CPU unit-side firmware as necessary.

  The program executed by the CPU 21 is second CPU unit side firmware. The second CPU unit side firmware is a program for controlling the second CPU unit 2 and is a program to be debugged.

  The debug command that the user has instructed to execute in the PC-side debugger program is transmitted as a debug command transmission character string to the first CPU unit-side debugger program via the OS. A reply to the received debug command is sent to the PC-side debugger program through the reverse route of transmission.

  Transmission / reception of inter-processor communication messages in inter-processor communication between the first CPU unit-side firmware and the second CPU unit-side firmware is performed via the first CPU unit-side debugger program and the second CPU unit-side firmware. An inter-processor communication message from the first CPU unit side firmware to the second CPU unit side firmware is sent from the first CPU unit side debugger program to the second CPU unit side firmware in a predetermined communication frame (unit of data transmitted and received in communication). Transmission of the communication frame from the second CPU unit side firmware to the first CPU unit side firmware takes the reverse path.

  The predetermined communication frame (format) used in the inter-processor communication message is also used when a debug command and its reply are transmitted and received between the first CPU unit-side debugger program and the second CPU unit-side firmware.

  FIG. 2 is a block diagram showing a functional configuration of the first CPU unit 1 and the second CPU unit 2. The first CPU unit 1 includes a CPU 11, a communication unit 15, and a communication unit 16. The communication unit 16 includes a debug command receiving unit 161. The debug command receiving unit 161 receives a debug command transmitted by the PC 3. The debug command includes information that specifies which of the first CPU unit 1 and the second CPU unit 2 is to be debugged. The debug command also includes an instruction to execute a predetermined function included in the firmware, an instruction to read data from the memory, an instruction to rewrite data to the memory, and the like.

  The CPU 11 includes a debug setting unit 111 and a debug execution unit 112. The debug setting unit 111 analyzes the debug command received by the debug command receiving unit 161 and determines whether the debug target is the first CPU unit 1 or the second CPU unit 2. When the debug target is the first CPU unit 1, the debug setting unit 111 sets the data request signal transmission unit 153 not to transmit the data request signal. In addition, when the debug target is the second CPU unit 2, the debug setting unit 111 instructs the start instruction signal transmission unit 151 to transmit a start instruction signal to the second CPU unit 2.

  When the debug target is the first CPU unit 1, the debug executing unit 112 executes debugging of firmware stored in the first CPU unit 1. In addition, when the debug target is the second CPU unit 2, the debug executing unit 112 executes debugging using the debug data received by the debug data receiving unit 154.

  The communication unit 15 includes a start instruction signal transmission unit 151, an interrupt signal reception unit 152, a data request signal transmission unit 153, and a debug data reception unit 154. The start instruction signal transmission unit 151 transmits a start instruction signal to the second CPU unit 2 based on an instruction from the debug setting unit 111. The interrupt signal receiving unit 152 receives the interrupt signal transmitted by the second CPU unit 2. When the interrupt signal receiving unit 152 receives an interrupt signal, the data request signal transmitting unit 153 transmits a data request signal for requesting debug data to the second CPU unit 2. The debug data receiving unit 154 receives debug data transmitted by the second CPU unit 2.

  The second CPU unit 2 includes a CPU 21, a communication unit 22, and a RAM 24. The communication unit 22 includes a start instruction signal reception unit 221, an interrupt signal transmission unit 222, a data request signal reception unit 223, and a debug data transmission unit 224. The CPU 21 includes a debug data extraction unit 211, a determination unit 212, and a debug data reading unit 213.

  The start instruction signal receiving unit 221 receives the start instruction signal transmitted by the first CPU unit 1. When the start instruction signal is received by the start instruction signal receiver 221, the debug data extractor 211 executes the firmware stored in the second CPU unit 2 and extracts debug data used for debugging. The debug data extraction unit 211 monitors data contents stored in the transmission buffer 241 and the change status buffer 242, outputs the extracted debug data to the transmission buffer 241, and outputs debug data from the transmission buffer 241 to the change status buffer 242. Output.

  The determination unit 212 determines whether debug data is stored in the change status buffer 242. The interrupt signal transmission unit 222 transmits an interrupt signal to the first CPU unit 1 when the determination unit 212 determines that the debug data is stored in the change status buffer 242. The data request signal receiving unit 223 receives the data request signal transmitted by the first CPU unit 1.

  The debug data reading unit 213 reads debug data from the change status buffer 242 when the data request signal is received by the data request signal receiving unit 223. The debug data transmitting unit 224 transmits the debug data read by the debug data reading unit 213 to the first CPU unit 1.

  The RAM 24 includes a transmission buffer 241 and a change status buffer 242. The transmission buffer 241 stores the debug data extracted by the debug data extraction unit 211. Note that the debug data stored in the transmission buffer 241 is composed of, for example, a plurality of characters. The change status buffer 242 stores state change information of the second CPU unit 2 and stores debug data output from the transmission buffer 241. Note that the transmission buffer 241 sequentially outputs a plurality of characters to the change status buffer 242 one by one. The debug data stored in the change status buffer 242 stores, for example, a plurality of characters one by one.

  Note that the state change information of the second CPU unit 2 stored in the change status buffer 242 is, for example, information indicating that the side cover is open when the second CPU unit 2 is a post-processing device. That is, the state change information is information for voluntarily notifying the first CPU unit 1 of the changed state when the state of the second CPU unit 2 changes.

  In the present embodiment, the image forming apparatus 10 corresponds to an example of an information processing apparatus, the first CPU unit 1 corresponds to an example of a first CPU unit, and the second CPU unit 2 corresponds to an example of a second CPU unit. The debug data extraction unit 211 corresponds to an example of an extraction unit, the debug data transmission unit 224 corresponds to an example of a data transmission unit, the debug data reception unit 154 corresponds to an example of a data reception unit, and the debug execution unit 112 Corresponds to an example of execution means.

  The RAM 24 corresponds to an example of a storage unit, the determination unit 212 corresponds to an example of a determination unit, the interrupt signal transmission unit 222 corresponds to an example of an interrupt signal transmission unit, and the interrupt signal reception unit 152 includes an interrupt signal reception unit. The data request signal transmitting unit 153 corresponds to an example of a data request signal transmitting unit, the data request signal receiving unit 223 corresponds to an example of a data request signal receiving unit, and the debug data reading unit 213 is a reading unit. It corresponds to an example. Further, the debug command receiving unit 161 corresponds to an example of a command receiving unit, and the debug setting unit 111 corresponds to an example of a first setting unit.

  Next, the debugging operation by the first CPU unit 1 and the second CPU unit 2 will be described. FIG. 3 is a flowchart for explaining a debugging operation by the first CPU unit 1 and the second CPU unit 2 shown in FIG.

  First, the input device 36 of the PC 3 receives an input of a debug command by the user. At this time, the input device 36 accepts which unit of the first CPU unit 1 and the second CPU unit 2 is to be debugged. The communication unit 32 transmits the debug command received by the input device 36 to the first CPU unit 1. Then, the debug command receiving unit 161 of the first CPU unit 1 receives the debug command transmitted by the PC 3 (step S1). The debug command receiving unit 161 outputs the received debug command to the debug setting unit 111.

  Next, the debug setting unit 111 analyzes the debug command received by the debug command receiving unit 161 (step S2). As a result of analyzing the debug command, when the debug command includes information indicating that the first CPU unit 1 is debugged, the debug setting unit 111 does not transmit a data request signal even if an interrupt signal is received. The request signal transmission unit 153 is set (step S3). In addition, when the debug command includes information indicating that the second CPU unit 2 is debugged as a result of analyzing the debug command, the debug setting unit 111 issues a start instruction signal to debug the second CPU unit 2. The signal is output to the signal transmission unit 151.

  Next, the debug setting unit 111 determines whether or not to debug the first CPU unit 1 (step S4). If it is determined that the first CPU unit 1 is to be debugged (YES in step S4), the process proceeds to step S9, and the debug executing unit 112 executes debugging of the firmware stored in the ROM 12.

  On the other hand, when it is determined not to debug the first CPU unit 1, that is, to debug the second CPU unit 2 (NO in step S4), the start instruction signal transmission unit 151 transmits a start instruction signal to the second CPU unit 2 (step S4). S5).

  Next, the start instruction signal receiving unit 221 of the second CPU unit 2 receives the start instruction signal transmitted by the first CPU unit 1 (step S11). When the start instruction signal is received by the start instruction signal receiving unit 221, the debug data extracting unit 211 executes the firmware stored in the ROM 23 and extracts debug data (debug data) (step S 12). The extracted debug data is output to the transmission buffer 241 (step S13). The debug data is extracted when the debug data extraction unit 211 executes an output function for outputting debug data included in the firmware. As this output function, for example, a printf function which is a general-purpose output function of C language is used.

  Thus, since the data used for debugging is extracted by executing the output function for outputting the data used for debugging from the program, by executing the output function described in advance in the program, Data used for debugging can be easily extracted. In this embodiment, the printf function, which is a general-purpose output function in C language, is used. However, the present invention is not particularly limited to this, and output functions in other languages may be used.

  Next, the debug data extraction unit 211 monitors the storage contents of the transmission buffer 241 and determines whether debug data is stored in the transmission buffer 241 (step S14). If it is determined that debug data is not stored in the transmission buffer 241 (NO in step S14), the process returns to step S12 to execute a process of extracting debug data.

  On the other hand, when it is determined that debug data is stored in the transmission buffer 241 (YES in step S14), the debug data extraction unit 211 outputs the debug data stored in the transmission buffer 241 to the change status buffer 242. (Step S15). At this time, when debug data composed of a plurality of characters is stored in the transmission buffer 241, the debug data extraction unit 211 extracts the characters from the transmission buffer 241 one by one in order from the first character, and sends them to the change status buffer 242. Output.

  Next, the determination unit 212 monitors the stored contents of the change status buffer 242 and determines whether or not the change status buffer 242 is empty (step S16). If it is determined that the change status buffer 242 is empty (YES in step S16), the determination unit 212 repeatedly executes the determination in step S16 at predetermined intervals until debug data is stored in the change status buffer 242. To do.

  On the other hand, when it is determined that the change status buffer 242 is not empty (NO in step S <b> 16), the determination unit 212 outputs an interrupt signal to the interrupt signal transmission unit 222 in order to generate an interrupt process in the first CPU unit 1. Next, the interrupt signal transmission unit 222 transmits an interrupt signal to the first CPU unit 1 (step S17).

  Next, the interrupt signal receiver 152 of the first CPU unit 1 receives the interrupt signal transmitted by the second CPU unit 2 (step S6). When the interrupt signal is received by the interrupt signal receiving unit 152, the data request signal transmitting unit 153 transmits a data request signal for requesting transmission of debug data to the second CPU unit 2 (step S7).

  Next, the data request signal receiver 223 of the second CPU unit 2 receives the data request signal transmitted by the first CPU unit 1 (step S18). Next, when the data request signal is received by the data request signal receiving unit 223, the debug data reading unit 213 reads the debug data stored in the change status buffer 242 (step S19). The debug data reading unit 213 outputs the read debug data to the debug data transmitting unit 224.

  Next, the debug data transmitting unit 224 transmits the debug data read from the change status buffer 242 by the debug data reading unit 213 to the first CPU unit 1 (step S20). Then, after the debug data is transmitted to the first CPU unit 1, the process returns to the process of step S14, it is determined whether or not there is debug data in the transmission buffer 241, and the subsequent processes are executed.

  Next, the debug data receiving unit 154 of the first CPU unit 1 receives the debug data transmitted by the second CPU unit 2 (step S8). The debug data receiving unit 154 outputs the received debug data to the debug executing unit 112.

  Next, the debug executing unit 112 executes a debug function using the debug data received by the debug data receiving unit 154 (step S9). Specifically, the debug execution unit 112 outputs debug data to the PC 3 via the communication unit 16. The communication unit 32 of the PC 3 receives the debug data transmitted by the first CPU unit 1 and outputs it to the display device 35. The display device 35 displays debug data received by the communication unit 32. In this way, the debug result for the debug command input by the input device 36 is displayed on the display device 35.

  Next, a specific debugging operation by the first CPU unit 1 and the second CPU unit 2 shown in FIG. 2 will be described. FIG. 4 is a schematic diagram for explaining a specific debugging operation by the first CPU unit 1 and the second CPU unit 2 shown in FIG.

  First, the debug data extraction unit 211 of the second CPU unit 2 executes a program (firmware) 231 stored in the ROM 23, extracts debug data (debug data), and sends the extracted debug data to the transmission buffer 241. Output. In FIG. 4, a process of transmitting debug data “BUG” will be described. At this time, the debug data extraction unit 211 extracts the debug data “BUG” by executing the printf function included in the program 231 and stores it in the transmission buffer 241.

  When debug data is stored in the transmission buffer 241, the debug data extraction unit 211 outputs debug data of the first character from the top of the transmission buffer 241 to the change status buffer 242. In this case, debug data “B” located at the head of the transmission buffer 241 is output to the change status buffer 242.

  Then, when debug data “B” is stored in the change status buffer 242, the interrupt signal transmission unit 222 transmits an interrupt signal (interrupt request) to the first CPU unit 1 (step S101). Next, when the interrupt signal is received by the interrupt signal receiver 152 in the first CPU unit 1, the data request signal transmitter 153 transmits a data request signal (data request) to the second CPU unit 2 (step S102). .

  Next, in the second CPU unit 2, when the data request signal is received by the data request signal receiving unit 223, the debug data reading unit 213 reads the debug data “B” stored in the change status buffer 242, The data is output to the debug data transmission unit 224. Next, the debug data transmitting unit 224 transmits debug data “B” read from the change status buffer 242 to the first CPU unit 1 as a response signal of the data request signal (step S103).

  Next, when debug data “B” is received by the debug data receiving unit 154 of the first CPU unit 1, the debug executing unit 112 transmits debug data “B” to the PC 3 via the communication unit 16. The display device 35 of the PC 3 displays the received debug data “B”.

  As described above, the debug data “B” among the debug data composed of a plurality of characters “BUG” is displayed on the display device 35 of the PC 3.

  Subsequently, the debug data extraction unit 211 outputs the debug data of the second character from the top of the transmission buffer 241 to the change status buffer 242. In this case, debug data “U” located at the second character from the top of the transmission buffer 241 is output to the change status buffer 242.

  When debug data “U” is stored in the change status buffer 242, the interrupt signal transmission unit 222 transmits an interrupt signal (interrupt request) to the first CPU unit 1 (step S104). Next, in the first CPU unit 1, when the interrupt signal is received by the interrupt signal receiver 152, the data request signal transmitter 153 transmits a data request signal (data request) to the second CPU unit 2 (step S105). .

  Next, in the second CPU unit 2, when the data request signal is received by the data request signal receiving unit 223, the debug data reading unit 213 reads the debug data “U” stored in the change status buffer 242, The data is output to the debug data transmission unit 224. Next, the debug data transmission unit 224 transmits the debug data “U” read from the change status buffer 242 to the first CPU unit 1 as a response signal of the data request signal (step S106).

  Next, when debug data “U” is received by the debug data receiving unit 154 of the first CPU unit 1, the debug executing unit 112 transmits debug data “U” to the PC 3 via the communication unit 16. The display device 35 of the PC 3 displays the received debug data “U”.

  As described above, the debug data “BU” among the debug data composed of a plurality of characters “BUG” is displayed on the display device 35 of the PC 3.

  Similarly, the debug data extraction unit 211 outputs debug data of the third character from the top of the transmission buffer 241 to the change status buffer 242. In this case, debug data “G” located at the third character from the top of the transmission buffer 241 is output to the change status buffer 242.

  When the debug data “G” is stored in the change status buffer 242, the interrupt signal transmission unit 222 transmits an interrupt signal (interrupt request) to the first CPU unit 1 (step S107). Next, in the first CPU unit 1, when the interrupt signal is received by the interrupt signal receiver 152, the data request signal transmitter 153 transmits a data request signal (data request) to the second CPU unit 2 (step S108). .

  Next, in the second CPU unit 2, when the data request signal is received by the data request signal receiving unit 223, the debug data reading unit 213 reads the debug data “G” stored in the change status buffer 242, The data is output to the debug data transmission unit 224. Next, the debug data transmission unit 224 transmits debug data “G” read from the change status buffer 242 to the first CPU unit 1 as a response signal of the data request signal (step S109).

  Next, when debug data “G” is received by the debug data receiving unit 154 of the first CPU unit 1, the debug executing unit 112 transmits debug data “G” to the PC 3 via the communication unit 16. The display device 35 of the PC 3 displays the received debug data “G”.

  As described above, debug data “BUG” out of debug data composed of a plurality of characters “BUG” is displayed on the display device 35 of the PC 3.

  As described above, the image forming apparatus 10 includes the first CPU unit 1 having a debugging function for debugging a program executed by the CPU 11 and the CPU 21 and the second CPU unit 2 having no debugging function. Then, in the second CPU unit 2, data used for debugging (debug data) is extracted, and the extracted debug data is transmitted to the first CPU unit 1. The first CPU unit 1 receives the debug data transmitted from the second CPU unit 2 and executes the debug function using the received debug data.

  Therefore, since data used for debugging is automatically extracted and transmitted to the first CPU unit 1 in the second CPU unit 2 that does not have the debugging function, the state at the moment when the malfunction of the CPU 21 that does not have the debugging function occurs. Can be caught.

  Further, in the second CPU unit 2, the extracted debug data is stored in the change status buffer 242 of the RAM 24, it is determined whether or not the data is stored in the change status buffer 242, and the data is stored in the change status buffer 242. If it is determined, an interrupt signal is transmitted to the first CPU unit 1. When the first CPU unit 1 receives the interrupt signal transmitted by the second CPU unit 2, a data request signal for requesting debug data is transmitted to the second CPU unit 2. Subsequently, when the second CPU unit 2 receives the data request signal transmitted by the first CPU unit 1, the debug data stored in the change status buffer 242 is read, and the read debug data is 1 is transmitted to the CPU unit 1.

  Accordingly, when debugging data is stored in the change status buffer 242 of the RAM 24, an interrupt signal is transmitted from the second CPU unit 2 to the first CPU unit 1, so the first CPU unit 1 always monitors the second CPU unit 2. There is no need, and the second CPU unit 2 can be debugged only when debugging data is extracted in the second CPU unit 2.

  Further, the first CPU unit 1 receives a debug command transmitted by the PC 3. This debug command includes information specifying which of the first CPU unit 1 and the second CPU unit 2 is to be debugged. In the first CPU unit 1, when the debug command includes information for debugging the first CPU unit 1, the data request signal transmission unit 153 is set not to transmit the data request signal.

  Therefore, when debugging the first CPU unit 1, the data request signal is not transmitted even if the interrupt signal from the second CPU unit 2 is received, and the debugging data is not transmitted from the second CPU unit 2. The debugging data in the second CPU unit 2 and the debugging data in the second CPU unit 2 are not output at the same time, and only the first CPU unit 1 can be debugged.

  In the present embodiment, when the debug command includes information indicating that the first CPU unit 1 is debugged, the data request signal transmission unit 153 does not transmit the data request signal even if an interrupt signal is received. However, the present invention is not particularly limited to this, and when the debug command includes information indicating that the first CPU unit 1 is debugged, the interrupt signal transmission unit 222 is set so as not to transmit the interrupt signal. It may be set.

  FIG. 5 is a block diagram showing a functional configuration of the first CPU unit 1 and the second CPU unit 2 when the interrupt signal transmission unit 222 is set not to transmit an interrupt signal. In FIG. 5, the description of the same configuration as that of the first CPU unit 1 and the second CPU unit 2 shown in FIG. 2 is omitted, and only a different configuration is described.

  The CPU 11 includes a debug execution unit 112 and a first debug setting unit 113. The communication unit 15 includes a start instruction signal transmission unit 151, an interrupt signal reception unit 152, a data request signal transmission unit 153, a debug data reception unit 154, and a setting signal transmission unit 155. The communication unit 22 includes a start instruction signal reception unit 221, an interrupt signal transmission unit 222, a data request signal reception unit 223, a debug data transmission unit 224, and a setting signal reception unit 225. The CPU 21 includes a debug data extraction unit 211, a determination unit 212, a debug data read unit 213, and a second debug setting unit 214.

  When the debug target is the second CPU unit 2, the first debug setting unit 113 instructs the start instruction signal transmission unit 151 to transmit a start instruction signal to the second CPU unit 2. In addition, when the debug target is the first CPU unit 1, the first debug setting unit 113 outputs a setting signal for setting the second CPU unit 2 not to transmit an interrupt signal to the setting signal transmission unit 155.

  The setting signal transmission unit 155 transmits the setting signal output by the first debug setting unit 113 to the second CPU unit 2. The setting signal receiving unit 225 receives the setting signal transmitted by the setting signal transmitting unit 155 of the first CPU unit 1. The setting signal receiving unit 225 outputs the received setting signal to the second debug setting unit 214. When the setting signal is received by the setting signal receiving unit 225, the second debug setting unit 214 sets the interrupt signal transmitting unit 222 not to transmit the interrupt signal.

  In the present embodiment, the first debug setting unit 113, the setting signal transmitting unit 155, the setting signal receiving unit 225, and the second debug setting unit 214 correspond to an example of a second setting unit.

  In this way, when the setting signal for setting the second CPU unit 2 not to transmit the interrupt signal is received by the setting signal receiving unit 225, the interrupt signal transmitting unit 222 is set not to transmit the interrupt signal. The Therefore, when debugging the first CPU unit 1, the interrupt signal is not transmitted from the second CPU unit 2 and the debug data is not transmitted from the second CPU unit 2. Therefore, the debug data in the first CPU unit 1 and the debug data in the second CPU unit 2 are not transmitted. Are not output at the same time, and only the first CPU unit 1 can be debugged.

1 is a block diagram showing an outline of a hardware configuration of an image forming apparatus which is an example of an information processing apparatus according to the present invention and a PC (personal computer) connected thereto. It is a block diagram which shows the function structure of a 1st CPU unit and a 2nd CPU unit. 3 is a flowchart for explaining a debugging operation by a first CPU unit and a second CPU unit shown in FIG. 2. FIG. 3 is a schematic diagram for explaining a specific debugging operation by the first CPU unit and the second CPU unit shown in FIG. 2. It is a block diagram which shows the function structure of a 1st CPU unit and a 2nd CPU unit in the case of setting an interrupt signal transmission part so that an interrupt signal may not be transmitted.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st CPU unit 2 2nd CPU unit 10 Image forming apparatus 11, 21, 31 CPU
12,23 ROM
13, 24, 33 RAM
14 Operation panel section 15, 16, 22, 32 Communication section 34 HDD
35 display device 36 input device 111 debug setting unit 112 debug execution unit 113 first debug setting unit 151 start instruction signal transmission unit 152 interrupt signal reception unit 153 data request signal transmission unit 154 debug data reception unit 155 setting signal transmission unit 161 debug command Reception unit 211 Debug data extraction unit 212 Judgment unit 213 Debug data reading unit 214 Second debug setting unit 221 Start instruction signal reception unit 222 Interrupt signal transmission unit 223 Data request signal reception unit 224 Debug data transmission unit 225 Setting signal reception unit 241 Transmission Buffer 242 Change status buffer

Claims (6)

An information processing apparatus in which a plurality of CPU units including a CPU that executes a program and a memory that stores the program are connected to be communicable with each other,
A first CPU unit having a debugging function for debugging a program executed by each CPU included in the plurality of CPU units;
A second CPU unit not having the debugging function,
The second CPU unit is
An extraction means for extracting data used for debugging;
Data transmission means for transmitting the data extracted by the extraction means to the first CPU unit;
The first CPU unit is
Data receiving means for receiving data transmitted by the data transmitting means;
An information processing apparatus comprising: execution means for executing a debugging function using data received by the data receiving means.   The information processing apparatus according to claim 1, wherein the extraction unit extracts data used for debugging by executing an output function for outputting data used for debugging from the program. The second CPU unit is
Storage means for storing data extracted by the extraction means;
Determination means for determining whether data is stored in the storage means;
An interrupt signal transmitting means for transmitting an interrupt signal to the first CPU unit when the determining means determines that data is stored in the storage means;
The first CPU unit is
Interrupt signal receiving means for receiving the interrupt signal transmitted by the interrupt signal transmitting means;
A data request signal transmitting means for transmitting a data request signal for requesting data to the second CPU unit when an interrupt signal is received by the interrupt signal receiving means;
The second CPU unit is
Data request signal receiving means for receiving the data request signal transmitted by the data request signal transmitting means;
A reading means for reading data stored in the storage means when a data request signal is received by the data request signal receiving means;
The information processing apparatus according to claim 1, wherein the data transmission unit transmits the data read by the reading unit to the first CPU unit. The first CPU unit further comprises command receiving means for receiving a command transmitted by an external device,
The command includes information specifying which of the first CPU unit and the second CPU unit to debug,
The first CPU unit further includes first setting means for setting not to transmit a data request signal by the data request signal transmitting means when the command includes information for debugging the first CPU unit. The information processing apparatus according to claim 3, further comprising: The first CPU unit further comprises command receiving means for receiving a command transmitted by an external device,
The command includes information specifying which of the first CPU unit and the second CPU unit to debug,
The second CPU unit further comprises second setting means for setting the interrupt signal transmission means not to transmit an interrupt signal when the command includes information for debugging the first CPU unit. The information processing apparatus according to claim 3. The information processing apparatus is an image forming apparatus that forms an image;
The first CPU unit includes a control unit that controls the entire image forming apparatus,
The information processing apparatus according to claim 1, wherein the second CPU unit includes an engine control unit that controls a drive source built in the image forming apparatus.

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