JP2007140849A - Microcontroller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output an interrupt signal to a master block from a slave block separated from a system bus. <P>SOLUTION: The synchronous outputting part 40 of the slave block 2 holds an interrupt factor signal INT from a function processing part 20 in synchronization with a bus clock BCK and outputs the interrupt factor signal, as a clock permission signal CKE, to a clock control part 30. When the clock permission signal CKE is given, the clock control part 30 supplies the bus clock BCK, as an internal clock CLK, to a bus interface part 10 and an interrupt outputting part 40 independently of a selection signal SEL to the slave block 2. By this, an interrupt outputting part 40 holds the clock permission signal CKE in synchronization with the internal clock CLK and outputs the clock permission signal CKE, as an interrupt request signal IRQ, to the master block 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a microcontroller in which a master block and a slave block are connected by a system bus, and more particularly, to an interrupt signal output from a non-selected slave block to a master block.

JP 2003-288278 A JP 2002-351825 A

  In the above-mentioned Patent Document 1, a microcontroller having a master block and a plurality of slave blocks and having a function of stopping the supply of a clock signal to each slave block is provided with a default slave block that is always supplied with a clock signal. The controller is listed. In this microcontroller, when the default slave block monitors the access to the slave block and detects access to the slave block for which the supply of the clock signal is stopped, it indicates that the access is abnormal on behalf of the slave block. A response signal is output. As a result, even when the slave block being stopped is accessed, the access operation of the master block can be stopped.

  On the other hand, in Patent Document 2 described above, it is detected that serial data transfer with the master block is not performed for a certain period of time, and a transition is made to a dormant state. A communication system is described that includes a slave block that returns to an active state upon receipt of. Thus, the slave block can be put into a dormant state during non-communication, so that power consumption can be reduced.

  In the systems described in Patent Documents 1 and 2, the slave block sleep / active control is performed from the master block, so that a signal such as a return request is output from the slave block in the sleep state to the master block. I can't. For this reason, for example, in the slave block such as a timer, the time monitoring after the time setting is performed is independently performed in the slave block, so the connection with the master block is unnecessary until the set time is reached. There is a problem that it cannot be separated from the master block because there is no time-out notification means.

  An object of the present invention is to output an interrupt signal to a master block from a slave block separated from the system bus in a microcontroller in which a master block and a slave block are connected by a system bus.

  In the present invention, in a microcontroller in which a master block and a slave block are connected via a system bus, the slave block performs processing based on an instruction from the master block based on a local clock, and a predetermined factor occurs. A function processing unit for outputting an interrupt factor signal having a predetermined logic level, and a bus interface for transferring a signal between the system bus and the function processing unit based on an internal clock independent of the local clock And an interrupt output unit that generates a clock permission signal having a logic level based on a logic level of the interrupt factor signal and outputs and holds an interrupt request signal to the master block in synchronization with the internal clock; The internal clock is selected according to the logic level of the selection signal for the slave block. Output of the clock, and the internal clock regardless of the logic level of the selection signal in response to the clock enable signal having become a logic level based on the interrupt factor signal of the predetermined logic level. And a clock control unit for outputting.

  When an interrupt factor signal is output from the function processing unit, the slave block of the present invention supplies the bus clock as an internal clock to the bus interface and the interrupt output unit regardless of the presence or absence of a selection signal for the slave block. A clock control unit is included. Therefore, even if the slave block is disconnected from the system bus, an interrupt request signal can be output to the master block.

  In the present invention, the slave block is provided with an edge detection unit that generates a pulse of one cycle width of the system clock when the output of the clock permission signal is started from the interrupt output unit. The permission signal is given to the clock controller. As a result, the number of internal clocks output until the interrupt factor is released is only one clock, and the power consumption of the slave block when not selected can be further reduced.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of a microcontroller showing Embodiment 1 of the present invention.
The microcontroller includes a master block 1 that performs overall control, a plurality of slave blocks (only one is shown in the figure) 2 that performs processing of a predetermined function based on an instruction from the master block 1, and a master block 1 An address decoder 3 that outputs a selection signal SEL for each slave block 2 based on an instruction, and a system bus 4 that commonly connects them are provided. The system bus 4 includes an address signal line for transmitting the address signal ADR output from the master block 1 to each block, a data signal line for transferring the data signal DATA bidirectionally between the master block 1 and each slave block 2, Control signal line for transferring the control signal CON and the bus clock BCK.

  The slave block 2 includes a bus interface unit 10, a function processing unit 20, a clock control unit 30, and an interrupt output unit 40.

  The bus interface unit 10 transfers the address signal ADR, the data signal DATA, and the control signal CON between the function processing unit 20 and the system bus 4 in synchronization with the internal clock CLK supplied from the clock control unit 30. It is. The bus interface unit 10 stops its operation when the internal clock CLK stops.

  The function processing unit 20 performs predetermined function processing such as time monitoring based on the local clock LCK asynchronous with the bus clock BCK, and continues to operate even when the bus interface unit 10 is stopped. Yes. The function processing unit 20 outputs an interrupt factor signal INT when a predetermined interrupt factor occurs, for example, when a predetermined time has elapsed.

  When the selection signal SEL for selecting the slave block 2 from the address decoder 3 (in this embodiment, the selection signal SEL of the level “H”) is given from the address decoder 3, the clock control unit 30 generates the internal clock CLK corresponding to the bus clock BCK. When the selection signal SEL is not supplied (in this embodiment, when the selection signal SEL is at the level “L”), the output of the internal clock CLK is stopped. However, the clock control unit 30 outputs the internal clock CLK regardless of the selection signal SEL according to the clock permission signal CKE from the interrupt output unit 40 when the interrupt factor signal INT is output from the function processing unit 20. It is supposed to be. The internal clock CLK is supplied to the bus interface unit 10 and the interrupt output unit 40.

  The clock control unit 30 includes, for example, a NOR gate 31 that takes the logical sum of the clock enable signal CKE output from the interrupt output unit 40 and the selection signal SEL provided from the address decoder 3 and outputs an inverted signal thereof, The OR gate 32 is configured to output the logical sum of the signal S31 output from the NOR gate 31 and the bus clock BCK as the internal clock signal CLK.

  When the interrupt factor signal INT is output from the function processing unit 20, the interrupt output unit 40 holds the interrupt factor signal INT in synchronization with the bus clock BCK and uses the clock control unit 30 as a clock permission signal CKE. The interrupt request signal IRQ is held and output to the master block 1 in synchronization with the internal clock CLK supplied from the clock controller 30. The interrupt request signal IRQ is directly given to the master block 1 without going through the system bus 4.

  The interrupt output unit 40 is composed of, for example, cascade-connected D-type flip-flops 41, 42, and 43, and the interrupt factor signal INT from the function processing unit 20 is input to the input terminal D of the first-stage flip-flop 41. Is given. A bus clock BCK is supplied to the clock terminal C of the flip-flops 41 and 42, and a clock permission signal CKE is output from the output terminal Q of the flip-flop 42. The clock terminal C of the flip-flop 43 is supplied with the internal clock CLK from the clock control unit 30, and the interrupt request signal IRQ is output from the output terminal Q of the flip-flop 43.

  FIG. 2 is a signal waveform diagram showing the operation of FIG. Hereinafter, the operation of FIG. 1 will be described focusing on the slave block 2 with reference to FIG.

  When the selection signal SEL for the slave block 2 is activated by the address decoder 3 and becomes “H”, the signal S31 of the clock control unit 30 becomes “L”, and the bus interface BCK is used as the internal clock CLK. 10 and the interrupt output unit 40. Thus, the address signal ADR, the data signal DATA, and the control signal CON are transferred between the system bus 4 and the function processing unit 20 in synchronization with the bus clock BCK.

  In the function processing unit 20, predetermined function processing is performed based on the local clock LCK in accordance with an instruction given from the master block 1. When a predetermined factor is generated in the function processing unit 20 and the interrupt factor signal INT becomes “H”, the interrupt factor signal INT is synchronized with the bus clock BCK by the interrupt output unit 40, and the interrupt factor signal INT is interrupted. Is input to the master block 1 as a request signal IRG.

  Here, for example, it is assumed that after the master block 1 instructs the slave block 2 to monitor for a certain time, the selection signal SEL for the slave block 2 is stopped and becomes “L”. At this time, it is assumed that a predetermined factor is not generated in the function processing unit 20 of the slave block 2 and the interrupt factor signal INT is “L”.

  In this state, as shown at time t 1 in FIG. 2, the signal S 31 of the clock control unit 30 is “H”, the output of the OR gate 32 is fixed to “H”, and the internal clock CLK is sent to the bus interface unit 10. Supply is stopped. As a result, the operation of the bus interface unit 10 is stopped. On the other hand, the function processing unit 20 continues time monitoring based on the local clock LCK.

  When the function processing unit 20 detects that the monitoring time has elapsed at time t2, the interrupt factor signal INT becomes “H”. As a result, the output signal of the flip-flop 41 becomes “H” at the next rise timing of the bus clock BCK.

  When the bus clock BCK rises at time t3, the clock enable signal CKE output from the flip-flop 42 becomes “H”. As a result, the signal S31 of the clock control unit 30 becomes “L”, a signal corresponding to the bus clock BCK is output from the OR gate 32 as the internal clock CLK, and the operation of the bus interface unit 10 is resumed.

  When the internal clock CLK rises at time t4, the clock permission signal CKE is held in the flip-flop 43 of the interrupt output unit 40, and the interrupt request signal IRQ becomes “H”. Thereby, in the master block 1, the interrupt request signal IRQ from the slave block 2 is detected, and predetermined processing is performed in response to the interrupt request. Then, for example, a response indicating that the interrupt request has been accepted is returned from the master block 1 to the slave block 2.

  When the interrupt factor signal INT is canceled by the function processing unit 20 of the slave block 2 at time t5, the interrupt output unit 40 synchronizes with the second rise of the internal clock signal CLK at time t6. Becomes “L”. As a result, the output of the OR gate 32 is fixed to “H”, and the supply of the internal clock CLK to the bus interface unit 10 is again stopped.

  As described above, in the slave block 2 in the microcontroller of the first embodiment, when the interrupt factor signal INT is output from the function processing unit 20, regardless of the selection signal SEL for the slave block 2, the bus clock BCK The clock control unit 30 supplies the bus interface unit 10 and the interrupt output unit 40 with the internal clock CLK. Therefore, even if the slave block 2 is disconnected from the system bus 4, there is an advantage that the interrupt request signal IRQ can be output to the master block 1.

In addition, this invention is not limited to the said Example 1, A various deformation | transformation is possible. Examples of this modification include the following.
(1) The bus interface unit 10 may be configured not only to transfer the address signal ADR, the data signal DATA, and the control signal CON but also to perform a predetermined functional operation in synchronization with the internal clock CLK.
(2) The configuration of the clock control unit 30 is not limited to the illustrated circuit, and any circuit having the same function may be used. For example, instead of the NOR gate 31 and the OR gate 32, an OR gate and an AND gate may be used, respectively.
(3) The configuration of the interrupt output unit 40 is not limited to the illustrated circuit, and any circuit having a similar function may be used. For example, the flip-flop 42 can be deleted.

FIG. 3 is a configuration diagram of a slave block showing the second embodiment of the present invention.
In the constituent elements of the slave block in FIG. 3, elements common to those in FIG. 1 are denoted by common reference numerals.

  In this slave block, the clock permission signal CKE output from the interrupt output unit 40 is supplied to the clock control unit 30 via the edge detection unit 50.

  The edge detection unit 50 generates an edge detection signal EDG having a pulse width corresponding to one cycle of the bus clock BCK and supplies it to the clock control unit 30 when the clock permission signal CKE rises. The edge detection unit 50 includes, for example, a D-type flip-flop 51 and an AND gate 52 that operate in synchronization with the bus clock BCK. The clock enable signal CKE is supplied to the input terminal D of the flip-flop 51 and one input terminal of the AND gate 52. The inverting output terminal / Q of the flip-flop 51 is connected to the other input terminal of the AND gate 52, and the edge detection signal EDG is output from the AND gate 52 and supplied to the NOR gate 31 of the clock control unit 30. ing. Other configurations are the same as those in FIG.

FIG. 4 is a signal waveform diagram showing the operation of FIG.
At time T0 in FIG. 4, since the slave block is disconnected from the system bus 4, the selection signal SEL for this slave block is stopped and becomes “L”, and the function processing unit 20 generates a predetermined factor. The interrupt factor signal INT is “L”.

  At time T1, when a predetermined factor occurs in the function processing unit 20 and the interrupt factor signal INT becomes “H”, the output signal of the flip-flop 41 becomes “H” at the next rising timing of the bus clock BCK. .

  At the second rise of the bus clock BCK at time T2, the clock enable signal CKE of the flip-flop 42 becomes “H”. As a result, the edge detection signal EDG becomes “H”, and the signal S31 of the clock control unit 30 becomes “L”.

  When the bus clock BCK falls at time T3, the internal clock CLK output from the OR gate 32 also becomes “L”.

  When the bus clock BCK rises at time T4, the internal clock CLK output from the OR gate 32 also becomes “H”. With the rise of the internal clock CLK, the clock enable signal CKE is held in the flip-flop 43, and the interrupt request signal IRQ becomes “H”. On the other hand, with the rise of the bus clock BCK at time T4, the inverted output terminal / Q of the flip-flop 51 becomes “L”, and the edge detection signal EDG returns to “L”. As a result, the signal S31 becomes “H”, the output of the OR gate 32 is fixed to “H”, and the internal clock CLK is stopped again.

  As described above, the slave block according to the second embodiment generates the edge detection signal EDG having a pulse width corresponding to one cycle of the bus clock BCK and supplies it to the clock controller 30 when the clock enable signal CKE rises. An edge detection unit 50 is provided. Therefore, the internal clock CLK output when an interrupt factor occurs is only one cycle. As a result, the number of internal clocks CLK output until the interrupt factor is canceled is smaller than that of the first embodiment, and in addition to the same advantages as those of the first embodiment, the power consumption of the slave block when not selected is further increased. There is an advantage that it can be reduced.

It is a block diagram of the microcontroller which shows Example 1 of this invention. It is a signal waveform diagram which shows the operation | movement of FIG. It is a block diagram of the slave block which shows Example 2 of this invention. FIG. 4 is a signal waveform diagram illustrating the operation of FIG. 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Master block 2 Slave block 3 Address decoder 4 System bus 10 Bus interface part 20 Function processing part 30 Clock control part 40 Interrupt output part 50 Edge detection part

Claims (6)

In the microcontroller where the master block and slave block are connected via the system bus,
The slave block is
A function processing unit that performs processing based on an instruction from the master block based on a local clock, and outputs an interrupt factor signal having a predetermined logic level when a predetermined factor occurs;
A bus interface unit for transferring a signal between the system bus and the function processing unit based on an internal clock independent of the local clock; and a clock permission signal having a logic level based on a logic level of the interrupt factor signal. An interrupt output unit for generating and outputting an interrupt request signal to the master block in synchronization with the internal clock; and
The output of the internal clock is controlled in accordance with the logic level of the selection signal for the slave block, and the clock permission signal has become a logic level based on the interrupt factor signal of the predetermined logic level. A clock controller that outputs the internal clock regardless of the logic level of the selection signal,
A microcontroller comprising:   The clock control unit receives a system clock independent of the local clock and is controlled by the selection signal and the clock permission signal so that the system clock is output as the internal clock. The microcontroller according to claim 1, wherein:   The interrupt control unit holds the interrupt factor signal based on the system clock and generates the clock permission signal, and the interrupt based on the clock permission signal based on the internal clock. The microcontroller according to claim 1, further comprising a second portion that generates a request signal.   The clock control unit receives the selection signal and the clock permission signal, and when the selection signal is at a logic level indicating that the slave block is selected or when the clock permission signal is at the predetermined logic level 4. The microcontroller according to claim 2, comprising a logic circuit that outputs the system clock as the internal clock when having a logic level based on the interrupt factor signal.   The clock control unit receives the selection signal and the clock permission signal, and when the selection signal is at a logic level indicating that the slave clock is selected or when the clock permission signal is at the predetermined logic level 3. A logic circuit that outputs the system clock as the internal clock when an edge detection signal is generated in response to a change to a logic level based on an interrupt factor signal of claim 2. 3. The microcontroller according to 3.   6. The microcontroller according to claim 1, further comprising a decoder that is connected to the system bus and generates the selection signal for the slave block based on address information from the system bus. The microcontroller described in

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