JP2007134696A - Composition of polishing solution for semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a composition of a polishing solution for a semiconductor substrate whereby ceria particles are dispersed with high stability, a high-concentration product of stable quality can be prepared, the ability to selectively polish a recess is provided when the polishing solution is diluted, the influence of the density or size of an uneven pattern is small, that is, high flatness with low dependence on a pattern can be quickly obtained with a small amount of polishing, and defects can be reduced after polishing. <P>SOLUTION: The composition of the polishing solution for a semiconductor substrate contains dihydroxyethyl glycine, ceria particles, a disperser, and an aqueous medium, wherein the content of the ceria particles is 2 wt.% to 22 wt.% and the content of the disperser is 0.001 wt.% to 1.0 wt.%. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a polishing composition for a semiconductor substrate, a method for polishing a semiconductor substrate using the polishing composition for a semiconductor substrate, and a method for manufacturing a semiconductor device having a polishing step by the polishing method.

  The semiconductor substrate polishing liquid is manufactured as a high-concentration product in order to reduce the cost of manufacturing equipment and transportation, and is preferably diluted to a predetermined concentration during use. Therefore, there is a demand for a polishing liquid that is more excellent in dispersion stability.

In particular, ceria (cerium oxide) particles widely used as an abrasive in such polishing liquids are likely to settle from the beginning because their specific gravity is as large as about 7.3 g / cm ³ . Furthermore, the additive added to impart flattening performance tends to promote aggregation of ceria particles, accelerate sedimentation, and reduce dispersion stability. As a result, sedimentation in the polishing liquid supply pipe and clogging of the filter occur, which causes an increase in scratches.

  As a technique for making ceria particles difficult to settle, it is known to select a polyacrylic acid copolymer as an additive (Patent Document 1). However, in this polishing liquid, since the addition amount of the copolymer is small, when polishing the surface to be polished having uneven steps, not only the convex portions but also the concave portions are polished, so that dishing occurs and the flatness is increased. A semiconductor substrate cannot be obtained.

On the other hand, in the recent semiconductor field, high integration and high speed have been advanced, and in particular, high integration requires the miniaturization of wiring. As a result, in the manufacturing process of a semiconductor substrate, the depth of focus at the time of exposure of the photoresist becomes shallow, and further surface flatness is desired. In addition, as integration and miniaturization progress, circuit defects occur due to the presence of defects (also referred to as defects) on the wafer surface after polishing, and the yield of non-defective chips decreases. Even more required.

In such a semiconductor substrate manufacturing process, for example, a wiring formation process or a buried element separation process, a large number of fine irregularities having various widths exist on the substrate due to the formation of wiring or embedding grooves. There is a demand for flattening the steps and reducing defects.

  When polishing the uneven step on the surface of the substrate, if a polishing liquid containing only an abrasive is used, the convex portion is polished quickly, but the concave portion is also polished at the same time. It takes time, and there is a problem that a considerable amount of the member on the surface to be polished needs to be polished.

With respect to the above problems, the prior art attempts to improve planarization ability by adding a low-molecular additive such as aspartic acid (for example, Patent Document 2).
JP 2000-17195 A JP 2001-7059 A

  However, in the polishing composition described in Patent Document 2, the above-mentioned dispersion stability of the ceria particles is not sufficient, and an effective improvement measure has not been presented. The object of the present invention is to produce a high-concentration product with excellent dispersion stability of ceria particles, stable quality, and imparting selective polishing performance of convex portions when used diluted, and the density or size of the concave-convex pattern Polishing liquid composition for semiconductor substrate capable of promptly achieving high level planarization with little pattern dependency and less defects after polishing, and capable of reducing defects after polishing, and polishing liquid for semiconductor substrate An object of the present invention is to provide a method for polishing a semiconductor substrate using the composition, and a method for manufacturing a semiconductor device having a polishing step by the polishing method.

That is, the present invention
[1] A polishing liquid composition for a semiconductor substrate containing dihydroxyethylglycine, ceria particles, a dispersant and an aqueous medium, wherein the content of ceria particles in the polishing liquid composition is 2 to 22% by weight, a dispersing agent A polishing composition for a semiconductor substrate having a content of 0.001 to 1.0% by weight,
[2] A polishing composition for a semiconductor substrate obtained by blending dihydroxyethylglycine, ceria particles, a dispersant and an aqueous medium, wherein 2 to 22% by weight of ceria particles are contained in the polishing composition. Is a polishing composition for a semiconductor substrate obtained by blending 0.001 to 1.0% by weight and an aqueous medium,
[3] A step of supplying a liquid obtained by diluting the polishing composition for a semiconductor substrate according to [1] or [2] to the substrate at a supply rate of 0.01 to 10 g / min per 1 cm ^{2 of the} substrate to be polished. A method for polishing a semiconductor substrate, and [4] a method for manufacturing a semiconductor device comprising a step of polishing a substrate to be polished by the polishing method according to [3],
About.

  According to the present invention, high-concentration products with excellent dispersion stability of ceria particles and stable quality can be produced, and when used by diluting, selective polishing performance of convex portions is imparted, and the influence of density or size of the concave-convex pattern A polishing composition for a semiconductor substrate that can be easily subjected to high level planarization with a small amount of polishing and that can reduce defects after polishing, and the polishing composition for a semiconductor substrate, which is less susceptible to patterning, i.e., less dependent on a pattern, can be achieved. A method for polishing a semiconductor substrate and a method for manufacturing a semiconductor device having a polishing step by the polishing method can be provided.

  The semiconductor substrate polishing liquid composition of the present invention (hereinafter sometimes simply referred to as “polishing liquid composition”), as described above, contains dihydroxyethylglycine, ceria particles, a dispersant, and an aqueous medium. A polishing liquid composition having a ceria particle content of 2 to 22% by weight and a dispersant content of 0.001 to 1.0% by weight in the polishing liquid composition. is there. By having such a configuration, the present invention can produce a high-concentration product having excellent dispersion stability of ceria particles and stable quality, and imparting selective polishing performance of convex portions when used by diluting. There is an effect that it is difficult to be influenced by the density or size of the pattern, that is, it is possible to quickly achieve high leveling with less pattern dependency with a small amount of polishing.

〔mechanism〕
The reason why the polishing composition of the present invention exhibits high planarization performance and excellent dispersion stability of ceria particles is because the following mechanism is caused by the coexistence of ceria particles and dihydroxyethylglycine. It is estimated to be.
Dihydroxyethylglycine has an anion group, a cation group, and a nonion group in a balanced state in the molecule, so that even if adsorbed on ceria particles, the zeta potential and hydrophilicity of the particles are not greatly reduced. It is estimated that it is difficult to affect the effect. Furthermore, since there is no cross-linking effect between ceria particles like a polymer compound, it is estimated that the dispersion stability of ceria particles is excellent even when added at a high concentration.
On the other hand, when the polishing composition is applied to a semiconductor substrate, dihydroxyethylglycine is adsorbed on the surface of ceria particles and / or the surface of the film to be polished to form a film. The film formed on the surface inhibits the action of ceria particles on the surface of the film to be polished and suppresses the progress of polishing. However, when a high polishing load is applied, the adsorbed film of dihydroxyethylglycine breaks, and the ceria particles can act on the surface of the film to be polished, so that polishing proceeds. Therefore, when polishing a film to be polished having uneven steps, a high polishing load acts locally on the convex part, so the adsorption film breaks and polishing proceeds, and conversely, the concave part has a locally low load and adsorbs. The film is protected and polishing does not proceed. Therefore, only the convex portion is selectively polished, and the uneven step is efficiently reduced.
Further, when the polishing progresses and the uneven step is reduced, the local load applied to the convex portion and the concave portion approaches the set load. Therefore, by setting the conditions so that the polishing hardly progresses with the set load in advance, the characteristic polishing characteristic (after the convex part / after flattening) that the polishing hardly progresses after the uneven step is eliminated (after flattening). (Polishing selection ratio) can be expressed.
As a result, an excellent effect is achieved that high level planarization with little pattern dependency and a small amount of polishing can be achieved quickly. This effect is significant when the film on the surface of the semiconductor substrate contains at least silicon, particularly when silicon oxide is included.

(1) Polishing liquid composition [ceria particles]
Examples of the ceria particles used in the present invention include ceria particles prepared by various synthesis methods. Examples of this synthesis method include a firing method, a hydrothermal synthesis method, a salt / catalyst method, a gas phase method (PSV method), etc. Among them, from the viewpoint of polishing rate, carbonates, sulfates, oxalates, etc. A firing method in which a cerium compound is fired to obtain cerium oxide (ceria) is preferred.

  The volume average particle diameter of the ceria particles is preferably 30 nm or more from the viewpoint of polishing rate, and is preferably 1000 nm or less from the viewpoint of dispersion stability of the ceria particles in the aqueous medium and prevention of sedimentation separation. The volume average particle diameter of the ceria particles is preferably 30 to 1000 nm, more preferably 40 to 500 nm, still more preferably 50 to 160 nm, and still more preferably 50 to 140 nm. The volume average particle diameter is a volume-based median diameter measured in a diluted state while ultrasonically dispersing with a laser diffraction / scattering particle size distribution analyzer (LA-920, manufactured by Horiba, Ltd.).

  In addition, the average primary particle diameter (crystallite size) of the ceria particles is preferably 5 nm or more from the viewpoint of polishing rate, and is preferably 100 nm or less from the viewpoint of suppressing generation of scratches on the polished surface. The average primary particle diameter of the ceria particles is preferably 5 to 100 nm, more preferably 10 to 50 nm, and still more preferably 20 to 40 nm. Examples of the method for measuring the average primary particle diameter of the ceria particles include a method for obtaining a spherical particle shape from the specific surface area obtained by the BET method, and an X-ray diffraction method.

The content of the ceria particles in the polishing liquid composition is 2% by weight or more from the viewpoint of production and transportation costs, and from the viewpoint of dispersion stability of the ceria particles in the aqueous medium and prevention of sedimentation separation,
22% by weight or less. Accordingly, the content is 2 to 22% by weight, preferably 2 to 15% by weight, more preferably 2.5 to 12% by weight, still more preferably 3 to 10% by weight, and even more preferably 3 to 8% by weight. is there.
The content of ceria particles in the polishing composition when diluted at the time of use is preferably 0.1% by weight or more, more preferably 0.2% by weight or more from the viewpoint of polishing rate, and 0.4 % By weight or more is more preferable, and 0.5% by weight or more is even more preferable. Further, from the viewpoint of dispersion stability and cost of the ceria particles in the aqueous medium, the content is preferably 8% by weight or less, more preferably 5% by weight or less, further preferably 4% by weight or less, and 3% by weight. The following are even more preferred: Accordingly, the content in use is preferably 0.1 to 8% by weight, more preferably 0.2 to 5% by weight, further preferably 0.4 to 4% by weight, and further 0.5 to 3% by weight. More preferred.

[Dihydroxyethylglycine]
The content of dihydroxyethyl glycine in the polishing liquid composition is preferably 0.4% by weight or more from the viewpoint of production and transportation costs. Also, the viewpoint of dispersion stability of ceria particles in an aqueous medium and prevention of sedimentation separation. Therefore, 40% by weight or less is preferable. Therefore, the content is preferably 0.4 to 40% by weight, more preferably 1 to 20% by weight, still more preferably 2 to 15% by weight, and even more preferably 3 to 12% by weight.
The content of dihydroxyethyl glycine in the polishing composition when diluted at the time of use is preferably 0.2% by weight or more and preferably 10% by weight or less from the viewpoint of planarization performance. Therefore, the content is preferably 0.2 to 10% by weight, more preferably 0.5 to 8% by weight, and further preferably 1 to 6% by weight.

  Further, other components can be contained within the range not impairing the effects of the present invention, but from the viewpoint of planarization performance, the content of dihydroxyethylglycine is determined from the polishing composition of the present invention to the aqueous medium and ceria. In the component excluding the particles, 80% by weight or more is preferable, 90% by weight or more is more preferable, 95% by weight or more is further preferable, and 97% by weight or more is more preferable. Further, the content of dihydroxyethylglycine is preferably 99.98% by weight or less, and more preferably 99.97% by weight or less. Accordingly, the content is preferably 80 to 99.98% by weight, more preferably 90 to 99.98% by weight, still more preferably 95 to 99.98% by weight, and even more preferably 97 to 99.97% by weight. is there.

[Dihydroxyethylglycine and ceria particle content ratio (weight ratio)]
In the polishing composition of the present invention, the content ratio (weight ratio) of the dihydroxyethylglycine / ceria particles is preferably 1/5 or more, more preferably 1/4 or more, from the viewpoint of dishing prevention and defect reduction. 1/3 or more is more preferable. Further, from the viewpoint of the flattening speed, 15/1 or less is preferable, 12/1 or less is more preferable, and 10/1 or less is more preferable.
Therefore, the content ratio (weight ratio) of dihydroxyethylglycine / ceria particles is preferably 1/5 to 15/1, more preferably 1/4 to 12/1, and still more preferably 1/3 to 10/1.

[Dispersant]
Examples of the dispersant include surfactants such as anionic surfactants and nonionic surfactants, or polymer dispersants such as acrylic acid copolymers and ethylene oxide-propylene oxide block copolymers (pluronics). Is mentioned. Among these, from the viewpoint of the dispersion effect, acrylic acid copolymers, particularly polyacrylic acid or salts thereof are preferable, and the weight average molecular weight is preferably 1000 to 10,000, and more preferably 1000 to 6000. Here, the weight average molecular weight is a value measured by the following gel permeation chromatography (GPC) method.
<GPC conditions>
Column: G4000PWXL + G2500PWXL (manufactured by Tosoh Corporation)
Eluent: 0.2M phosphate buffer / CH ₃ CN = 9/1
Flow rate: 1.0 mL / min
Column temperature: 40 ° C
Detection: RI
Reference material: Polyacrylic acid equivalent

In addition, the content of the dispersant in the polishing liquid composition is 0.001 to 1.0% by weight, preferably 0.003 to 0.3% by weight, and more preferably 0.005 to 0.1% by weight from the viewpoint of obtaining an appropriate dispersion effect.
The content of the dispersant in the polishing composition when diluted at the time of use is preferably 0.0005 to 0.5% by weight, more preferably 0.001 to 0.1% by weight from the viewpoint of the dispersion effect.
From the viewpoint of the dispersion effect, preferred salts of the acrylic acid copolymer include ammonium salts, tetramethylammonium salts, water-soluble amine salts, potassium salts, and more preferably ammonium salts.

[Aqueous medium]
In the present invention, the aqueous medium refers to water and a mixed medium of water and a solvent (alcohol or the like) that can be mixed with water. As the aqueous medium, it is preferable to use water such as ion exchange water.
The content of the aqueous medium in the polishing composition is preferably 60 to 97.599% by weight from the viewpoint of improving the polishing rate and from the viewpoint of dispersion stability and prevention of sedimentation separation in the aqueous medium of the ceria particles. 70 to 96% by weight is more preferable.
As the content of the aqueous medium in the polishing liquid composition when diluted at the time of use, from the viewpoint of improving the polishing rate and dispersion stability of the ceria particles in the aqueous medium and prevention of sedimentation separation, 80 to 99.6995 weight% is preferable and 85-99 weight% is more preferable.

[Method for preparing polishing liquid composition]
The polishing liquid composition of the present invention can be prepared by blending the above-mentioned ceria particles, dihydroxyethyl glycine, a dispersant, and, if desired, optional components described later into an aqueous medium. Above all, from the viewpoint of dispersion stability of ceria particles at the time of blending, an aqueous dispersion (ceria slurry) containing ceria particles or ceria particles and a dispersant is prepared in advance, and an aqueous solution in which this ceria slurry and dihydroxyethylglycine are dissolved Is preferably mixed and stirred. Alternatively, a method of mixing the ceria slurry and the dihydroxyethylglycine aqueous solution after preparing each in advance to a set pH before mixing, or a method of adjusting to a set pH after mixing can be used.

[Preparation of ceria slurry]
The ceria slurry can be prepared by performing a dispersion treatment. Examples of the dispersion treatment include a method of dispersing with a stirrer such as a homomixer, a homogenizer, an ultrasonic disperser, or a wet ball mill. In addition, from the viewpoint of dispersibility of the ceria particles, it is preferable to use the above dispersant in combination during the dispersion treatment. The pH of the ceria slurry is preferably adjusted to 3-10.

  It is preferable to remove coarse particles from the ceria slurry obtained as described above. Examples of the method for removing the coarse particles include a centrifugal separation method and a filter filtration method after the dispersion treatment.

  Moreover, it is preferable that pH of the aqueous solution which melt | dissolved dihydroxyethylglycine is adjusted to 3-10.

[Optional ingredients]
Further, in the polishing liquid composition of the present invention, as an optional component (additive), benzalkonium chloride, benzethonium chloride, 1,2-benzisothiazolin-3-one, (5-chloro-) 2-methyl-4 -Preservatives such as isothiazoline-3-one, hydrogen peroxide and hypochlorite may be mixed. Moreover, oxidizing agents, such as a peroxide or permanganic acid, chromic acid, nitric acid, peroxo acid, or those salts, can be mixed. In addition, as chelating agents other than dihydroxyethylglycine, ethylenediaminetetraacetic acid (EDTA), cyclohexanediaminetetraacetic acid (CyDTA), nitrilotriacetic acid (NTA), hydroxyethylethylenediaminetriacetic acid (HEDTA), diethylenetriaminepentaacetic acid (DTPA), Ethylenetetramine hexaacetic acid (TTHA), L-glutamic acid diacetic acid (GLDA), aminotri (methylenephosphonic acid), 1-hydroxyethylidene 1,1-diphosphonic acid, ethylenediaminetetra (methylenephosphonic acid), diethylenetriaminepenta (methylenephosphonic acid) , Β-alanine diacetic acid (β-ADA), α-alanine diacetic acid (α-ADA), aspartic acid diacetic acid (ASDA), ethylenediaminenicosuccinic acid (EDDS), iminodiacetic acid IDA), hydroxyethyliminodiacetic acid (HEIDA), 1,3-propanediaminetetraacetic acid (1,3-PDTA), malic acid, tartaric acid, gluconic acid, citric acid, aspartic acid, glutamic acid, glycine, 4-aminobutyric acid Arginine, phthalic acid, and the like can be mixed as long as the effects of the present invention are not impaired. These optional components may be mixed in either the ceria slurry or the dihydroxyethylglycine aqueous solution.
The above optional components can be added within a range not impairing the effects of the present invention. The amount of such optional components is preferably 0.001 to 1.0% by weight in the polishing composition, and 0.01 to 0. More preferred is 5% by weight.

[PH of polishing composition]
The pH range of the polishing composition of the present invention obtained by the method as described above is preferably 3 to 10, more preferably 4 to 8, still more preferably 4.5 to 7, from the viewpoint of polishing rate. To 7 is more preferable, and 5.8 to 6.5 is more preferable.

  The pH of the polishing composition can be adjusted with a pH adjuster. pH adjusters include basic substances such as ammonia, potassium hydroxide, water-soluble organic amines, quaternary ammonium hydroxides, inorganic acids such as nitric acid, hydrochloric acid, sulfuric acid, phosphoric acid, and acetic acid, oxalic acid, succinic acid, glycol Acid substances such as organic acids such as acid, malic acid, citric acid, and benzoic acid can be mentioned.

The polishing composition of the present invention is preferably used after being diluted. The dilution factor is preferably 1.5 times or more, more preferably 2 times or more, further preferably 3 times or more, further preferably 4 times or more, from the viewpoint of production / transport costs, and from the viewpoint of polishing rate, It is preferably 20 times or less, more preferably 15 times or less, further preferably 10 times or less, and further preferably 8 times or less. Accordingly, the dilution ratio when using the polishing composition of the present invention is preferably 1.5 to 20 times, more preferably 2 to 15 times, further preferably 2 to 10 times, and further preferably 2 to 8 times.
As a dilution method, a method of adding a predetermined amount of an aqueous medium to the polishing composition of the present invention and stirring and mixing can be used. More specifically, a method of taking the polishing composition of the present invention in a tank before polishing and adding a predetermined amount of the aqueous medium to the tank and stirring and mixing, or a method of adding an aqueous medium separately from the polishing liquid of the present invention during polishing. Can be used.

[Semiconductor substrate]
The polishing composition of the present invention is used for polishing a semiconductor substrate.
The semiconductor substrate in the present invention will be described in detail later, but the material thereof is a metal or semi-metal such as silicon, aluminum, nickel, tungsten, copper, tantalum, and titanium, and an alloy or glass mainly composed of these metals. Glassy materials such as glassy carbon and amorphous carbon, ceramic materials such as alumina, silicon dioxide, silicon nitride, tantalum nitride, and titanium nitride, and resins such as polyimide resin. Among them, those in which a film including silicon and having an uneven step shape is formed on the substrate surface are preferable. As a film containing silicon, TEOS (Tetraethoxysilane), silicon oxide such as quartz and glass, oxidation such as phosphorus and boron such as BPSG (Boro-Phospho-Silicate Glass) and PSG (Phospho-Silicate Glass) are doped. Examples thereof include silicon, silicon nitride, and polysilicon. In particular, when the polishing composition of the present invention is used when polishing a semiconductor substrate having a film to be polished containing silicon dioxide as a main component, planarization can be realized efficiently.
In the case of silicon oxide doped with elements such as phosphorus and boron, such as BPSG and PSG, more additives need to be added in order to achieve planarization performance compared to a normal silicon oxide film. However, the higher the concentration of the additive, the easier it is for the ceria particles to aggregate and settle due to the salting-out effect and the like, and therefore the polishing liquid composition of the present invention having better dispersion stability is more preferably used.

Especially, the polishing liquid composition of this invention is suitable for the grinding | polishing performed in order to planarize the semiconductor substrate which has 50-2000 nm, Preferably it is 100-1500 nm. The uneven step can be obtained by a profile measuring device (for example, trade name: HRP-100, manufactured by KLA-Tencor).
The “concavo-convex step shape” of the present invention refers to a film in which at least a silicon-containing film is patterned on the surface of a semiconductor substrate so as to form an uneven step. For example, as a semiconductor substrate having the above film, silicon nitride is formed on a silicon substrate by a CVD (Chemical Vapor Deposition) method, etched, patterned, and further HDP-TEOS (High-density plasma tetraethoxysilane). ) What is patterned in the uneven step formed when the silicon oxide film is formed. Similarly, the silicon substrate may be etched and patterned, and further patterned into uneven steps formed when BPSG (Boro-Phospho-Silicate Glass) is formed thereon. In these cases, the depth of patterning at the time of the previous etching is reflected in the “uneven step shape” of the silicon-containing film on the surface of the semiconductor substrate. In the examples described later, silicon nitride is etched after the CVD method is formed or before BPSG (Boro-Phospho-Silicate Glass) is formed. This is reflected in the “uneven step shape” of the silicon-containing film on the surface of the semiconductor substrate.
In particular, when the uneven step is made of the same member, the polishing liquid composition of the present invention exhibits an excellent effect that the convex portion can be quickly polished and flattened.

(2) Polishing Method The polishing method of the present invention includes a step of supplying a liquid obtained by diluting the above polishing liquid composition to the substrate at a supply rate of 0.01 to 10 g / min per 1 cm ^{2 of the} substrate to be polished. A method for polishing a semiconductor substrate may be mentioned.

[Polishing composition supply speed]
The supply rate of the polishing composition (dilution solution) is 0.01 g / min or more, preferably 0.1 g / min from the viewpoint of maintaining a high polishing rate per 1 cm ^{2 of the} substrate to be polished and flattening in a short time. From the viewpoints of economy and waste liquid treatment, it is 10 g / min or less, preferably 5 g / min or less. Therefore, the supply rate is 0.01 to 10 g / min, preferably 0.1 to 5 g / min.

[Polishing load]
The polishing load is preferably 5 kPa or more, more preferably 10 kPa or more from the viewpoint of the polishing rate, and preferably 100 kPa or less, more preferably 70 kPa or less, from the viewpoint of flattening the polished surface and suppressing scratches. More preferably, it is 50 kPa or less. Therefore, the polishing load is preferably 5 to 100 kPa, more preferably 10 to 70 kPa, and still more preferably 10 to 50 kPa.

  As a liquid obtained by diluting the polishing liquid composition, for example, a liquid obtained by diluting the above polishing liquid composition at the above-described preferable dilution ratio may be used.

  There is no restriction | limiting in particular as a semiconductor substrate polishing apparatus using the polishing liquid composition (dilution liquid) of this invention, Polishing provided with the jig | tool and polishing cloth (polishing pad) which hold | maintain the to-be-polished object represented by the semiconductor substrate. A device is used. As a specific example of a polishing method using the polishing apparatus, as a polishing cloth, a jig for holding the object to be polished on a surface plate on which an organic polymer foam, non-foam, non-woven polishing cloth or the like is attached. The object to be polished is sandwiched between a surface plate pressed with a tool or a polishing cloth, the polishing composition of the present invention is supplied to the surface of the object to be polished, and a constant pressure (load) is applied while applying a constant pressure (load). The method of grind | polishing the to-be-polished object surface by moving to-be-polished object is mentioned.

  The polishing conditions other than the supply amount of the polishing composition and the polishing load are not particularly limited.

(3) Manufacturing Method of Semiconductor Device Generally, a semiconductor device such as a memory IC, a logic IC, or a system LSI forms an insulating film such as silicon oxide on a single crystal substrate (wafer) typified by silicon. A step of forming an element such as a transistor, a resistor, a capacitor, a diode, and a capacitor by disposing a metal electrode; a wiring step of forming a metal wiring between the devices; and a step of chipping a substrate obtained through the step. In addition, arranging the metal electrode means forming a thin film such as an insulating film on the wafer and patterning it by lithography, and further diffusing impurities to form a p-type and / or n-type region. Including the case of forming. Specifically, the insulating film element forming step and / or the wiring step include a buried element separating step, an interlayer insulating film planarizing step, a buried metal wiring forming step, a buried capacitor forming step, and the like. Here, the element obtained in the step of forming the element and / or the step of forming a metal wiring between the elements or a wafer in which the element and the wiring are combined is called a semiconductor substrate.
The manufacturing method of the semiconductor device of this invention is a method which has the process of grind | polishing a semiconductor substrate using the said polishing liquid composition (dilution liquid). As an example thereof, a semiconductor device manufacturing method including a step of polishing a substrate to be polished by the above polishing method can be given.
In addition, about polishing conditions, such as a polishing pad, what is necessary is just the same as the said polishing method.

  Specifically, the method includes a step of forming a thin film containing silicon above a semiconductor substrate having a stepped shape, and a polishing step of polishing the thin film. In the polishing step, ceria particles, dihydroxyethylglycine, and a dispersing agent are provided. A method comprising supplying the polishing liquid composition contained on the surface of the polishing pad and planarizing the surface of the thin film having an uneven step shape by CMP (Chemical Mechanical Polishing) is exemplified. There are embedded element isolation process, interlayer insulation film planarization process, buried metal wiring formation process, embedded capacitor formation process, etc., but it is particularly suitable for embedded element isolation process, interlayer insulation film planarization process, memory IC, logic It is suitably used for manufacturing semiconductor devices such as ICs or system LSIs.

Examples 1-7 and Comparative Examples 1-10
1. Evaluation of dispersion stability Dihydroxyethylglycine (Kyrest GA, manufactured by Crest, Inc.), aspartic acid (Wako Pure Chemical Industries, Ltd.), ethylenediaminetetraacetic acid (Dojindo, 4H), nitrilotriacetic acid (Chirest) listed in Table 2 Ion-exchange water was added to and mixed and dissolved in phthalic acid (manufactured by Kyres NT), phthalic acid (manufactured by Kishida Chemical Co., Ltd.) or polyacrylic acid (ammonia neutralization degree 65 mol%, molecular weight 6000, solid content 40 wt%). In a state of stirring the solution, a predetermined amount of an aqueous dispersion of ceria shown in Table 2 (ceria solid content 40% by weight, average particle diameter of ceria particles 125 nm, crystallite size of ceria particles 28 nm, molecular weight 6000 as a dispersing agent. Polyacrylic acid ammonium salt containing 0.1% by weight) was added, and the pH was adjusted to 6.0 to 6.3 with aqueous ammonia (28% by weight of ammonia) (manufactured by Toyama Pharmaceutical Co., Ltd.). 1-10 polishing liquid compositions were obtained. The average particle diameter of the ceria particles is a volume-based median diameter measured with a laser diffraction / scattering particle size distribution analyzer (LA-920, manufactured by Horiba, Ltd.).
Using the polishing composition thus prepared, ceria particle size was measured and a dispersibility test was performed under the following conditions.

<Measurement of ceria particle size in polishing composition>
As an index of the level of aggregation of ceria particles in the high-concentration polishing liquid composition, the ceria particle diameter in the polishing liquid composition that was allowed to stand for one day after preparation was measured. Specifically, using a Microtrac particle size measuring device UPA-150 (manufactured by Nikkiso Co., Ltd.), the polishing composition was shaken immediately before the measurement and sufficiently dispersed, and then the measurement was performed. The measurement conditions were ceria specific gravity of 7.3, measurement time of 2 minutes, and repeated measurements three times in succession. The ceria particle diameter was the median diameter (D50) of the volume average particle diameter.

<Dispersibility test>
After stirring 100 ml of each polishing composition with a magnetic stirrer for 10 minutes, the mixture was allowed to stand at room temperature (20 to 25 ° C.) in a colorimetric tube with a stopper (diameter 29 mm, volume 100 ml), and after a certain period of time (1 day later) The dispersion stability was determined from the state of separation of the supernatant liquid by sedimentation of ceria particles after 3 days and after 7 days. The judgment criteria are shown in Table 1, and the results are shown in Table 2.

<Dispersibility test results>
As the results of Table 2, the polishing liquid compositions of Examples 1 to 7 and Comparative Example 2 are free from agglomeration because of the small ceria particle diameter in the polishing liquid composition, and also have good dispersion stability. Indicates. On the other hand, the polishing liquid compositions of Comparative Examples 1 and 3 to 5 and 7 to 10 had aggregation due to the large ceria particle diameter in the polishing liquid composition, and had a problem in dispersion stability. In addition, the polishing liquid composition of Comparative Example 6 had insolubles.

2. Evaluation of planarization performance (1)
Furthermore, a polishing test was conducted under the following conditions using a diluted product obtained by diluting the above polishing liquid composition with ion-exchanged water.
<Polishing test (1)>
1. Polishing conditions Polishing tester: Single-side polishing machine (Part No .: LP-541, manufactured by Lapmaster SFT, surface plate diameter 540 mm)
Polishing pad: IC-1000 / Sub400 (Nitta Haas)
Surface plate rotation speed: 60 rpm
Head rotation speed: 62 rpm (Rotation direction is the same as the surface plate)
Polishing load: 40 kPa
Polishing liquid supply amount: 200 ml / min (0.6 g / cm ² · min)
Substrate to be polished: Sematech864, a commercially available pattern wafer for CMP characteristics evaluation (Substrate patterned on a silicon substrate with a thickness of 170 nm by CVD (Chemical vapor deposition) and then etched to a depth of 500 nm) On top of a silicon substrate patterned on HDP-TEOS (high-density plasma tetraethoxysilane) silicon oxide film having a thickness of 600 nm or a BPSG film patterned wafer (same shape as Sematech864) at a depth of 370 nm (Those with a BPSG film with a thickness of 1000 nm)

  After polishing for 2 minutes under the above polishing conditions, evaluation was performed by measuring the remaining film thickness of the Sematech864 or BPSG film pattern wafer. Specifically, D20, D50, D80 pattern part (D20: Line & Space pattern with convex part width 20μm / concave part width 80μm, D50: Line & Space pattern with convex part width 50μm / concave part width 50μm, D80: Convex part width 80μm / concave part width The remaining film thickness (20 μm Line & Space pattern) is measured, and the step height (uneven step) is calculated from these remaining film thickness values. Here, the term Line & Space refers to the width of the linear pattern (line) and the interval (space) between the linear patterns at the location where the linear (linear) patterns are repeatedly arranged in the IC wiring structure, etc. The term “wiring pitch” refers to the dimension of wiring lines and spaces combined.

Sematech864: Step Height = Remaining film thickness of protrusion (HDP film + SiN film) + Si step-Remaining film thickness of recess
BPSG film pattern wafer: Step Height = protrusion remaining film thickness + Si step-recess remaining film thickness Here, the Si step represents the depth of the recess formed in the pattern on the silicon wafer.

  The Si level difference of the wafer used in this evaluation is 330 nm for Sematech 864 and 370 nm for the BPSG film pattern wafer. In addition, the measurement of the remaining film thickness used the optical interference type film thickness meter (Dainippon Screen Mfg. Co., Ltd. product name: VM-1000). The judgment criteria are shown in Table 3, and the results are shown in Table 4.

<Flatification performance evaluation result (1)>
Sematech864: In the diluted product of Example 1, the convex HDP film on the silicon nitride film disappears, and the polishing amount of the silicon nitride film is also small. In addition, the difference in HDP residual film thickness of the recesses between the patterns D20 and D80 was within 150 nm, and the patterning dependency was small and good planarization performance was obtained. In addition, in the diluted products of Comparative Examples 1 and 3, a good planarized surface was obtained as in the diluted product of Example 1. However, in the diluted product of Comparative Example 3, due to the decrease in the polishing rate, the convex HDP film remained in the polishing for 2 minutes, and the target flattening was not completed, and it was necessary to extend the polishing time to 5 minutes. On the other hand, in the diluted product of Comparative Example 2, the convex HDP film disappeared, but the polishing of the underlying silicon nitride film also progressed, and the silicon nitride film disappeared in the D20 pattern portion. Furthermore, since the difference in the HDP residual film thickness of the recesses was 250 nm or more between the D20 and D80 patterns, the pattern dependency was large and good planarization performance could not be obtained.
BPSG film pattern wafer: In the diluted product of Example 2, the step height in each pattern of D20, D50, and D80 is within 30 nm, and the remaining film thickness of the recess is within 100 nm between the patterns of D20 and D80. And good planarization performance was obtained. In the diluted product of Comparative Example 4, although the difference between the D20 and D80 patterns of the recess remaining film thickness was within 100 nm and excellent in the pattern dependency, the step height was 137 nm in the D80 pattern and the step was not eliminated. On the other hand, in the diluted product of Comparative Example 2, since the convex BPSG film disappeared after 2 minutes of polishing, the polishing time was shortened to 1 minute, but in the D20 pattern, the convex BPSG film disappeared. Furthermore, the remaining film thickness of the recesses was as large as 200 nm or more between the D20 and D80 patterns, and the pattern dependency was large, and good planarization performance could not be obtained.

3. Evaluation of planarization performance (2)
The following conditions were used, using diluted products (compositions after dilution are shown in Table 5) obtained by diluting the polishing liquid compositions of Examples 7 and 2 and Comparative Example 10 with ion-exchanged water at the dilution ratio shown in Table 5. A polishing test (2) was conducted.
<Polishing test (2)>
1. Polishing conditions Polishing tester: Single-side polishing machine (Part number: EPO222D, manufactured by Ebara Corporation)
Polishing pad: IC-1000 / Sub400 (Nitta Haas)
Surface plate rotation speed: 100 rpm
Head rotation speed: 107 rpm (Rotation direction is the same as the surface plate)
Polishing load: 30 kPa
Polishing liquid supply amount: 200 ml / min (0.6 g / cm ² · min)
Substrate to be polished: Sematech 864, a commercial pattern wafer for CMP characteristics evaluation (thickness 550 nm on a substrate patterned by etching a silicon nitride film with a thickness of 150 nm on a silicon substrate to a depth of 500 nm by etching) HDP-TEOS silicon oxide film) or BPSG film pattern wafer (1000 nm thick BPSG film formed on a 350 nm deep silicon substrate)

The polishing time was determined for each polishing liquid by measuring the change in the friction coefficient between the pattern wafer and the polishing pad by measuring the driving motor current of the surface plate and detecting the polishing end point.
The planarization performance was evaluated by measuring the remaining film thickness of the Sematech864 or BPSG film pattern wafer. Specifically, P25, P50, P100, P250, P500 pattern part (P25: Line & Space pattern with convex part width 12.5μm / concave part width 12.5μm, P50: Line & Space pattern with convex part width 25μm / concave part width 25μm, P100: Convex part Measure the remaining film thickness of the line & space pattern (part width 50μm / recess width 50μm, P250: line & space pattern with protrusion width 125μm / recess width 125μm, P500: line & space pattern with protrusion width 250μm / recess width 250μm) Step Height (unevenness level difference) is calculated from the value of the film thickness.

Sematech864: Step Height = Remaining film thickness of protrusion (HDP film + SiN film) + Si step-Remaining film thickness of recess
BPSG film pattern wafer: Step Height = protrusion remaining film thickness + Si step-recess remaining film thickness Here, the Si step represents the depth of the recess formed in the pattern on the silicon wafer.

  The Si step of the wafer used in this evaluation is 350 nm for Sematech 864 and 350 nm for the BPSG film pattern wafer. In addition, the measurement of the remaining film thickness used the optical interference type film thickness meter (KLA Tencor company make, brand name: Aset F5x). Table 5 shows the measurement results of Step Height of each pattern.

<Flatification performance evaluation result (2)>
As compared with the diluted product of Example 7 and the diluted product of Example 2, the Step Height value was small in any pattern, indicating that the planarization performance was excellent.

4. Evaluation of Defects Further, a polishing test was conducted in the same manner as in the planarization performance evaluation (2) with diluted products of the polishing liquid compositions of Examples 7 and 2 and Comparative Example 10 (described in Table 5). However, a blanket wafer made of a thermal oxide film was used as the substrate to be polished. After polishing for 60 seconds, hydrogen peroxide (2%) was used, and cleaning was performed with a roll brush for 60 seconds. Defects were determined by using a laser type defect inspection apparatus (trade name: Surfscan SP1 manufactured by KLA Tencor) and the number and size of each blanket wafer. In the measurement method, the number of defects and the size are converted from the intensity and angle of reflected light by irradiating the wafer surface with a laser.
Table 6 shows the results of the number of defects.

<Defect evaluation result>
The number of defects at a level of 0.14 μm or more, which is considered to be the most realistic in the setting of the inspection apparatus recipe, is smaller in the diluted products of Examples 7 and 2 than in the diluted product of Comparative Example 10, and is superior in performance. all right.

  From the above, it can be seen that the polishing composition of the present invention can achieve excellent dispersion stability in a high concentration state, high level flatness without pattern dependency, and reduction of defects after polishing.

The polishing composition for a semiconductor substrate of the present invention is used, for example, in an embedded element isolation step, an interlayer insulating film planarization step, an embedded metal wiring formation step, an embedded capacitor formation step, etc. It is suitable for the process and the interlayer insulating film flattening process, and is suitably used for manufacturing a semiconductor device such as a memory IC, a logic IC, or a system LSI.

Claims (12)

  A polishing composition for a semiconductor substrate containing dihydroxyethylglycine, ceria particles, a dispersant and an aqueous medium, wherein the content of ceria particles in the polishing composition is 2 to 22% by weight, and the content of the dispersant Polishing liquid composition for semiconductor substrates whose is 0.001-1.0 weight%.   A polishing composition for a semiconductor substrate obtained by blending dihydroxyethylglycine, ceria particles, a dispersant and an aqueous medium, wherein the ceria particles are contained in an amount of 2 to 22% by weight and the dispersant is 0. A polishing composition for a semiconductor substrate obtained by blending 001 to 1.0% by weight and an aqueous medium.   The polishing composition for a semiconductor substrate according to claim 1 or 2, wherein the content of dihydroxyethylglycine in the component excluding the aqueous medium and the ceria particles is 80 to 99.98 wt%.   The polishing composition for a semiconductor substrate according to claim 1, wherein the content of dihydroxyethylglycine in the polishing composition for a semiconductor substrate is 0.4 to 40% by weight.   The polishing composition for a semiconductor substrate according to any one of claims 1 to 4, wherein the content ratio of dihydroxyethylglycine to ceria particles (dihydroxyethylglycine / ceria particles) is 1/5 to 15/1 (weight ratio).   6. The polishing composition for a semiconductor substrate according to claim 1, wherein the content of the aqueous medium in the polishing composition for a semiconductor substrate is 60 to 97.599 wt%.   The dispersant is at least one selected from the group consisting of an anionic surfactant, a nonionic surfactant, an acrylic acid copolymer, a salt of an acrylic acid copolymer, and an ethylene oxide-propylene oxide block copolymer. A polishing composition for a semiconductor substrate according to any one of claims 1 to 6.   The polishing composition for a semiconductor substrate according to any one of claims 1 to 7, wherein the semiconductor substrate is formed by forming a film having at least silicon and having an uneven step shape of 50 to 2000 nm on the surface thereof. A step of supplying a liquid obtained by diluting the polishing composition for a semiconductor substrate according to claim 1 to the substrate at a supply rate of 0.01 to 10 g / min per 1 cm ^{2 of the} substrate to be polished. Polishing method.   The method for polishing a semiconductor substrate according to claim 9, wherein the substrate to be polished is polished by pressing a polishing pad with a polishing load of 5 to 100 kPa.   A method for manufacturing a semiconductor device, comprising a step of polishing a substrate to be polished by the polishing method according to claim 9. An element forming step in which an insulating film is formed on a single crystal substrate and a metal electrode is disposed thereon, a wiring step in which a metal wiring is formed between the elements, and a step in which a substrate obtained through the step is chipped A method for manufacturing a semiconductor device, comprising: a step of polishing a substrate to be polished by the polishing method according to claim 9 or 10 in an element formation step and / or a wiring step.