JP2007134035A5

JP2007134035A5 -

Info

Publication number: JP2007134035A5
Application number: JP2006300842A
Authority: JP
Filing date: 2006-11-06
Publication date: 2009-12-17
Anticipated expiration: 2026-11-06

Claims

Extending between a plurality of first and second memory cells configured for simultaneous programming, conducting a program current for recording data in one of the plurality of first and second memory cells. A first current source line configured as follows:
A first current source transistor connected to the first current source line and the word line;
A program conductor connected to the first current source transistor and extending across a bit line connected to one of the plurality of first and second memory cells to conduct the program current;
A second current source transistor connected to the program conductor and configured to switch the program current flowing from the program conductor toward an output terminal of the second current source transistor;
A second current source line extending adjacent to one of the plurality of first and second memory cells and facing the first current source line;
A first bias circuit configured to apply a first bias voltage to the first or second memory cell selected for access during a read operation;
A second bias circuit configured to apply a second bias voltage to the first or second memory cell not selected for access during the read operation;
A magnetic memory cell array device comprising:

A bit line driving circuit configured to provide a third bias voltage to the first or second memory cell that is not selected for access during the reading operation;
Wherein the third bias voltage is a magnetic memory cell array element according to claim 1, wherein the substantially identical to the second bias voltage.

First and second transfer transistors respectively connected between the outputs of the first and second bias circuits and the first and second word lines;
First and second enable gates connected to gates of the first and second transfer transistors;
The first and second transfer transistors are configured to transmit a predetermined voltage level of each output in the bias circuit to the first and second word lines in response to an output of the enable gate. The magnetic memory cell array device according to claim 2 .

4. The magnetic memory of claim 3 , wherein each of the first and second transfer transistors provides a single voltage drop across each element between the output of the bias circuit and the first word line. Cell array element.

The magnetic memory cell array elements, personal media players, mobile navigation systems, home appliances, PDA, personal computer, digital camera, television or magnetic memory cell array element according to claim 1, wherein the included in the game console.

Said first and second word lines, a magnetic memory cell array device according to claim 1, characterized by comprising a first and second digit lines, respectively.

In a resistive memory element,
A program current flowing from the first end toward the second end across the bit line connected to the memory cell located at the first and second ends of the block including the memory cell is applied. A pair of opposed current source transistors configured as described above, wherein the pair of current source transistors are configured such that the program current flows in parallel to adjacent blocks of the memory cell. .

8. The resistive memory device according to claim 7, wherein the resistive memory cell comprises a magnetic memory cell, a PRAM cell, or an OxRam cell.

In a resistive memory element,
A first bias circuit configured to apply a first bias voltage to a first memory cell or a second memory cell selected for access during a read operation;
A second bias circuit configured to apply a second bias voltage to the first memory cell or the second memory cell that is not selected for access during the read operation;
A resistive memory element comprising: