JP2007133968A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of accurately detecting abnormalities during an EW operation and accurately testing an error process by outputting an operation state information indicating which of a plurality of operation stages is executed according to the progress of the operation stages. <P>SOLUTION: In the nonvolatile semiconductor memory device for executing a stored information writing or deleting operation by diving the operation into a plurality of operation stages by an internal control circuit and according to a predetermined algorithm, the internal control circuit outputs operation state information indicating which of the plurality of operation stages is executed according to the progress of the operation stages. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device that executes a write operation or an erase operation of stored information into a plurality of operation stages by an internal control circuit and executes the operation according to a predetermined algorithm.

  Some nonvolatile semiconductor memory elements require complicated operations when writing or erasing stored information. In a storage device using such a nonvolatile semiconductor memory element, a write or erase operation is simplified by allowing a control circuit prepared in the storage device to perform an operation necessary for writing or erasing. There is something.

  A typical example of the nonvolatile semiconductor memory device is a flash memory. Hereinafter, the operation of the flash memory will be described. A flash memory uses a nonvolatile semiconductor memory element having a floating gate structure, and performs a write / erase operation of stored information by changing a floating gate voltage by injecting / releasing electrons to / from the floating gate. In order to inject / emit electrons to / from the floating gate, a complicated operation (hereinafter referred to as an EW operation) such as switching of a voltage applied to the storage element and verification of read data from the storage element is required.

  The EW operation includes a plurality of processing stages. As an example, the processing stage in the erasing operation will be described. The flash memory here performs writing by lowering the floating gate voltage by injecting electrons into the floating gate, and erasing by raising the floating gate voltage by releasing electrons from the floating gate. When performing a writing operation by injection of electrons into the floating gate or an erasing operation by emission of electrons, it is necessary to set a voltage to the storage element in accordance with each operation. Note that since the voltage to be applied to the memory element differs between the write operation and the erase operation, a circuit for changing the applied voltage is prepared.

  FIG. 3 shows a flowchart of the erase operation of the flash memory. Stage B performs precondition processing, stage D performs erase processing, stage F performs postcondition processing, and stages A, C, and E perform voltage settings necessary for electron injection / discharge processing.

  A write operation by injection of electrons into the floating gate can be performed in units of storage elements, whereas an erase operation by emission of electrons from the floating gate can only be performed in units of blocks (one block is composed of several thousand words of storage elements). I can't. For this reason, it is necessary to equalize the floating gate voltages of all the memory elements in the target block before performing the erase process in the erase operation, and electrons are injected into the unwritten memory elements in the target block. Perform precondition processing.

  In addition, the erase process is performed in units of blocks. However, since there is a difference in the degree of electron emission from the floating gate due to the characteristic variation of each storage element, the floating gate voltage after the erase process of each storage element varies. Arise. For this reason, after the erase process, in order to equalize the floating gate voltage, a post-condition process is performed in which electrons are injected into the memory element in which the electron emission is large and the floating gate voltage is excessively increased.

  Furthermore, in each of the preconditioning process, the erasing process, and the postconditioning process, a verify process for checking the floating gate voltage is performed after the electron injection / emission process to the floating gate, and the electron injection / emission is insufficient. If so, the electron injection / emission process is repeated.

  The flash memory has a built-in control circuit in the flash memory and inputs a write command or erase command so that complicated write and erase operations consisting of multiple processing stages can be performed easily. The control circuit performs EW operation. However, since a plurality of EW operations cannot be performed simultaneously, it is not possible to input a write command or an erase command during the EW operation, and it is necessary to input a command after the completion of the EW operation. Since a period of several microseconds to several hundred milliseconds is required from the input of the write command or the erase command to the completion of the EW operation, a dedicated terminal (READY / BUSY # terminal) is used to notify the completion of the EW operation. ), Or a function of outputting status information when reading from the flash memory after inputting a write command or an erase command.

  The READY / BUSY # terminal and the status information output operation will be described with reference to FIG. When a write command or an erase command is input, a START pulse is generated, the latch 10 is set, and the ENABLE signal becomes “H” level (power supply voltage level). When the ENABLE signal becomes “H” level, the control circuit 17 is activated to perform the EW operation. When the EW operation ends, the control circuit 17 generates a COMPLEATE pulse. The latch 10 is reset by the COMPLEATE pulse, the ENABLE signal becomes “L” level (ground voltage level), and the control circuit 17 stops. The output circuit 13 outputs a READY / BUSY # signal in response to the ENABLE signal. The output circuit 13 sets the output to “L” level when the ENABLE signal is “H”, and sets the output to high impedance when the ENABLE signal is “L” level. In general, since the READY / BUSY # terminal is pulled up to the power supply via a resistor, when the output circuit 13 sets the output to the “L” level, the output of the READY / BUSY # terminal is “L”. When the output circuit 13 sets the output to high impedance, the output of the READY / BUSY # terminal becomes the “H” level.

  The output MUX 18 selects read data from the memory cell when RD_DATA is at “H” level, and outputs the selected data from the output terminals DQ 0 to 7 through the output circuit 14. When RD_STAT is at “H” level, the ENABLE signal is selected and output from the output terminal DQ 7 via the output circuit 14. At this time, when the ENABLE signal is “H” level, DQ7 = “0”, “00h” is output as the status signal from the output terminals DQ0 to DQ7, and when the ENABLE signal is “L” level, DQ7 = “1”, and “80h” is output as the status signal from the output terminals DQ0 to DQ7. When performing a memory read, RD_DATA = “H”, but when a write command or an erase command is input, RD_STAT = “H” and a status signal is output simultaneously with the generation of the START pulse.

  FIG. 9 shows the output waveforms of the READY / BUSY # terminal and the DQ0 to DQ7 terminals after the erase command is input. During the EW operation period, the READY / BUSY # terminal is at the “L” level, and “00H” is output from the DQ 0 to 7 terminals. When the EW operation is completed, the READY / BUSY # terminal becomes “H” level, and “80H” is output from the DQ0 to 7 terminals.

  By the way, not only in the case of different storage devices, but also in the same storage device, if the storage elements to be operated are different, there is a difference in the required EW operation time. This is mainly due to variations in the characteristics of the individual memory elements and different degrees of electron injection / discharge. Further, when there is an abnormality in the storage element and the degree of electron injection / emission falls beyond the above range, or there is an abnormality in the voltage control circuit applied to the storage element, If the necessary voltage is not applied to the memory element, the EW operation time will increase significantly.

  Therefore, conventionally, an EW operation time is measured, and when a preliminarily assumed EW operation time is exceeded, an abnormality detection method is used in which an abnormality of the storage element or an abnormality of the voltage control circuit has occurred. . Of course, the assumed EW operation time is determined in consideration of variations in the EW operation time due to normal storage elements.

Japanese Patent Laid-Open No. 2003-16788

  However, the processing time at each processing stage performed in the EW operation is different, and even if the processing time increases due to some abnormality in a stage with a short processing time, the influence on the processing time of the entire EW operation is small, so that an abnormality is detected. There was a problem that could not be performed.

  For example, in the erase operation flowchart of FIG. 3, the ratio of the processing time of each stage to the EW operation time is 2% for stages A, C, and E, 30% for stage B, 50% for stage D, and for stage F. Suppose that it is 14%. Then, the EW operation time increases by 100% when the processing time of stage D is tripled, whereas the EW operation time when the processing time of stage A is triple is only 4% increase. Don't be. Here, if it is assumed that the criterion for determining the EW operation time for detecting a circuit abnormality is set when the EW operation time has increased by 100% or more, stage D is determined to be abnormal by three times or more. If it is A, it will not be judged as abnormal unless it becomes 51 times or more.

  In addition, as another problem, when testing whether error processing during EW operation is performed correctly, it is difficult to test error processing for all processing stages and to confirm that testing is possible. There is a problem. In order to test the error processing, an error factor is generated during the EW operation and the processing result is checked. To test the error processing for all processing stages, each processing stage is being performed. It is necessary to generate an error factor. However, in the prior art, it is possible to determine that the EW operation is being performed based on the output from the READY / BUSY # terminal, but it is not possible to determine which processing stage is currently being performed. A factor cannot be generated. Similarly, it is also impossible to determine which processing stage was performed when the error factor was generated.

  The present invention has been made in view of the above problems, and an object of the present invention is to output EW operation information that indicates which of a plurality of operation stages is being executed in accordance with the progress of the operation stages. Therefore, it is possible to provide a nonvolatile semiconductor memory device capable of accurately detecting an abnormality therein and accurately executing an error processing test.

  In order to achieve the above object, a non-volatile semiconductor memory device according to the present invention includes a non-volatile semiconductor memory that performs a write operation or an erase operation of stored information into a plurality of operation stages by an internal control circuit and executes the operation according to a predetermined algorithm. The apparatus is characterized in that the internal control circuit can output operation state information indicating which of the plurality of operation stages is being executed in accordance with the progress of the operation stages.

  In the nonvolatile semiconductor memory device having the above characteristics, the internal control circuit generates a plurality of operation state signals individually associated with the plurality of operation stages indicating the operation state information, and outputs the operation state signal to an output terminal. The second feature is that the output is from.

  According to a third aspect of the nonvolatile semiconductor memory device having the above characteristics, the internal control circuit outputs the operation state signal using an output terminal used for reading the stored information.

  In the nonvolatile semiconductor memory device according to the first feature, the internal control circuit generates a plurality of operation state signals individually associated with the plurality of operation stages indicating the operation state information, and the operation state signal A fourth feature is that an operation state code indicating the operation state information is generated, and the operation state code is output from an output terminal.

  The nonvolatile semiconductor memory device having the above characteristics is characterized in that the internal control circuit outputs the operation state code signal using an output terminal used for reading the stored information.

  According to the present invention, the operation state information indicating which one of a plurality of operation stages is being executed can be output in accordance with the progress of the operation stage. Therefore, during a storage state write operation or erase operation (EW operation) The processing time at each operation stage (processing stage) can be individually measured, and even a processing stage with a short processing time can be detected when some abnormality occurs and the processing time increases.

  In addition, since the processing stage currently being operated can be determined, it is possible to specify an arbitrary processing stage and generate an error factor during the specified processing stage. It becomes possible to test the treatment.

  Embodiments of a nonvolatile semiconductor memory device according to the present invention (hereinafter simply referred to as “device of the present invention” as appropriate) will be described below with reference to the drawings.

  The device according to the present invention performs a write operation or erase operation (EW operation) of stored information into a plurality of operation stages by an internal control circuit and executes it according to a predetermined algorithm, and the internal control circuit executes it by an EW operation. The operation state information corresponding to the operation stage (processing stage) in the middle is output in accordance with the progress of the processing stage, and the current processing state can be read by the operation state information.

<First Embodiment>
A first embodiment of the device of the present invention will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a schematic block diagram showing a schematic configuration of the device 1 of the present invention. The device 1 of the present invention includes a latch 10 for latching a START pulse, a control circuit 11 corresponding to an internal control circuit that receives the START pulse and controls an EW operation, an output circuit 13 that generates a READY / BUSY # signal, and an output circuit 14. When a write command or an erase command is input to the device 1 of the present invention, a START pulse is generated, the latch 10 is set, and the ENABLE signal becomes “H” level (power supply voltage level). When the ENABLE signal becomes “H” level, the control circuit 11 is activated and performs an EW operation. In the present embodiment, at this time, operation state information STG_A, STG_B, STG_C, STG_D, STG_E, and STG_F are output according to each processing stage of the EW operation. When the EW operation ends, the control circuit 11 generates a COMPLEATE pulse. When the COMPLEATE pulse is generated, the latch 10 is reset, the ENABLE signal is changed from “H” level to “L” level, and the control circuit 11 is stopped.

  The output circuit 13 outputs a READY / BUSY # signal in response to the ENABLE signal. The output circuit 13 sets the output to “L” level when the ENABLE signal is “H” level, and sets the output to high impedance when the ENABLE signal is “L”. Generally, since the READY / BUSY # terminal is pulled up to the power supply voltage via a resistor, the output of the READY / BUSY # terminal is “L” when the output circuit 13 sets the output to the “L” level. When the output circuit 13 sets the output to high impedance, the output of the READY / BUSY # terminal becomes the “H” level.

  The output MUX 12 selects read data from the memory cell when RD_DATA is at “H” level, and outputs the selected data from the output terminals DQ 0 to 7 through the output circuit 14. The output MUX 12 selects the ENABLE signal when RD_STAT is at “H” level, and outputs it from the output terminal DQ 7 via the output circuit 14. At this time, when the ENABLE signal is at “H” level, DQ7 = “0”, and “00h” (h indicates hexadecimal notation) is output from the output terminals DQ0 to DQ7. Similarly, when the ENABLE signal is “L” level, DQ7 = “1”, and “80h” is output as the status signal from the output terminals DQ0 to DQ7.

  The output MUX 12 selects the operation state information when RD_STGE is at “H” level, and outputs it from the output terminals DQ 0 to 5 through the output circuit 14. At this time, DQ6 = "0" and DQ7 = "0". Specifically, in stage A, since the STG_A signal is generated and output from DQ0, the values of the output terminals DQ0 to DQ7 are “01h”. In stage B, since the STG_B signal is generated and output from DQ1, the values of the output terminals DQ0 to DQ7 are “02h”. In stage C, since the STG_C signal is generated and output from DQ2, the values of the output terminals DQ0 to DQ7 are “04h”. In stage D, since the STG_D signal is generated and output from DQ3, the values of the output terminals DQ0 to DQ7 are “08h”. In stage E, since the STG_E signal is generated and output from DQ4, the values of the output terminals DQ0 to DQ7 are “10h”. In stage F, since the STG_F signal is generated and output from DQ5, the values of the output terminals DQ0 to DQ7 are “20h”.

  FIG. 2 shows output waveforms at the READY / BUSY # terminal and the DQ0 to DQ7 terminals after the erase command is input in the mode for reading the operation state information. In the mode for reading the operation state information, that is, when RD_STGE = “H” level, the READY / BUSY # terminal becomes “L” level during the EW operation period, and becomes “H” level except during the EW operation period. . The output terminals DQ0 to DQ7 are “01h” in stage A, “02h” in stage B, “04h” in stage C, “08h” in stage D, stage E according to the processing stage being executed in the EW operation. Is “10h” and stage F is “20h”. At this time, the processing time of each processing stage can be obtained by measuring the period during which the operation state information is output.

Second Embodiment
A second embodiment of the device of the present invention will be described with reference to FIGS. Here, the description of the same operation as in the first embodiment is omitted, and the difference from the first embodiment is described.

  The MUX 15 selects the operation state information STG_A to STG_C or STG_D to STG_F according to the value of the address signal Addr0, and outputs it as stage bit signals STG_0 to STG_2. Specifically, when Addr0 = "L", the MUX 15 outputs STG_A corresponding to STG_0, STG_B corresponding to STG_1, and STG_C corresponding to STG_2. Further, when Addr0 = "H", STG_D is output in correspondence with STG_0, STG_E in correspondence with STG_1, and STG_F in correspondence with STG_2.

  The output MUX 12 selects the stage bit signals STG_0 to STG_2 when RD_STGE = “H”, and outputs them in correspondence with the output signals DQ0 to 2 via the output circuit 14.

  FIG. 5 shows output waveforms of the READY / BUSY # terminal and the DQ0-7 terminals after the erase command is input in the mode for reading the operation state information. The READY / BUSY # terminal is at the “L” level during the EW operation period, and is at the “H” level during the EW operation period. The output terminals DQ0 to 7 output stage bit signals according to the processing stage being executed in the EW operation, and the values "01h", "02h", and "04h" are output as the EW process proceeds. . At this time, when checking the processing status of stage A, stage B, and stage C, the address signal Addr0 is set to “L”, and the processing status of stage D, stage E, and stage F is checked. Sets the address signal Addr0 to "H".

<Third Embodiment>
A third embodiment of the device of the present invention will be described with reference to FIGS. Here, the description of the same operation as in the first embodiment is omitted, and the difference from the first embodiment is described. In the first embodiment, the operation state information is output from the output circuit 14, but in the present embodiment, a case will be described in which the operation state code in which the operation state information is encoded by the encoder 16 is output from the output circuit 14.

  The operation state information output from the control circuit 11 is encoded by the encoder 16 into the operation state code STG_N. Specifically, when STG_A = “H”, STG_N = “01h”, when STG_B = “H”, STG_N = “02h”, when STG_C = “H”, when STG_N = “03h”, and when STG_D = “H” When STG_N = “04h”, STG_E = “H”, STG_N = “05h”, and when STG_F = “H”, STG_N = “06h”.

  The output MUX 12 selects the operation state code STG_N when RD_STGE = “H”, and outputs it to the output terminals DQ 0 to 7 through the output circuit 14.

  FIG. 7 shows output waveforms at the READY / BUSY # terminal and the DQ0 to DQ7 terminals after the erase command is input in the mode for reading the operation state information. The READY / BUSY # terminal is at “L” level during the EW operation period, and is at “H” level except during the EW operation period. Depending on the processing stage being executed, the output terminals DQ0-7 are “01h” for stage A, “02h” for stage B, “03h” for stage C, “04h” for stage D, as operation status codes. A value of “05h” is output at stage E, and “06h” is output at stage F.

  In the first embodiment, since one operation state information is assigned to one DQ terminal, when the output data width is 8 bits, up to eight types of operation state information can be handled. In the embodiment, a larger number of operation state information can be handled. For example, the erase operation shown in FIG. 3 is composed of six types of processing stages. Of these, the electron injection / emission processing and the verification processing are separately performed for each of the precondition processing, the erase processing, and the postcondition processing. In this processing stage, the erasing operation is composed of nine types of stages. In this case, in the second embodiment and the third embodiment, since it is possible to cope with a larger number of stages with the same output data width, it is possible to cope with an EW operation composed of nine types of processing stages. .

  More specifically, in the second embodiment, the operation state information output by the address signal Addr0 can be selected, so that more operation state information than the output data width can be output. When the output terminal is 8 bits, a total of 16 types of operation state information can be output, with 8 types when Addr0 = "L" and 8 types when Addr0 = "H". Furthermore, it is possible to cope with a lot of operation state information by increasing the address signal for selecting the operation state information. In the third embodiment, since the operation state information encoded is output as the operation state code, when the output data width is 8 bits as in this embodiment, the operation state code is set from “01h” to “FFh”. Therefore, 255 types of operation state information can be output.

1 is a block diagram showing a schematic configuration in a first embodiment of a nonvolatile semiconductor memory device according to the present invention. The wave form diagram which shows the output waveform of each signal in 1st Embodiment of the non-volatile semiconductor memory device which concerns on this invention Flow chart showing each operation stage of erasure operation The block diagram which shows schematic structure in 2nd Embodiment of the non-volatile semiconductor memory device which concerns on this invention The wave form diagram which shows the output waveform of each signal in 2nd Embodiment of the non-volatile semiconductor memory device which concerns on this invention The block diagram which shows schematic structure in 3rd Embodiment of the non-volatile semiconductor memory device based on this invention The wave form diagram which shows the output waveform of each signal in 3rd Embodiment of the non-volatile semiconductor memory device which concerns on this invention A block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to the prior art Waveform diagram showing output waveform of each signal of nonvolatile semiconductor memory device according to prior art

Explanation of symbols

1: Nonvolatile semiconductor memory device 10 according to the present invention: Latch 11: Control circuit 12: Output MUX
13: Output circuit 14: Output circuit 15: MUX
16: Encoder 17: Control circuit 18: Output MUX

Claims (5)

A nonvolatile semiconductor memory device that performs a write operation or an erase operation of stored information into a plurality of operation stages by an internal control circuit and executes the operation according to a predetermined algorithm,
A nonvolatile semiconductor memory device, wherein the internal control circuit can output operation state information indicating which of the plurality of operation steps is being executed in accordance with the progress of the operation steps.   The internal control circuit generates a plurality of operation state signals individually associated with the plurality of operation stages indicating the operation state information, and outputs the operation state signals from an output terminal. 2. The semiconductor memory device according to 1.   The semiconductor memory device according to claim 2, wherein the internal control circuit outputs the operation state signal using an output terminal used for reading the stored information.   The internal control circuit generates a plurality of operation state signals individually associated with the plurality of operation stages indicating the operation state information, encodes the operation state signal, and indicates an operation state code indicating the operation state information The semiconductor memory device according to claim 1, wherein the operation status code is output from an output terminal.   5. The semiconductor memory device according to claim 4, wherein the internal control circuit outputs the operation state code signal using an output terminal used for reading the stored information.