JP2007129763A - Solid-state imaging element and drive method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS image sensor capable of decreasing a read voltage and extending its dynamic range. <P>SOLUTION: P well regions 200 are formed to a semiconductor substrate, and an embedded type PD 119, a transfer transistor Tr 111, an amplifier transistor Tr 112, a selection transistor Tr 113, a reset transistor Tr 114, and an FD 115 or the like are provided in each of the P well regions 200, and signal electric charges of the PD 119 are transferred by the operation of the transfer transistor Tr 111. Then a negative voltage (substrate bias voltage) is applied to each of the P well regions 200 in matching with electric charge transfer operations by the transfer transistor Tr 111 to control a potential balance between the PD 119 and a transfer gate part thereby decreasing a voltage for electric charge transfer. Moreover, changing the substrate bias voltage during electric charge storage of the PD 119 corrects an angle of a sensitivity curve and extends the dynamic range. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device such as a CMOS type image sensor or a CCD type image sensor and a driving method thereof, and in particular, to reduce a voltage when reading a signal charge generated by a photoelectric conversion device and to expand a dynamic range. It relates to possible configurations.

10 and 11 are diagrams showing an example of a pixel structure in a conventional CMOS image sensor. FIG. 10 is a circuit diagram showing a configuration example of a pixel circuit, and FIG. 11 is a cross-sectional view showing a structure of an element.
First, the configuration of the pixel circuit will be described with reference to FIG.
In the illustrated configuration, each pixel is provided with a photodiode (PD) 10 and four pixel transistors (Tr) 11, 12, 13, and 14 for transfer, amplification, selection, and reset.
The PD 10 accumulates electrons generated by photoelectric conversion. The transfer Tr 11 transfers the electrons of the PD 10 to the floating diffusion (FD) 15.
The amplification Tr12 has a gate connected to the FD 15, and converts the potential fluctuation of the FD 15 into an electric signal. The selection Tr13 selects a pixel from which a signal is read out in units of rows. When the selection Tr13 is turned on, the amplification Tr12 and the constant current source 17 connected to the vertical signal line 16 outside the pixel form a source follower. Therefore, a voltage interlocked with the voltage of the FD 15 is output to the vertical signal line.
The reset Tr14 resets the potential of the FD15 to Vdd.

FIG. 11 shows a cross-sectional structure of a region from the PD 10 to the FD 15 through the gate portion of the transfer Tr 11.
As shown in the figure, the PD 10, the gate portion 11 A of the transfer Tr 11, and the FD 15 are provided in the P well region 20 A formed on the silicon substrate 20, and a gate oxide film (gate insulating film) 21 is formed on the silicon substrate 20. In the gate oxide film 21, an element isolation portion 22 by LOCOS is formed.
Further, a transfer gate electrode 11B of the transfer Tr11 is formed on the gate oxide film 21.

Here, as the PD 10, an embedded PD is known. For example, in the case of a photodiode formed in a P-well region, the buried PD is a p + layer (charge separation region) 10A near the interface of the gate oxide film 21, and an n layer (accumulating photoelectrons) underneath it. A charge storage region) 10B is formed, and charges are stored in the deep portion of the substrate 20.
In such a buried PD, since the interface of the n layer 10B is covered by the p + layer 10A, dark current generated at the interface of the n layer 10B can be prevented.
Further, if the transfer Tr11 and PD10 are appropriately designed, all the photoelectrons of the PD10 can be transferred to the FD15. Therefore, the embedded PD10 as described above has a structure widely used in CCD sensors. What is called a so-called HAD (Hole Accumulation Diode) structure is provided.

Further, since the transistor is formed by a normal CMOS process, the transfer gate electrode 11B is formed with a side wall 11C as a spacer by a silicon oxide film or the like.
The n layer 10B of the PD 10 is formed by ion implantation by self-alignment using the transfer gate electrode 11B after the transfer gate electrode 11B is formed and before the sidewall 11C is formed.
The p + layer 10A of the PD 10 is formed by ion implantation after self-alignment using the side wall 11C after the side wall 11C is formed.
The reason for this is to make it easier to transfer the photoelectrons of the PD 10 by reliably separating the distance between the p + layer 10A and the gate electrode 11B by a minute distance.
On the other hand, the FD 15 side has an LDD structure like a normal transistor. In the LDD structure, an n layer (LDD layer) having a low impurity concentration is formed immediately below the side wall 11C of the transfer gate portion 11A, and the n + layer (NSD) having a high impurity concentration is separated from the transfer gate portion 11A by the side wall 11C. Layer).

In addition, in the solid-state imaging device having the above-described structure, the present inventors apply a negative voltage such as −1 V (here, referred to as a transfer bias voltage) to the transfer gate electrode 11B, so that It has been proposed to suppress a dark current from the interface (a current whose component is electrons flowing into the PD even when no light is incident).
This is because, by biasing the transfer gate electrode 11B to a negative voltage, a p-type channel 11D is formed at the interface of the oxide film 21 below the transfer gate portion 11A, and the dark current from the interface state is the same as in the buried PD10. It is because it prevents.

  In addition, in this type of solid-state imaging device, a method of changing the voltage of the transfer gate or the reset gate during the accumulation time is known as a method for expanding the dynamic range (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 10-248035

By the way, in the pixel configuration shown in FIGS. 10 and 11 as described above, there is a problem that the gate voltage necessary for transferring the photoelectrons of the PD 10 cannot be lowered more than a certain level and it is difficult to lower the voltage of the CMOS sensor.
That is, the PD 10 is required to have a fully depleted voltage of, for example, 1.5 V or more so that the required number of electrons can be stored. In order to read all the electrons of the PD, when the transfer gate is turned on, a channel having a potential of 1.5 V or more is deeper than the interface of the oxide film 21 so as to be smoothly connected to the n layer of the PD. Must be made.

For these reasons, there has been a problem that the gate voltage cannot be made 2.7 V or less, for example, for complete transfer. This is inconsistent with the problem that it is difficult to transfer PD photoelectrons to a deep voltage with the same gate voltage, and the number of saturated electrons is small, that is, the dynamic range cannot be obtained. In particular, a CMOS sensor is required to have a low voltage of 2.5 V or 1.8 V, but how to increase the number of saturated electrons has always been a problem.
Note that these issues (lowering the transfer gate voltage and increasing the number of electrons that can be transferred with the same voltage) can be input even when the PD is not an embedded type or when a photogate is used instead of the PD. As long as there is a transfer means for controlling the potential, it exists in the same manner.

Next, the method disclosed in Patent Document 1 has the following problems.
First, when the voltage of the transfer gate is changed during the accumulation time, if a high voltage is applied to the transfer gate, the PD and FD are brought into conduction when the amount of light is large, so the operation range is limited.
Further, when the voltage of the reset gate is changed during the accumulation time, since the photoelectrons are stored in a node having a contact such as FD, the dark current is increased unlike the case of storing in the embedded photodiode.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device capable of achieving a low voltage when reading out signal charges generated by a photoelectric conversion device and capable of expanding a dynamic range, and a control method thereof. is there.

  In order to achieve the above object, the present invention provides a photoelectric conversion element that generates a signal charge corresponding to the amount of received light in a well region formed in a semiconductor substrate, and a signal charge generated by the photoelectric conversion element at a predetermined read timing. And a voltage control means for applying a predetermined substrate bias voltage to the well region when the signal charge is read by the read unit.

  The present invention also provides a photoelectric conversion element that generates a signal charge corresponding to the amount of received light in a well region formed in a semiconductor substrate, and a reading unit that reads the signal charge generated by the photoelectric conversion element at a predetermined read timing. And a voltage control means for changing a substrate bias voltage applied to the well region during a signal charge accumulation period by the photoelectric conversion element.

  The present invention also provides a photoelectric conversion element that generates a signal charge corresponding to the amount of received light in a well region formed in a semiconductor substrate, and a reading unit that reads the signal charge generated by the photoelectric conversion element at a predetermined read timing. A solid-state imaging device driving method comprising: applying a predetermined substrate bias voltage to the well region when reading the signal charge by the reading unit.

  The present invention also provides a photoelectric conversion element that generates a signal charge corresponding to the amount of received light in a well region formed in a semiconductor substrate, and a reading unit that reads the signal charge generated by the photoelectric conversion element at a predetermined read timing. And a substrate bias voltage applied to the well region is changed during a signal charge accumulation period of the photoelectric conversion element.

In the solid-state imaging device and the driving method thereof according to the present invention, when the signal charge generated by the photoelectric conversion device is read by the reading unit, a predetermined substrate bias voltage is applied to the well region, so that the photoelectric conversion is caused by the potential fluctuation of the well region. Although the potentials of the conversion element and the read unit also fluctuate, the shake amount of the read unit is suppressed by the presence of the read drive electrode, and the shake amount of the photoelectric conversion element increases.
As a result, even if the read voltage is low, the signal charge of the photoelectric conversion element can be efficiently transferred to the read unit side, and the read voltage can be lowered. Alternatively, if the same voltage is used, more charges can be read, and the amount of handled charges and the dynamic range can be increased.

  In the solid-state imaging device and the driving method thereof according to the present invention, the number of saturated electrons of the photoelectric conversion element is increased over time by changing the substrate bias voltage applied to the well region during the signal charge accumulation period of the photoelectric conversion element. Accordingly, by switching from small to large, the dynamic range can be expanded by avoiding saturation in a bright region without reducing sensitivity in a dark region.

Embodiments of a solid-state imaging device and a method for manufacturing the same according to the present invention will be described below.
In the embodiment of the present invention, a P-well region provided in a lower layer of a pixel in order to reduce the voltage when transferring signal charges of a PD (photoelectric conversion element) to an FD by a transfer gate (signal reading unit) On the other hand, the substrate bias voltage is applied in synchronization with the charge transfer. As a result, the read voltage can be lowered.
The dynamic range is expanded by changing the substrate bias voltage applied to the P-well region during the charge accumulation period of the PD.
Note that these principles will be described later using specific examples.

FIG. 1 is a block diagram showing an example of the overall configuration of a solid-state imaging device according to an embodiment of the present invention, and shows an example of a CMOS type image sensor.
FIG. 2 is a circuit diagram showing a configuration example of one pixel circuit of the solid-state imaging device shown in FIG.
As shown in FIG. 1, the solid-state imaging device of this example includes a pixel unit (imaging region unit) 110, a constant current unit 120, a column signal processing unit (column unit) 130, and a vertical (V) selection on a semiconductor element substrate 100. A driving unit 140, a horizontal (H) selection unit 150, a horizontal signal line 160, an output processing unit 170, a timing generator (TG) 180, and the like are provided.
The pixel portion 110 has a large number of pixels arranged in a two-dimensional matrix, and each pixel is provided with a pixel circuit as shown in FIG. The signal of each pixel from the pixel unit 110 is output to the column signal processing unit 130 through a vertical signal line (not shown in FIG. 1) for each pixel column.
In the constant current unit 120, a constant current source (not shown in FIG. 1) for supplying a bias current to each pixel is arranged for each pixel column.
The V selection drive unit 140 selects each pixel of the pixel unit 110 one row at a time, and drives and controls the shutter operation and readout operation of each pixel.

The column signal processing unit 130 receives the signal of each pixel obtained through the vertical signal line one row at a time, performs predetermined signal processing for each column, and temporarily holds the signal. For example, CDS (removing fixed pattern noise caused by variations in threshold values of pixel transistors) processing, AGC (auto gain control) processing, A / D conversion processing, and the like are appropriately performed.
The H selection unit 150 selects the signals of the column signal processing unit 130 one by one and guides them to the horizontal signal line 160.
The output processing unit 170 performs predetermined processing on the signal from the horizontal signal line 160 and outputs the signal to the outside, and includes, for example, a gain control circuit and a color processing circuit. Instead of performing A / D conversion by the column signal processing unit 130, the output processing unit 170 may perform the conversion.
The timing generator 180 supplies various pulse signals necessary for the operation of each unit based on the reference clock.

Next, the pixel circuit of this example will be described with reference to FIG.
In the illustrated configuration, a photodiode (PD) 110 and four pixel transistors (Tr) 111, 112, 113, and 114 for transfer, amplification, selection, and reset are provided in each pixel.
The PD 119 accumulates electrons generated by photoelectric conversion, and transfers the electrons of the PD 119 to the floating diffusion (FD) 115 by turning on the transfer Tr 111. Since the FD 115 has a parasitic capacitance, photoelectrons are stored here.
The amplifying Tr 112 has a gate connected to the FD 115 and converts a potential fluctuation of the FD 115 into an electric signal. The selection Tr 113 selects a pixel from which a signal is read out in units of rows. When the selection Tr 113 is turned on, the amplification Tr 112 and the constant current source 117 connected to the vertical signal line 116 outside the pixel form a source follower. Therefore, a voltage interlocked with the voltage of the FD 115 is output to the vertical signal line.
The reset Tr 114 resets the potential of the FD 115 to Vdd. The Vdd wiring is common to all pixels.

Further, the wirings 111A, 113A, 114A of the transfer Tr111, the selection Tr113, and the reset Tr114 extend in the horizontal direction (horizontal = row direction), and simultaneously drive pixels included in the same row.
Further, the transistors of each pixel are NMOS, and these are formed in the P well region. A wiring 118A for taking a contact 118 to the P well region extends in the horizontal direction (horizontal = row direction).
The wiring 118A for taking the contact 118 to the P well region is more effective. However, when high speed operation is not required, the electrical conductivity of the P well region itself is used even if it is not required. Thus, it is also possible to drive with contact only around the pixel portion (in this case, the pixel circuit is the same as that of FIG. 10 shown in the conventional example).

Next, in such a solid-state imaging device according to this embodiment, it is possible to lower the readout voltage from the PD by applying a substrate bias synchronized with the charge transfer to the P well region under the pixel. The principle will be described.
FIG. 3 is an explanatory diagram showing a potential structure in a region extending from PD to transfer gate to FD to reset gate to power supply wiring (Vdd) in the solid-state imaging device as described above, and FIG. FIG. 3B shows the potential when a substrate bias is applied (this embodiment). Note that the downward direction is the positive direction of the potential.

In the conventional transfer state shown in FIG. 3A, the transfer gate (transfer Tr) 111 is turned on and the photoelectrons of the PD 119 are transferred to the FD 115. However, the voltage of the transfer gate 111 is insufficient, and the transfer remains in the PD 119. Arise.
On the other hand, in this example shown in FIG. 3B, the transfer gate 111 is turned on and a negative substrate bias (absolute value VB) is applied to the P well region. At this time, since the capacitive coupling with the P well region is dominant in the PD 119, the potential of the PD 119 swings negative by a value close to the substrate bias VB.
On the other hand, since the channel below the transfer gate 111 is strongly capacitively coupled with the transfer gate 111, the ratio of coupling with the P well region is low, and the channel can swing slightly less than the substrate bias VB.

Further, since the FD 115 has capacitive coupling with the transfer gate 111 and the reset gate (reset Tr) 114 and capacitive coupling through the amplification gate (amplification Tr) 112, the ratio of coupling with the P well region is low. It can swing a little more than the substrate bias VB.
The channel below the reset gate 114 is the same as the channel below the transfer gate 111. Nodes to which a fixed voltage is applied like the power supply voltage Vdd do not move the potential.

Therefore, the potential relationship as shown in FIG. 3B is obtained, and the photoelectrons of the PD 119 can be transferred to the FD 115. Due to this effect, the photoelectrons of the PD 119 can be reliably transferred even when the voltage of the transfer gate 111 is low. Or, even with the same transfer gate voltage, the photoelectrons of the PD 119 can be read to a deeper potential, so that the amount of charge handled is increased and the dynamic range is expanded.
Further, as in a third embodiment to be described later, by changing the bias voltage of the P-well region during the accumulation period, it is possible to expand the dynamic range by a method of reducing the sensitivity of the portion with a large amount of light.

Hereinafter, some examples that further embody the present embodiment will be described in detail.
(First embodiment)
First, as a first embodiment, a specific example in which a substrate bias is applied to the P well region under the pixel portion described above will be described.
FIG. 4 is a plan view showing the structure of the P well region under the pixel portion of the first embodiment. The hatched portion shows the P well region 200, and the blank portion interposed inside the P well region 200 is the P well. The separation region 210 is shown. In addition, a region divided by a square in the P well region 200 represents one pixel 110A.
That is, in this example, the P well region 200 is electrically isolated for each pixel row of the pixel unit 110.

FIG. 5 is a timing chart showing each drive pulse of the pixel circuit in the first embodiment.
First, as a premise of the operation in this timing chart, it is assumed that the V selection driving unit 140 selects a row from which a pixel signal is output and supplies each pulse as shown in FIG.
The two timing pulses SHP and SHD are pulses that enter the column signal processing unit 130 instead of each pixel circuit, and are pulses for sample-holding the pixel output.
In the non-selected row, it is assumed that the transfer Tr 111, the reset Tr 114, and the selection Tr 113 are turned off and the P well region 200 is held at 0V.

Hereinafter, the operation of the selected row will be described with reference to FIG.
(1) First, the selection gate 113 is turned on. As a result, the signal of the row is output to the vertical signal line 116.
(2) Next, a reset pulse is input to the reset gate 114 to reset the FD 115.
(3) Next, with the sample hold pulse SHP, the voltage (reset level) of the vertical signal line 116 at that time is taken into the column signal processing unit 130.
(4) Next, after applying a negative substrate bias to the P well region 200 and turning on the transfer gate 111, the potential of the P well region 200 is returned to 0 V and the transfer gate 111 is turned off. As a result, photoelectrons are transferred to the FD 115.
(5) Next, with the sample hold pulse SHD, the voltage (signal level) of the vertical signal line 116 at that time is taken into the column signal processing unit 130.
(6) Next, the selection gate 113 is turned OFF, and the row is separated from the vertical signal line 116.

Thereafter, the column signal processing unit 130 calculates the difference between the reset level and the signal level by the above-described CDS circuit, performs other appropriate processing, and sequentially outputs the signal through the horizontal signal line 160.
As described above, in this embodiment, in (4) above, by applying the substrate bias at the time of charge transfer, transfer can be reliably performed even at a low voltage.
The V selection driving means 140 selects the next row after the column signal processing circuit 130 has finished outputting the signal to the horizontal signal line 160, and drives it in the same manner. By repeating this, a full screen signal is output.
In this embodiment, the column signal processing circuit 130 captures signals with SHP and SHD pulses. However, as long as signals are captured at the same timing, a circuit that does not use these pulses may be used. The same applies to the following embodiments.

(Second embodiment)
Next, as a second embodiment, an example will be described in which the substrate bias is applied to the P well region below the pixel unit as described above, not in units of rows but as the entire pixel unit.
FIG. 6 is a plan view showing the configuration of the P well region under the pixel portion of the second embodiment, and the hatched portion shows the P well region 220. In FIG. That is, this example is an example in which a P well region 220 that is electrically conductive is provided throughout the pixel portion 110.

FIG. 7 is a timing chart showing each drive pulse of the pixel circuit in the second embodiment.
First, pixels in all rows are operated simultaneously, and charge transfer is performed following reset of the FD 115. First, a reset pulse is input to reset the FD 115. Thereafter, a transfer pulse is input to transfer the photoelectrons of the PD 119 to the FD 115.
At the timing of this transfer pulse, as in the first embodiment, the potential of the P well region 220 is changed negatively to assist the transfer. As a result, the FD 115 of all the pixels holds a voltage shifted by the photoelectron from the reset voltage.

Next, the signal of each pixel is read out line by line. Here, only the read line operates.
In the readout row, first, the selection gate 113 is turned on, and the voltage (signal level) of the vertical signal line 116 in that state is taken into the column signal processing circuit 130 by SHD.
Next, a reset pulse is input, and the voltage (reset level) of the vertical signal line 116 is taken into the column signal processing circuit 130 by SHP. Then, the selection gate 113 is turned off.
The column signal processing circuit 130 calculates the difference between the reset level and the signal level, performs appropriate processing, turns off the selection gate 113, and sequentially outputs the signal through the horizontal signal line 140.
Thereafter, the read line moves to the next line, and the same operation is repeated.

Then, after reading the signals of all the rows one by one in this way, the dummy signal period continues until the end of one frame period. During this time, a PD reset operation is performed to determine the exposure time. In this operation, all rows of pixels operate simultaneously.
Note that this operation may be the same as the previous all-row FD simultaneous reset / transfer, and a negative potential is applied to the P-well region 220 during the transfer to assist the transfer. From this point, new photoelectrons start to be accumulated in the PD, and the same operation is performed from the beginning.

  In the first and second embodiments described above, a photodiode is used as the photoelectric conversion element. However, whether or not the photodiode is a buried type is irrelevant in these examples, or even if a photogate is used. The same effect that transfer is facilitated by the substrate bias can be obtained.

(Third embodiment)
Next, as a third embodiment, an example in which the dynamic range is widened by moving the bias voltage of the P-well region under the above-described pixel portion in the middle of the charge accumulation period will be described.
FIG. 8 is a timing chart showing an operation example when the bias voltage of the P-well region is changed in the middle of the charge accumulation period. The vertical axis shows the P-well voltage and the horizontal axis shows the passage of time. FIG. 9 is an explanatory diagram showing the relationship between the amount of light received by the PD and the number of accumulated electrons associated with the operation shown in FIG.

As shown in FIG. 8, when the accumulation of photoelectrons in the PD is started, for example, -1V is set. If this is set to 0 V in the middle of the accumulation time, as shown in FIG. 9, the number of electrons stored in the PD is sensitive to the amount of light when the amount of light is small, and becomes insensitive when the amount of light is large.
The reason is as follows. That is, when the P-well region is −1 V, the saturation of the PD is reduced, the PD is saturated with a certain number of electrons, and more than that flows out to the FD.

Here, when the P-well region is set to 0 V, PD saturation increases, so that photoelectrons can be further accumulated.
When the amount of light is small, photoelectrons of the entire accumulation period are collected without saturating the PD. However, when the amount of light is large, electrons exceeding saturation are discarded during the period of -1V in the P-well region, and the sensitivity is reduced accordingly. Will do.
As a result, as shown in FIG. 9, a sensitivity curve having a bend point a is obtained at a certain point, and a greater amount of light can be detected without sacrificing sensitivity in a dark place. That is, the dynamic range is widened.

In the example shown in FIG. 8, the P-well voltage is driven with binary values of -1 V and 0 V. However, if the P-well voltage is changed in increments of -1 V → 0.5 V → 0 V, the bending point of the sensitivity curve is increased. Various sensitivity curves can be realized in combination with appropriate setting of the voltage change time.
Further, when the P-well voltage is continuously changed, a curved sensitivity curve can be obtained instead of bending as shown in FIG.
By using such a method, there is a problem that there is a limitation in the operation range when changing the voltage of the transfer gate disclosed in Patent Document 1 described above, and the dark current when changing the voltage of the reset gate is large. This problem can also be solved.

The method of the third embodiment is independent of the first and second embodiments described above. That is, it is independent of applying a substrate bias at the time of transfer. Of course, the present invention can be implemented together with the configurations of the first and second embodiments.
Although a photodiode is used here as a photoelectric conversion element, even if a photogate is used, saturation can be reduced by the substrate bias, and the same effect can be obtained.
In the third embodiment, an example of a pixel circuit having a PD, a transfer gate, and an FD is described. However, for example, in a pixel circuit that does not have a transfer gate and an FD and is directly connected from the photodiode to the amplification gate, Instead, the reset gate determines the PD saturation and the substrate bias reduces the PD saturation, so the effect is exactly the same.

In the above embodiments, electrons are used as carriers and NMOS pixel transistors are used as a basis. However, it is also obvious that holes can be used as carriers and PMOSs as a basis. In accordance with this, the polarity of the voltage changes appropriately.
Further, the configuration of the pixel transistor is not limited to the example described above, and various configurations can be employed.

Furthermore, the present invention can be applied not only to a CMOS solid-state image sensor but also to a CCD solid-state image sensor.
That is, the CCD type solid-state imaging device has, for example, a plurality of CCD vertical transfer registers for each pixel column in a two-dimensional array, and a CCD horizontal transfer register at the end of each CCD vertical transfer register, and stores in each pixel. The signal charge is sequentially transferred by each transfer register, and the signal charge is converted into an electric signal by a floating diffusion provided at the final end of the CCD horizontal transfer register and output. Such a CCD type solid-state imaging device By applying the above-described substrate bias to the well region of each pixel, it becomes possible to reduce the gate voltage when reading from the photodiode of each pixel to each charge storage portion of the CCD vertical transfer register via the read gate. .

  As described above, according to the solid-state imaging device and the driving method thereof according to the present invention, when the signal charge generated by the photoelectric conversion device is read by the reading unit, by applying a predetermined substrate bias voltage to the well region, Although the potential of the photoelectric conversion element and the readout unit also fluctuate due to potential fluctuations in the well region, the readout amount of the readout unit is suppressed by the presence of the readout drive electrode, and the readout amount of the photoelectric conversion element increases, so that a low readout voltage is obtained. Even in this case, the signal charge of the photoelectric conversion element can be efficiently transferred to the reading unit side, and the reading voltage can be lowered. Alternatively, if the same voltage is used, more charges can be read, and the amount of handled charges can be increased and the dynamic range can be increased.

  In the solid-state imaging device and the driving method thereof according to the present invention, the number of saturated electrons of the photoelectric conversion element is increased over time by changing the substrate bias voltage applied to the well region during the signal charge accumulation period of the photoelectric conversion element. Accordingly, by switching from small to large, the dynamic range can be expanded by avoiding saturation in a bright region without reducing sensitivity in a dark region.

It is a block diagram which shows the example of whole structure of the solid-state image sensor by the example of embodiment of this invention. It is a circuit diagram which shows the structural example of the pixel circuit in the solid-state image sensor shown in FIG. It is explanatory drawing which shows the structure of the potential of the area | region ranging from PD-transfer gate-FD-reset gate-power supply wiring (Vdd) in the solid-state image sensor shown in FIG. FIG. 2 is a plan view illustrating a configuration of a P well region under a pixel unit according to the first embodiment of the solid-state imaging device illustrated in FIG. 1. 5 is a timing chart showing each drive pulse of the pixel circuit in the first embodiment shown in FIG. It is a top view which shows the structure of the P well area | region under the pixel part by 2nd Example of the solid-state image sensor shown in FIG. It is a timing chart which shows each drive pulse of the pixel circuit in 2nd Example shown in FIG. 10 is a timing chart showing an operation example of a change in bias voltage in the P-well region according to the third embodiment of the solid-state imaging device shown in FIG. It is explanatory drawing which shows the relationship between the light reception light quantity of PD accompanying the operation | movement shown in FIG. 8, and the number of accumulation | storage electrons. It is a circuit diagram which shows an example of the pixel circuit in the conventional solid-state image sensor. It is sectional drawing which shows the structure of the photodiode of the solid-state image sensor shown in FIG. 10, and its peripheral part.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor element substrate, 110 ... Pixel part, 111 ... Transfer Tr, 112 ... Amplification Tr, 113 ... Selection Tr, 114 ... Reset Tr, 119 ... Photodiode (PD), 120 ... Constant Current section, 130... Column signal processing section, 140... V selection drive means, 150... H selection means, 160.

Claims (21)

In the well region formed in the semiconductor substrate, a photoelectric conversion element that generates a signal charge according to the amount of received light, and a reading unit that reads the signal charge generated by the photoelectric conversion element at a predetermined read timing,
Voltage reading means for applying a predetermined substrate bias voltage to the well region when the signal charge is read by the reading unit;
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the photoelectric conversion element is provided for each of a plurality of pixels formed in a two-dimensional array on a semiconductor substrate.   3. The well region is formed integrally in a region including all of the plurality of pixels of the two-dimensional array, and a common substrate bias voltage is applied to all the pixels. Solid-state image sensor.   3. The solid-state imaging according to claim 2, wherein the well region is formed by being electrically separated for each row of the plurality of pixels of the two-dimensional array, and an independent substrate bias voltage is applied for each row. element.   The solid-state imaging device according to claim 1, wherein the well region is a p-type well region, and the substrate bias voltage is a negative voltage.   2. The solid state imaging device according to claim 1, wherein each pixel is a CMOS type solid-state imaging device provided with a pixel transistor that converts a signal charge read from the photoelectric conversion device into an electric signal and outputs the electric signal to a signal line. Image sensor.   CCD type having a charge transfer unit that takes in signal charges generated by photoelectric conversion elements of a plurality of pixels and sequentially transfers them, and a common conversion unit that converts the signal charges sequentially transferred by the charge transfer units into electric signals The solid-state image sensor according to claim 1, wherein the solid-state image sensor is a solid-state image sensor. In the well region formed in the semiconductor substrate, a photoelectric conversion element that generates a signal charge according to the amount of received light, and a reading unit that reads the signal charge generated by the photoelectric conversion element at a predetermined read timing,
Voltage accumulation means for changing a substrate bias voltage applied to the well region during a period of signal charge accumulation by the photoelectric conversion element;
A solid-state imaging device.   9. The solid-state imaging device according to claim 8, wherein the photoelectric conversion element is provided for each of a plurality of pixels formed in a two-dimensional array on a semiconductor substrate.   10. The well region is formed integrally in a region including all pixels of the plurality of pixels of the two-dimensional array, and a common substrate bias voltage is applied to all the pixels. Solid-state image sensor.   10. The solid-state imaging according to claim 9, wherein the well region is formed by being electrically separated for each row of the plurality of pixels of the two-dimensional array, and an independent substrate bias voltage is applied for each row. element.   9. The solid-state imaging device according to claim 8, wherein the well region is a p-type well region, and the substrate bias voltage is a negative voltage.   9. The solid-state image sensor according to claim 8, wherein each pixel is a CMOS solid-state imaging device provided with a pixel transistor that converts a signal charge read from the photoelectric conversion element into an electric signal and outputs the electric signal to a signal line. Image sensor.   CCD type having a charge transfer unit that takes in signal charges generated by photoelectric conversion elements of a plurality of pixels and sequentially transfers them, and a common conversion unit that converts the signal charges sequentially transferred by the charge transfer units into electric signals The solid-state image sensor according to claim 8, which is a solid-state image sensor. Solid-state imaging in which a well region formed on a semiconductor substrate is provided with a photoelectric conversion element that generates a signal charge according to the amount of received light, and a reading unit that reads out the signal charge generated by the photoelectric conversion element at a predetermined read timing A device driving method,
A predetermined substrate bias voltage is applied to the well region when the signal charge is read by the reading unit;
A method for driving a solid-state imaging device.   16. The method for driving a solid-state imaging element according to claim 15, wherein the photoelectric conversion element is provided for each of a plurality of pixels formed in a two-dimensional array on a semiconductor substrate.   16. The well region according to claim 15, wherein the well region is electrically integrally formed in a region including all the pixels of the two-dimensional array, and a common substrate bias voltage is applied to all the pixels. A method for driving a solid-state imaging device.   16. The solid-state imaging device according to claim 15, wherein the well region is formed to be electrically separated for each row of the plurality of pixels of the two-dimensional array, and an independent substrate bias voltage is applied to each row. Driving method.   16. The method of driving a solid-state imaging device according to claim 15, wherein the well region is a p-type well region, and the substrate bias voltage is a negative voltage. Solid-state imaging in which a well region formed on a semiconductor substrate is provided with a photoelectric conversion element that generates a signal charge according to the amount of received light, and a reading unit that reads out the signal charge generated by the photoelectric conversion element at a predetermined read timing A device driving method,
A substrate bias voltage applied to the well region is changed during a signal charge accumulation period of the photoelectric conversion element;
A method for driving a solid-state imaging device.   21. The method of driving a solid-state imaging device according to claim 20, wherein the photoelectric conversion element is provided for each of a plurality of pixels formed in a two-dimensional array on a semiconductor substrate.

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