JP2003169256A - Solid-state imaging unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging unit with high sensitivity and high image quality capable of eliminating after-image caused by defective transfer of electric charges and considerably reducing also transfer noise. <P>SOLUTION: A vertical scanning circuit 24 for power supply pulse once brings a high level power supply voltage VD(i) supplied to a drain terminal of a reset transistor 3 to a low level when a transfer transistor 2 and the reset transistor 3 are both turned on after the signal charge transfer operation where an electric charge transfer vertical scanning circuit 23 applies a high level voltage of an electric charge transfer pulse voltage VTX(i) to a gate of the transfer transistor 2. Thus, the electric charges excessively discharged by thermal emission in a non-depletion surface region other than a pinning layer of a photodiode 1A are supplemented by skimming operations from the drain region. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device such as a CMOS imager for picking up an image of a subject.

[0002]

2. Description of the Related Art Conventionally, this amplification type solid-state image pickup device has a plurality of pixel portions arranged in a matrix in the vertical and horizontal directions and a scanning circuit arranged around the plurality of pixel portions. However, this scanning circuit can read pixel data from a plurality of pixel portions. In particular, the plurality of pixel units have an amplification function for each pixel. In addition, the pixel configuration of the plurality of pixel portions has a CMOS configuration that is advantageous for integration with a drive circuit including a scanning circuit and a signal processing circuit in the periphery thereof.
A PS (Active Pixel Sensor) type image sensor is known.

In this APS type image sensor, it is necessary to form a photoelectric conversion section, an amplification section, a pixel selection section and a reset section in one pixel. Further, in the APS type image sensor, usually three to four MOS type transistors (Tr) are used for the amplification section, the pixel selection section and the reset section, in addition to the photoelectric conversion section formed of a photodiode (PD). Has been.

FIG. 4 is a circuit diagram showing a main structure of a conventional amplification type solid-state image pickup device. FIG. 4 shows one photodiode (PD) and four MOS transistors (Tr).
Is used to show a pixel configuration example of an APS type image sensor of PD + 4Tr system. This PD + 4Tr system is based on, for example, “A0.6 μm CMOS Pinned Photodiode ColorIma
ge Technology ”RM Guidash et a1., IEDM Tech.Diges
t, pp927 (1997).

In FIG. 4, an amplification type solid-state image pickup device includes a plurality of APS type image sensors 10 constituting a pixel portion for picking up an image of a subject and a plurality of APS type image sensors 10 provided around the horizontal direction of the pixel portion in the vertical direction in units of rows. A vertical scanning circuit unit 20 for scanning,
A horizontal scanning circuit unit 30 is provided around the vertical direction and horizontally scans each pixel unit on a column-by-column basis.

The APS type image sensor 10 includes a photodiode 1 as an image pickup section (photoelectric conversion section), a transfer transistor 2 (signal transfer section) for transferring signal charges accumulated in the photodiode 1, and a drive terminal. One end (the signal charge detection unit FD) is connected to the transfer transistor 2 and the other end is connected to the power supply line 14, and the reset transistor 3 (reset unit) and one end of the drive terminal are connected to the power supply line 14 for control. An amplification transistor 4 (amplification unit) whose terminal is connected to a connection point (signal charge detection unit FD) of the transistors 2 and 3, and a pixel selection transistor whose other end of the drive terminal of the amplification transistor 4 is connected to one end. 5 (pixel selection unit). The photodiode 1 is used as the PD, and the transistors 2 to 5 are used as the 4Tr, which is a PD + 4Tr system.

The vertical scanning circuit section 20 includes a pixel selection vertical scanning circuit 21, a reset vertical scanning circuit 22, and a charge transfer vertical scanning circuit 23, which are drawn out in the horizontal direction (row direction) for each pixel section in the row direction. It has a plurality of pixel selection clock lines 15, a reset clock line 13 and a charge transfer clock line 12.

One end of a pixel selection clock line 15 connected to the control terminal (gate) of the pixel selection transistor 5 is connected to the pixel selection vertical scanning circuit 21,
For example, the drive pulse voltage VSE (i) is applied from the vertical scanning circuit 21 to the gate of the pixel selection transistor 5 via the pixel selection clock line 15 of the i-th row.

The reset vertical scanning circuit 22 is connected to one end of a reset clock line 13 connected to the control terminal (gate) of the reset transistor 3.
For example, the driving pulse voltage VRS (i) is supplied to the reset vertical scanning circuit 2 via the reset clock line 13 of the i-th row.
2 is applied to the reset gate of the reset transistor 3.

One end of the charge transfer clock line 12 connected to the control terminal (gate) of the transfer transistor 2 is connected to the charge transfer vertical scanning circuit 23. For example, the charge transfer clock line 12 of the i-th row. The drive pulse voltage VTX (i) is applied to the gate of the transfer transistor 2 from the charge transfer vertical scanning circuit 23 via the.

Each of these drive pulse voltages VSE (i),
VRS (i) and VTX (i) are supplied at predetermined timings described later with reference to FIG.

The horizontal scanning circuit section 30 has a plurality of vertical signal lines 16 drawn out in the vertical direction (column direction) for each pixel section in the column direction, and a horizontal signal line 36 for outputting a signal to the outside.
It has a horizontal scanning circuit 34 for sequentially outputting the output signal on each vertical signal line 16 to a horizontal signal line 36 in a time series and a drive unit thereof.

A load transistor 17 is connected to the vertical signal line 16 for each column. The load transistor 33 is also connected to the horizontal signal line 36. Vertical signal line 1
The output signal on 6 is transmitted to the horizontal signal line 36 by the drive transistor 31 and the horizontal selection switch transistor 32 which form the drive section.

The drive transistor 31 is driven by inputting the output signal of the vertical signal line 16 to its control terminal (gate). Horizontal selection switch transistor 32
Is driven by inputting a horizontal scanning signal from the horizontal scanning circuit 34 to the control terminal (gate) via the horizontal scanning signal line 35. By driving the drive transistor 31 and the horizontal selection switch transistor 32, the power supply voltage V
D is output to the horizontal signal line 36 through the drive transistor 31 and the horizontal selection switch transistor 32, and the signal output to the horizontal signal line 36 is the buffer amplifier 37.
After being amplified by, the output signal OS is output to the outside.

FIG. 5 is a timing chart of various drive pulse voltage signals in the amplification type solid-state image pickup device of FIG. The circuit operation of the PD + 4Tr method shown in FIG. 4 will be described with reference to FIG. Note that VD (i) is a constant power supply voltage. Each driving pulse voltage VSE (i), VRS (i), V of the i-th row of each pixel portion arranged in a matrix
TX (i) and each drive pulse voltage VSE of the (i + 1) th row
Since (i + 1), VRS (i + 1), and VTX (i + 1) are similar drive pulse voltage waveforms that are output with one horizontal scanning period (1H), only the i-th row will be described here.

First, in the period t1, since the reset drive pulse voltage VRS (i) is on, the reset gate RS (i) of the reset transistor 3 is turned on, and the potential of the reset gate RS (i) is increased. Since the potential rises, charge transfer from the charge detection unit FD to the drain of the reset transistor 3 occurs, and the charge detection unit FD
Is reset to the power supply voltage VD.

Next, in the period t2, since the reset drive pulse voltage VRS (i) is turned off, the reset gate RS (i) of the reset transistor 3 is turned off, but the charge detection unit FD is reset. Potential of VD is held.

Further, since the drive pulse voltage VTX (i) for charge transfer is turned on in the period t3, the transfer gate TX (i) of the transfer transistor 2 is turned on.
Is turned on and the potential potential of the transfer gate TX (i) rises, so that the signal charge accumulated in the photodiode 1 of the photoelectric conversion unit is transferred to the signal charge detection unit FD.

Further, during the period t4, the drive pulse voltage VTX (i) for charge transfer is off, so that the transfer gate TX of the transfer transistor 2 is transferred.
Although (i) is turned off, the signal charge detection unit FD holds the potential from the photodiode 1 at the time of signal charge transfer.

Further, during the period t6, both the drive pulse voltage VTX (i) for charge transfer and the drive pulse voltage VRS (i) for reset are turned on, so that the transfer gate TX (i),
Since the reset gates RS (i) of the reset transistor 3 are both turned on and the potential potentials of both gates rise, the gate RS of the reset transistor 3 is removed from the photodiode 1 and the signal charge detection unit FD.
Charge transfer occurs to the drain via (i). As a result, the potential of the photodiode 1 depends on the gate high level of the transfer transistor 2 (φT
H), and the potential of the signal charge detection unit FD is reset to the power supply voltage VD.

Further, during the period t7, the drive pulse voltage VTX (i) for charge transfer is turned off, so that the transfer gate TX (i) of the transfer transistor 2 is transferred.
Is turned off, and the photodiode 1 is electrically cut off from the external circuit. This period t7 is a preliminary period for electrically disconnecting the signal charge detection unit FD from the external circuit after holding the potential of the photodiode 1 at the potential (φTH) depending on the transfer gate TX (i). .

Since the drive pulse voltage VSE (i) for pixel selection is on during the above periods t1 to t4,
Driving pulse voltage VSE of the pixel selection clock line 15
(I) is applied to the gate of the pixel selection transistor 5, and the pixel selection transistor 5 is in the ON state. Therefore, in the period t1 to t4, the detection signal in the signal charge detection unit FD is amplified by the amplification transistor 4 and output as a signal to the vertical signal line 16.

[0023]

In the circuit configuration shown in FIG. 4 and the circuit operation shown in FIG. 5, the photodiode 1 is used.
When the charge is transferred from the signal charge detecting section FD to the signal charge detecting section FD via the transfer transistor 2, the following problems occur. This problem will be described with reference to FIGS. 6 (a), 6 (b) and 7 (a), 7 (b).

FIG. 6A is a pixel sectional view of a conventional amplification type solid-state image pickup device, and FIG. 6B is a potential potential distribution diagram corresponding to the pixel sectional view of FIG. 6A. Note that here, an n-channel type in which signal charge is electrons is shown.

In FIG. 6A, a photodiode 1, a transfer transistor 2, a charge detection unit 104, a reset transistor 3 and a drain 105 are formed in this order from left to right on a p-type substrate 100. Reference numeral 106 denotes an amplifier circuit (buffer amplifier 37 or the like).

In FIG. 6B, when the photoelectrically converted charges are transferred from the photodiode 1 to the charge detection unit 104, the potential of the photodiode 1 after reading the signal charges is used for transfer due to the heat emission effect. Transistor 2
Cannot remain at the high-level potential φTH of the gate of, and depends on the transfer period and the number of times of reading. That is, the amount of charges accumulated in the next accumulation period is affected, and an afterimage is generated. This is called an incomplete charge transfer mode. Further, in the case of FIGS. 6A and 6B, transfer noise occurs when the charges are transferred from the photodiode 1 to the charge detection unit 104, and the amount ΔVn thereof is expressed by the following equation (1). To be done.
This is `` Analysis and enhancement of low-light
-level performance of photodiode-type CMOS active
pixel imagers operated with sub-threshold reset '',
Bedabrata Pain et al., IEEE Workshop on CCDs and Ad
vanced Image Sensors 1999, p.140.

ΔVn = √ (kTCj / 2) (1) Here, Cj is the capacitance of the photodiode portion, which is mainly the junction capacitance, and its reduction is difficult.

As a means for solving the above problems, a complete charge transfer method using a pin type (embedded type) photodiode is disclosed in, for example, "New LV-BPD (Low Buried Photo-Diode)".
for CMOS Imager ”Ikuko Inoue et al., IEDMT Tech.Dige
st, pp883 (1999). This is shown in FIGS. 7 (a) and 7 (b).

FIG. 7A is a pixel sectional view of another conventional amplification type solid-state image pickup device, and FIG. 7B is a potential potential distribution diagram corresponding to the pixel sectional view of FIG. 7A.

In FIG. 7A, the photodiode 1
A charge storage layer 101 of a relatively low concentration of n-type,
A high concentration p-type pinning layer 102 for pinning the potential is formed on the surface side. In this configuration example, the charge storage layer 101 and the pinning layer 102
It is possible to completely deplete the charge storage layer 101 after the signal charge is transferred from the photodiode 1 to the signal charge detection unit 104 (FD) by optimizing the formation conditions of (1). In this case, the photodiode potential becomes the depletion potential (φdep), and if it is lower than the transfer gate high level potential (φTH), it is possible to completely transfer the charges from the photodiode 1 to the charge detection unit 104. This is called a complete charge transfer mode.

However, in practice, the charge storage layer 101
It is extremely difficult to optimize the conditions for forming the pinning layer 102. That is, in FIG. 7A, if the position of the gate side end of the transfer transistor 2 of the pinning layer 102 is slightly enlarged, that is, the pinning layer 1
When 02 is shifted in the gate direction of the transfer transistor 2, a potential barrier 110 as shown in FIG. 7B is formed. On the contrary, the pinning layer 10
When the position of 2 on the transfer gate side end is slightly reduced, a potential pocket 111 as shown in FIG. 7B is formed. In either case of the potential barrier 110 and the potential pocket 111, an afterimage is generated as a cause of incomplete charge transfer.

The present invention has been made in view of the above circumstances, and provides a high-sensitivity and high-quality solid-state image pickup device which can eliminate the afterimage phenomenon caused by defective charge transfer and can significantly reduce transfer noise. The purpose is to

[0033]

A solid-state image pickup device of the present invention has one or a plurality of pixel portions, and the pixel portion is provided with a signal charge detection portion from a photoelectric conversion element through a transfer gate. A predetermined semiconductor region is provided from the signal charge detection unit via the reset gate, and the photoelectric conversion element is provided after the reset operation by the power supply voltage (drain voltage or source voltage) from the semiconductor region (drain region or source region) to the charge detection unit. In the solid-state imaging device performing the signal charge transfer operation from the signal charge detection unit to the signal charge detection unit, at least a part of the semiconductor surface area of the photoelectric conversion element is covered with the pinning layer, and the transfer gate and the reset after the signal charge transfer operation are performed. When the gate is turned on, the power supply voltage (drain voltage or source voltage) to the semiconductor region (drain region or source region) is increased. Scan voltage) are those having once power supply voltage control means for changing the low-level potential high level potential of (the drain potential control means or the source potential control means), the object is achieved.
The reset operation and the signal charge transfer operation are to reset the potential of the signal charge detection unit from the semiconductor region via the reset gate and then transfer the signal charge of the photoelectric conversion element to the signal charge detection unit via the transfer gate. This is an operation, and the signal charge is detected by this operation. Also,
Here, the power supply voltage is a voltage supplied from a voltage source (here, a voltage applied to the semiconductor region of the power supply pulse voltage VD, specifically, a drain voltage or a source voltage), and is not limited to a generally used power supply. Alternatively, it may be a voltage newly generated from a commonly used power supply, for example, an intermediate voltage of a normal power supply voltage.

Further, preferably, the pinning layer in the solid-state image pickup device of the present invention is provided in a region other than a region adjacent to the transfer gate. That is, at least the region adjacent to the transfer gate in the semiconductor surface region of the photoelectric conversion element is not covered with the pinning layer.

Further, in the solid-state image pickup device of the present invention, preferably, the potential of the signal charge storage portion under the pinning layer is depleted, and the potential of the signal charge storage portion is depleted when the transfer gate is in the ON state. The potential is lower than the channel potential under the transfer gate.

Further, preferably, in the solid-state imaging device of the present invention, the high level potential of the power supply voltage to the semiconductor region is lower than the channel potential below the reset gate when the reset gate is in the ON state, and the semiconductor region. The low-level potential of the power supply voltage to the transfer gate is lower than the channel potential under the transfer gate when the transfer gate is in the ON state.

Further, preferably, the solid-state image pickup device of the present invention comprises an amplification section for amplifying a potential change of the signal charge detection section,
In a solid-state imaging device having a pixel selection unit capable of selectively reading the output signal of the amplification unit, after the read operation of the output signal by the pixel selection unit, the power supply voltage to the semiconductor region is temporarily changed to a low level potential. Then, the potential of the surface region other than the pinning layer is preset to a constant potential after each read operation.

Further, preferably, in the solid-state image pickup device of the present invention, the period for transferring the signal charge from the photoelectric conversion element to the signal charge detecting portion is T1, and the potential of the semiconductor region is changed from the low level potential to the high level potential. When the period from when the transfer gate is turned off to when the transfer gate is turned off is T2, T1 = T2.

Further, preferably, in the solid-state image pickup device of the present invention, the plurality of pixel portions are arranged in a matrix in the row and column directions, and the power supply potential control means is independent in the semiconductor region in units of horizontal rows. The scanning circuits are connected to each other, and a pulsed driving voltage is sequentially applied to the semiconductor regions in units of rows by the scanning circuits.

Further, preferably, in the solid-state image pickup device of the present invention, the power supply to the semiconductor region is different from the power supply to the amplification section.

The operation of the above structure will be described below.

The power supply potential control means performs a series of operations for temporarily setting the high level power supply potential to the semiconductor region to the low level potential when the transfer gate and the reset gate after the signal charge transfer operation are turned on. As a result, the charges excessively discharged by heat emission in the non-depleted surface region other than the pinning layer of the photoelectric conversion element are filled by the skimming operation from the semiconductor region. As a result, the afterimage phenomenon and noise are significantly suppressed.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a case where the present invention is applied to an amplification type solid-state image pickup device as an embodiment of the solid-state image pickup device of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a main configuration of an embodiment of the amplification type solid-state image pickup device of the present invention. In addition,
Hereinafter, members having the same effects as those of the conventional art are designated by the same reference numerals.

In FIG. 1, an amplification type solid-state image pickup device 50.
Is a plurality of pixel portions 10A for subject imaging arranged in a matrix in the row direction and the column direction, and a vertical scanning circuit portion 20A provided around the horizontal direction and scanning each pixel portion in the vertical direction row by row. And a horizontal scanning circuit section 30 provided around the vertical direction and scanning each pixel section in the horizontal direction in units of columns.

The pixel section 10A is an image pickup section (photoelectric conversion element).
Photodiode 1A as a photo diode 1
Transfer transistor 2 as a signal transfer unit for transferring the signal charge accumulated in A to the signal charge detection unit FD
A reset transistor 3 as a reset unit for resetting the potential of the signal charge detection unit FD from a drain region as a semiconductor region to which a power supply pulse voltage VD (semiconductor region applied voltage) as a power supply voltage is supplied; VOD is supplied via a power supply potential supply line 141 described later, and the amplification transistor 4 as an amplification unit that amplifies the signal according to the potential of the signal charge detection unit FD and the output signal amplified by the amplification transistor 4 can be read. And a pixel selection transistor 5 as a pixel selection unit.

The vertical scanning circuit portion 20A includes a pixel selection vertical scanning circuit 21, a reset vertical scanning circuit 22A, a charge transfer vertical scanning circuit 23A, and a power supply pulse vertical scanning circuit 24 (power supply potential control means). A plurality of pixel selection clock lines 15 and a reset clock line 1 that are drawn out in the horizontal direction (row direction) for each pixel portion in the direction.
3, a charge transfer clock line 12, and a power supply potential supply line 140 as a power supply line.

To the pixel selection vertical scanning circuit 21, one end of a pixel selection clock line 15 connected to the control terminal (gate) of the pixel selection transistor 5 is connected,
For example, when the high-level potential of the drive pulse voltage VSE (i) is selected through the pixel selection clock line 15 of the i-th row during pixel selection (periods t1 to t4 in FIG. 3 described later), the vertical scanning circuit 2
1 to the gate of the pixel selection transistor 5.

One end of the reset clock line 13 connected to the control terminal (gate) of the reset transistor 3 is connected to the reset vertical scanning circuit 22A, and for example, via the reset clock line 13 of the i-th row. The high-level potential of the drive pulse voltage VRS (i) is applied to the gate of the reset transistor 3 from the reset vertical scanning circuit 22A at the time of reset (periods t1, t5 to t7 in FIG. 3 described later).

One end of the charge transfer clock line 12 connected to the control terminal (gate) of the transfer transistor 2 is connected to the charge transfer vertical scanning circuit 23A. For example, the signal charge transfer clock line of the i-th row. 12
The high-level potential of the drive pulse voltage VTX (i) is transferred via the signal charge transfer period (periods t3, t5, t in FIG.
6) is applied to the gate of the transfer transistor 2 from the charge transfer vertical scanning circuit 23A.

In the vertical scanning circuit 24 for power supply pulse,
One end of a power supply potential supply line 140 connected to the drain terminal (drain region as a semiconductor region) of the reset transistor 3 is connected, and for example, the power supply pulse voltage VD is supplied via the power supply potential supply line 140 of the i-th row.
When the transfer transistor 2 and the reset transistor 3 are turned on to the low level potential of (i) after the signal charge transfer operation and immediately after the pixel selection operation (see FIG.
In the period t5), the low-level potential is applied to the drain terminal (drain region) of the reset transistor 3 for a predetermined period from the vertical scanning circuit 24 for supplying the power potential so as to be changed once.

The power supply pulse voltage VD of the drain potential of the reset transistor 3 and the power supply fixed voltage VOD of the source follower of the amplification transistor 4 are power supply voltages supplied from different power supplies. Since this source follower is driven row by row, the source follower fixed voltage VOD
When is extracted in the horizontal direction, the drive current is concentrated on the power supply line in units of rows, and the influence of the wiring resistance may appear in the output signal from the pixel portion. On the other hand, the source follower power supply of the present invention is connected to the source of the amplifying transistor 4 in the column direction in the vertical direction via the power supply potential supply line 141, and it becomes possible to avoid concentration of the drive current. on the other hand,
The current flowing in the reset drain region is the current for discharging the signal charges of the light receiving unit and the charge / discharge of the capacitance, and since it is small, even if it is connected in the horizontal direction via the power supply potential supply line 140, the concentration of the drive current or the like is reduced. There is no problem.

The horizontal scanning circuit section 30 includes a plurality of vertical signal lines 16 drawn in the vertical direction (column direction) for each pixel section in the column direction, and a horizontal signal line 36 for outputting a signal to the outside.
It has a horizontal scanning circuit 34 for sequentially outputting the output signal on each vertical signal line 16 to the horizontal signal line 36 in time series and a drive unit thereof.

A load transistor 17 is connected to the vertical signal line 16 for each column, and an output signal on the vertical signal line 16 is sent to a horizontal signal line 36 via a drive transistor 31 and a horizontal selection switch transistor 32. Transmitted. The horizontal selection switch transistor 32 is driven by a drive signal from the horizontal scanning circuit 34.

The load transistor 3 is connected to the horizontal signal line 36.
3 is connected. The signal on the horizontal signal line 36 is amplified by the buffer amplifier 37 and becomes the output signal OS.

Here, the effect of reducing the afterimage phenomenon and transfer noise due to charge transfer failure based on the semiconductor structure of the pixel portion 10A of the present invention and its control will be described.

2A and 2B are views showing a pixel portion of the amplification type solid-state image pickup device of FIG. 1. FIG. 2A is a plan view thereof, FIG. 2B is a sectional view thereof, and FIG. is there.

2A and 2B, the pixel portion 10A of the amplification type solid-state image pickup device 50 of the present invention includes a photodiode 1A as a photoelectric conversion element and a transfer gate of a transfer transistor 2. The signal charge detection unit 104 (FD) is provided, and the drain region 105 is provided from the charge detection unit 104 (FD) via the reset gate of the reset transistor 3.

The photodiode 1A is constructed by forming an n-type semiconductor layer 101 on a p-type semiconductor substrate 100 and a pinning layer 102 made of a high-concentration p-type semiconductor layer on a part of the surface thereof. In the high-concentration p-type semiconductor region of the n-type semiconductor layer 101 covered with the pinning layer 102, the transfer transistor 2 is turned on and completely depleted during signal charge transfer from the photodiode 1A to the charge detection unit 104. , Its potential is φd
p. The potential potential φdep under the pinning layer 102 must be lower than the potential potential φTH when the transfer transistor 2 is in the ON state. That is, the potential of the signal charge storage portion when the signal charge storage portion under the pinning layer 102 is depleted must be lower than the potential below the transfer gate channel when the transfer transistor 2 is in the ON state.

On the other hand, in the n-type semiconductor layer 101, a region 103 adjacent to the gate of the transfer transistor 2
Are not covered with the pinning layer 102. That is, the pinning layer 102 is provided in a region other than the region 103 adjacent to the transfer gate of the transfer transistor 2. With such a surface condition, conventionally,
As described above, the incomplete transfer mode is set and an afterimage occurs.

However, in the present invention, the after-image does not occur in the area 103 due to the following control operation. As shown in FIG. 2C, the drain region 105 is not the DC fixed potential but the power supply pulse voltage VD which becomes the high level (VDH) and the low level (VDL). Here, VDH is set to a potential slightly higher than the gate high level potential φRH of the reset transistor 3, and VDL is set to a potential slightly lower than the gate high level potential φTH of the transfer transistor 2. The drain region 105 becomes VDL immediately after the normal reset operation and transfer operation are completed and the pixel selection operation is completed. That is, after the normal pixel selection operation (the period from tl to t4 in FIG. 3 described later) is completed, the gates of the transfer transistor 2 and the reset transistor 3 are set to the high level again,
The drain region 105 is once set to VDL and is operated to return to VDH again. After that, the gate of the transfer transistor 2 returns to the low level. By this series of operations, the charges excessively discharged by heat emission in the non-depleted region 103 are filled by the skimming operation from the drain region 105. This suppresses the afterimage phenomenon. It is only in the non-depleted region 103 that charges are injected and discharged by this skimming operation. When the capacitance of the non-depleted region 103 is C0, the amount of noise ΔVn generated in the non-depleted region 103 due to the skimming operation is expressed by the following equation.

ΔVn = √ (kTC0 / 2) (2) Comparing the above equation (2) with the above equation (1), FIG.
As is clear from the comparison between (c) and FIG. 6 (b), C0
≪Cj. Therefore, in the present invention, the formula (1)
The amount of noise ΔVn represented by can be significantly reduced. That is, with the configuration of the present invention, it is possible to suppress the afterimage and also significantly suppress the noise.

As another advantage of the present invention, the formation of the non-depleted region 103 is allowed. Therefore, conventionally, it becomes very easy to form a pin-type photodiode that requires extremely strict positional accuracy in order to prevent the formation of a potential barrier and a potential pocket. Furthermore, by making most of the photodiode region a pin type, it is possible to significantly reduce the dark current, which was an important factor of the photodiode performance.

With the above configuration, the operation will be described below.

FIG. 3 is a timing chart of each drive pulse voltage for explaining the operation of the amplification type solid-state imaging device of FIG. 1 having the pixel portion of the semiconductor structure of FIG. 2 (b). In addition, each drive pulse voltage VSE of the i-th row and the i + 1-th row
(I), VRS (i), VTX (i), VSE (i +
1), VRS (i + 1), VTX (i + 1) and power supply pulse voltages VD (i), VD (i + 1) have similar pulse voltage waveforms with one horizontal scanning period (1H), and therefore, for the i-th row Only explained.

In the present invention, the power supply pulse voltage VD of the reset drain voltage also changes in synchronization with the read operation. The voltage waveform VD (i) of the power supply pulse voltage VD at this time is
As shown in FIG. 3, it changes in the horizontal direction row by row.

As shown in FIG. 3, first, in the period tl,
Since the gate RS (i) of the reset transistor 3 is turned on and the potential potential of the gate RS (i) rises, charge transfer from the charge detection unit FD to the drain region of the reset transistor 3 occurs and the potential of the charge detection unit FD changes. The high level potential VD (H) of the power supply voltage VD is reset.

Next, in the period t2, the gate RS (i) of the reset transistor 3 is turned off, but the electric potential VD (i) at the time of reset is held in the charge detection portion FD.

Further, in the period t3, the gate TX (i) of the transfer transistor 2 is turned on, and the potential potential of the gate TX (i) rises, so that the signal charge accumulated in the photodiode 1A is charged.
Forwarded to D. Due to this charge transfer, under the pinning layer 102 in the depletion region of the photodiode 1A, the potential becomes φdep, but in the non-depleted region 103, the potential is not fixed due to the heat emission effect.

Further, in the period t4, the gate TX (i) of the transfer transistor 2 is turned off,
The signal charge detection unit FD holds the potential at the time of signal charge transfer. In the periods t1 to t4 so far, the reset drain voltage VD (i) and the drive pulse voltage VSE
(I) holds the high level potential VD (H).
That is, in the period tl to t4, the drive pulse voltage VSE (i) of the pixel selection clock line 15 is applied to the gate of the pixel selection transistor 5, and the pixel selection transistor 5 is in the ON state, so the signal charge detection unit FD The output signal amplified in accordance with the detection signal is output to the vertical signal line 16 via the pixel selecting transistor 5.

Further, in the period t5, the reset drain voltage VD (i) of the reset transistor 3 changes to the low level potential VD (L), the gate TX (i) of the transfer transistor 2 and the gate RS (of the reset transistor 3 Since i) is both turned on, charges are injected from the drain region of the reset transistor 3 into the non-depleted region 103 of the photodiode 1A.

Further, in the period t6, the reset drain voltage VD (i) of the reset transistor 3 becomes the high level potential VD (H) again, and the gate TX (i) of the transfer transistor 2 and the gate RS (i of the reset transistor 3 are obtained. ) Is in the ON state, the gate TX (i) of the transfer transistor 2 is included in the charge amount injected into the non-depleted region 103 of the photodiode 1A.
Is returned to the drain region of the reset transistor 3 again, and the potential of the non-depleted region 103 of the photodiode 1A is reduced to the potential φ.
It is preset to TH. Since the potential of the non-depleted region 103 of the photodiode 1A at this time is the same as the potential during the operation in the period t3, the state after the read operation can be always kept constant. As a result, the afterimage phenomenon does not occur.

Further, in the period t7, the drive pulse voltage VTX (i) for charge transfer is turned off, so that the transfer gate TX (i) of the transfer transistor 2 is transferred.
Is turned off, and the photodiode 1A is electrically cut off from the external circuit. This period t7 is a preliminary period for electrically disconnecting the charge detection unit FD from the external circuit after holding the potential of the photodiode 1A at the potential (φTH) depending on the transfer gate TX (i).

As described above, according to the present embodiment, since the non-depleted region 103 is allowed to be formed in a part of the surface of the pin type photodiode 1A, the photodiode 1A can be formed very easily. Become. Moreover, the afterimage can be eliminated by the skimming operation. Further, by making most of the photodiode region a pin type, it is possible to significantly reduce the dark current, which was an important factor in the photodiode performance. In addition to these, since the capacitance of the non-depleted region 103 can be made extremely small, it is possible to significantly reduce transfer noise. As described above, the present invention is extremely useful for forming a high performance image sensor.

The potential change due to the heat release effect changes logarithmically. Therefore, of the above-mentioned periods, the period t
By setting 3 = period t6, the potential change in each period can be made the same. From the above, in the present invention, it is desirable that the period t3 = the period t6.

In the circuit example shown in FIG. 2, the power supply potential supply line 140 for supplying the reset drain voltage connected to the drain region of the reset transistor 3 and the power supply potential supply line 141 of the source follower are different circuits. However, the present invention is not limited to this. That is, since the drive current flows through the source follower in the period t1 to the period t4 in FIG. 3, the power supply pulse voltage signal VD from the power supply pulse vertical scanning circuit 24 is supplied.
Pulse driving can be performed in time series by (i) or the like. Therefore, if the wiring resistance is not affected even if the drive current of the source follower is concentrated on the power supply line of each row, although not shown, the power supply potential supply line 141 of the source follower and the power supply potential supply for supplying the reset drain voltage are not shown. A new power supply pulse voltage signal VD (i) from the vertical scanning circuit 24 for power supply pulse, which is commonly connected to the line 140.
May be applied.

[0077]

As described above, according to the present invention, the power supply potential control means temporarily sets the high level power supply potential to the semiconductor region to the low level potential when the transfer gate and the reset gate after the signal charge transfer operation are turned on. Therefore, the charges excessively discharged by heat emission in the non-depleted surface region other than the pinning layer of the photoelectric conversion element are filled by the skimming operation from the semiconductor region. As a result, it is possible to eliminate the afterimage phenomenon that has conventionally been caused by defective charge transfer and also to significantly reduce transfer noise, so that it is possible to obtain a high-sensitivity and high-quality solid-state imaging device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part configuration in an embodiment of an amplification type solid-state imaging device of the present invention.

2A and 2B are diagrams for explaining a pixel portion of the amplification type solid-state imaging device of FIG. 1, in which FIG. 2A is a plan view thereof, FIG. 2B is a sectional view thereof, and FIG. is there.

3 is a timing chart of each drive pulse voltage in the amplification type solid-state imaging device of FIG.

FIG. 4 is a circuit diagram showing a main configuration of a conventional amplification type solid-state imaging device.

5 is a timing chart of each drive pulse voltage in the amplification type solid-state imaging device of FIG.

FIG. 6A is a pixel cross-sectional view of a conventional amplification type solid-state imaging device, and FIG. 6B is a potential potential distribution diagram corresponding to the pixel cross-section of FIG.

7A is a pixel cross-sectional view of another conventional amplification type solid-state imaging device, and FIG. 7B is a potential potential distribution diagram corresponding to the pixel cross-section of FIG. 7A.

[Explanation of symbols]

50 Amplification type solid-state imaging device 10A pixel part 1A photodiode 100 p-type semiconductor substrate 101 n-type semiconductor layer 102 pinning layer 103 Transfer gate adjacent area 2 Transistor for transfer 104 (FD) Signal charge detection unit 3 Reset transistor 105 drain region (semiconductor region) 4 amplification transistor 5 Pixel selection transistor 20A vertical scanning circuit section 21 Vertical scanning circuit for pixel selection 22A reset vertical scanning circuit 23A Vertical scanning circuit for charge transfer 24 Vertical scanning circuit for power supply potential supply 15 pixel selection clock line 13 Reset clock line 12 Charge transfer clock line 140, 141 Power supply line FD signal charge detector VD power supply pulse voltage VOD power supply fixed voltage

Claims (8)

[Claims] 1. A pixel unit having one or a plurality of pixel units, wherein the pixel unit is provided with a signal charge detection unit from a photoelectric conversion element via a transfer gate, and from the signal charge detection unit to a predetermined unit via a reset gate. In a solid-state imaging device provided with a semiconductor region and performing a signal charge transfer operation from the photoelectric conversion element to the signal charge detection unit after a reset operation by a power supply voltage from the semiconductor region to the charge detection unit, At least a part of the semiconductor surface region is covered with the pinning layer, and when the transfer gate and the reset gate are turned on after the signal charge transfer operation, the high level potential of the power supply voltage to the semiconductor region is once set to low. A solid-state imaging device having power supply potential control means for changing to a level potential. 2. The pinning layer is provided in a region other than a region adjacent to the transfer gate.
The solid-state imaging device described. 3. The potential of the signal charge storage portion when the signal charge storage portion under the pinning layer is depleted is lower than the potential of the transfer gate lower channel when the transfer gate is in the ON state. The solid-state imaging device according to claim 1 or 2. 4. A high level potential of the power supply voltage to the semiconductor region is lower than a channel potential under the reset gate when the reset gate is in an ON state, and a low level potential of the power supply voltage to the semiconductor region. 4. The solid-state imaging device according to claim 1, wherein is a potential lower than a channel potential under the transfer gate when the transfer gate is in an ON state. 5. A solid-state imaging device comprising: an amplification section for amplifying a potential change of the signal charge detection section; and a pixel selection section capable of selectively reading an output signal of the amplification section. The power supply voltage to the semiconductor region is temporarily changed to a low level potential after the read operation of the output signal, and the potential of the surface region other than the pinning layer is preset to a constant potential after the read operation. Alternatively, the solid-state imaging device according to item 2. 6. The transfer gate is turned off after changing a potential of the semiconductor region from a low level potential to a high level potential in a period T1 in which a signal charge is transferred from the photoelectric conversion element to the signal charge detection unit. The solid-state image pickup device according to claim 1, wherein T1 = T2, where T2 is the period up to. 7. The plurality of pixel portions are arranged in a matrix in the row and column directions, and the power supply potential control means is composed of a scanning circuit independently connected to the semiconductor region in horizontal row units. The scanning circuit sequentially applies a pulsed drive voltage to the semiconductor region row by row.
The solid-state imaging device described. 8. The solid-state imaging device according to claim 5, wherein the power supply to the semiconductor region is different from the power supply to the amplifier.