JP2007128978A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is provided with an opening with a straight part and a corner in a gate electrode and an LDMOS structure wherein a channel formation area and source area are formed by self-aligning diffusion from the opening of the gate electrode and can improve withstand voltage without inducing an increase in on-state resistance, and to provide its manufacturing method. <P>SOLUTION: A gate electrode 3 having an opening 3a wherein a straight part and a corner part are formed is formed on an n-type silicon substrate 1 with a gate oxide film 2 in-between, and a p-channel formation area 4 and an n<SP>+</SP>-source area 5 are formed by self-aligning diffusion from the opening 3a in the surface layer of the substrate 1. A low-concentration impurity diffusion area 10 is formed by self-aligning diffusion from the opening 3a in the surface layer of the substrate 1 inside the area 4 and outside the area 5, and it is of an n-type and is lower in impurity concentration than the source area 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

As a general technique for reducing the on-resistance of an LDMOS transistor, a mesh gate structure cell is known as described in the prior art section of Patent Document 1. Specifically, as shown in FIGS. 16 and 17, a part of the polysilicon forming the gate electrode is removed in a square to form the source opening 105 and the drain opening 106, and the two are alternately arranged. . A P-type channel formation region 103 and an N-type source region 104 are formed by self-aligned diffusion (Diffusion Self-Align) from the source opening 105. The drain opening 106 is doped with high-concentration N-type impurities to form an impurity diffusion region 102 for making a low ohmic contact when the electrodes are connected.
Japanese Patent No. 2626139

  However, in the case of the mesh gate cell as described above, the impurity concentration profile in the channel formation region is different between the corner portion (A portion in FIG. 16) and the straight portion (B portion in FIG. 16) of the source opening 105. Occurs.

A more detailed description will be given with reference to FIG. In FIG. 18, as a planar structure, source cells (indicated by S in the figure) and drain cells (indicated by D in the figure) are alternately arranged vertically and horizontally. A vertical cross section (AA cross-sectional view) at the center of the source cell and a vertical cross section (BB cross-sectional view) at the corner of the source cell are arranged on the N-type silicon substrate 110 via the gate oxide film 111. A gate electrode 112 is formed. A P well region 113 and an N ⁺ source region 114 as channel forming regions are formed in the surface layer portion of the silicon substrate 110 in the rectangular source cell opening 112 a in the gate electrode 112. Here, when the impurity for forming the P well region 113 as the channel formation region diffuses in the lateral direction, the corner portion becomes thinner due to the two-dimensional effect, and the impurity concentration profile of the P well region 113 becomes the source cell opening. The corner portion and the straight portion of the portion 112a are different. As a result, as shown in FIG. 19, with respect to the channel concentration (impurity concentration), the corner portion (BB cross section) of the gate electrode opening is lower than the straight portion (AA cross section) of the gate electrode opening. End up. That is, regarding the substrate surface concentration of the PN junction formed in the P well region 113 and the N ⁺ source region 114, the linear portion concentration α and the corner portion concentration β of the gate electrode opening portion are the linear portion concentration α. The density β of the corner portion becomes lower than (α> β). As a result, the threshold voltage Vt for the punch-through breakdown voltage of the element is determined at the corner portion.

  Therefore, in order to ensure the punch through breakdown voltage of the element, it is necessary to set the P well region 113 as the channel formation region to be darker. For this reason, if the P well region 113 in the straight portion of the gate electrode opening, which becomes the majority of the current path during device operation, is darkened, there arises a problem that the on-resistance increases as a result. More specifically, as shown in FIG. 20, when an LDMOS transistor with a stripe structure (without a gate corner) and an LDMOS transistor with a mesh structure (with a gate corner) are compared, the corner portion of the gate electrode opening becomes Vt-controlled. The threshold voltage Vt is lower in the mesh structure (with the gate corner) than in the stripe structure (without the gate corner). Therefore, if the P well region 113 is thickened to ensure the punch-through breakdown voltage, the on-resistance Ron is dominated by the P-well region 113 in the straight portion of the gate electrode opening, leading to an increase in on-resistance.

  The present invention has been made paying attention to the above-mentioned problems, and its purpose is to have an opening in which a straight portion and a corner portion are formed in the gate electrode, and to be self-aligned from the opening of the gate electrode. An object of the present invention is to provide a semiconductor device having an LDMOS structure in which a channel formation region and a source region are formed by appropriate diffusion and capable of improving the breakdown voltage without causing an increase in on-resistance, and a method for manufacturing the same. .

  The invention according to claim 1 is formed by self-aligned diffusion from the opening of the gate electrode in the surface layer portion of the semiconductor substrate inside the channel formation region and outside the source region, The gist of the semiconductor device includes a low-concentration impurity diffusion region having an impurity concentration lower than that of the source region.

  According to the first aspect of the present invention, the concentration of the corner portion of the gate electrode opening is lower than that of the straight portion during self-aligned diffusion from the opening of the gate electrode with respect to the channel formation region. Similarly, in the impurity diffusion region, the concentration of the corner portion of the gate electrode opening is lower than that of the straight portion. As a result, the impurity concentration of the channel formation region at the substrate surface at the PN junction formed by the channel formation region and the low concentration impurity diffusion region at the corner portion of the opening of the gate electrode is changed between the channel formation region and the source region. Can be made higher than the impurity concentration of the channel formation region on the substrate surface at the PN junction formed by (can be increased by Δβ in FIG. 2), and the punch-through breakdown voltage can be improved. . Therefore, unlike the prior art, it is not necessary to set the channel formation region to be darker in order to ensure the breakdown voltage of the device (the channel formation region in the straight portion of the gate electrode opening that becomes the most current path during device operation is darkened). (Without) an increase in on-resistance can be avoided.

  Thus, an LDMOS having an opening formed with a straight portion and a corner portion in the gate electrode, and a channel forming region and a source region formed by self-aligned diffusion from the opening of the gate electrode. In a semiconductor device having a structure, the breakdown voltage can be improved without increasing the on-resistance.

  As described in claim 2, in the semiconductor device according to claim 1, when the impurity concentration of the low concentration impurity diffusion region is one to two digits lower than that of the source region, the concentration profile is optimized. It is preferable from the viewpoint of aiming.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the impurity concentration of the channel formation region at the substrate surface in the PN junction formed by the channel formation region and the low concentration impurity diffusion region is It is preferable from the viewpoint of optimizing the concentration profile that the corner portion and the straight portion in the opening of the gate electrode are equal to each other or the corner portion is darker than the straight portion.

  The semiconductor device according to any one of claims 1 to 3, wherein a sidewall is formed in the opening of the gate electrode, and an outer peripheral end of the source region is positioned under the sidewall. The source region may not be provided under the gate electrode, and the low concentration impurity diffusion region may be provided under the gate electrode. In this case, the impurity concentration of the channel formation region at the substrate surface in the PN junction formed by the channel formation region and the low concentration impurity diffusion region is adjusted to a desired value by adjusting the width dimension of the sidewall. Therefore, the degree of freedom in designing the density profile can be improved.

  6. The semiconductor device according to claim 1, wherein the source region is dug from a main surface of the semiconductor substrate and has a planar structure in a direction from the source region to the drain region. A trench formed so as to penetrate a channel formation region between the gate electrode and the drain region, and the gate electrode is formed not only on the semiconductor substrate but also on the inner surface of the trench via a gate insulating film The present invention may be applied to a semiconductor device.

  According to a sixth aspect of the present invention, there is provided a semiconductor device including a planar gate electrode and a trench gate electrode, wherein the corner portion of the opening of the planar gate electrode and the trench are overlapped with or in contact with each other in a planar shape. The gist of the semiconductor device is as described above.

  According to the sixth aspect of the present invention, in the corner portion of the gate electrode opening portion, impurities cannot diffuse in the lateral direction in the self-aligned diffusion of the channel formation region, and the corner portion of the gate electrode opening portion The channel concentration (impurity concentration) increases. Therefore, conventionally, with respect to the channel concentration (impurity concentration), the corner portion of the gate electrode opening portion is lower than the straight portion, and in order to ensure the punch through breakdown voltage of the element, the channel formation region is set to be darker. For this reason, when the channel formation region of the linear portion of the gate electrode opening, which becomes the majority of the current path during device operation, is increased, the on-resistance increases, but in the present invention, the linear portion of the gate electrode is increased. In a semiconductor device having an LDMOS structure, in which a channel forming region and a source region are formed by self-aligned diffusion from the opening of the gate electrode, an opening having a corner is formed. The breakdown voltage can be improved without causing an increase.

  As described in claim 7, as a method of manufacturing a semiconductor device according to any one of claims 1 to 5, the rotation angle is changed in order to form the low-concentration impurity diffusion region of the first conductivity type. When an ion implantation process is performed in which a plurality of oblique ion implantations are performed and the amount of ion implantation into the corner portion is smaller than that of the straight portion at the opening of the gate electrode, the degree of freedom in designing the concentration profile can be improved.

  As described in claim 8, as a method for manufacturing a semiconductor device according to any one of claims 1 to 5, in the first step, a shallow channel formation region is formed from the opening of the gate electrode. After performing ion implantation, a sidewall is formed in the opening of the gate electrode, and ion implantation for forming a first conductivity type low concentration impurity diffusion region is performed from the opening of the gate electrode using the sidewall. In the second step, the shallow channel formation region and the first conductivity type low-concentration impurity diffusion region are diffused to the same depth by heat treatment, and in the third step, the sidewalls are used to form the gate electrode. Ion implantation for forming a deep channel formation region under the shallow channel formation region is performed from the opening. Thereby, by adjusting the width dimension of the sidewall, the impurity concentration of the channel formation region at the substrate surface in the PN junction formed by the channel formation region and the low concentration impurity diffusion region is adjusted to a desired value. Therefore, the degree of freedom in designing the density profile can be improved.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a semiconductor device according to this embodiment. This semiconductor device has an LDMOS structure and is an N-channel transistor.

  In the present semiconductor device (LDMOS transistor), as described with reference to FIG. 16, the cell has a mesh gate structure, and the source cell and the drain cell are alternately arranged vertically and horizontally as a planar structure on the substrate. .

  In FIG. 1, an N-type silicon substrate 1 is used as a first conductivity type semiconductor substrate. A polysilicon gate electrode 3 is formed on a silicon substrate 1 via a gate oxide film 2 as a gate insulating film. The gate electrode 3 is formed with a rectangular opening 3a, and the gate electrode 3 has an opening 3a in which a straight portion and a corner portion are formed.

  A P channel formation region (second conductivity type channel formation region) 4 is formed in the surface layer portion of the silicon substrate 1. The P channel formation region 4 is a well region, and the P channel formation region 4 is formed by self-aligned diffusion from the opening 3 a of the gate electrode 3.

An N ⁺ source region (first conductivity type source region) 5 is formed in the surface layer portion of the silicon substrate 1 inside the P channel formation region 4. That is, the N ⁺ source region 5 is formed shallower than the P channel forming region 4 in the surface layer portion of the N type silicon substrate 1 in the P channel forming region 4. The N ⁺ source region 5 is formed by self-aligned diffusion from the opening 3 a of the gate electrode 3.

A P ⁺ contact region 6 is adjacent to the N ⁺ source region 5 and shallower than the P channel formation region 4 in the surface layer portion of the N-type silicon substrate 1 in the P channel formation region 4. The P ⁺ contact region 6 is a diffusion layer for making ohmic contact with the channel forming region 4.

A source electrode 7 is disposed on the N-type silicon substrate 1, and the source electrode 7 is electrically connected to the N ⁺ source region 5 and the P ⁺ contact region 6.
A LOCOS oxide film 8 is formed on the upper surface of the N-type silicon substrate 1 between the source cell and the drain cell. A polysilicon gate electrode 3 is routed on the LOCOS oxide film 8 (a wiring portion of the gate electrode).

An N ⁺ drain region 9 is formed in the surface layer portion of the N-type silicon substrate 1 in the drain cell.
When the LDMOS transistor is turned on, an inversion layer is formed at a portion facing the gate electrode 3 in the P channel formation region 4, and a portion (inversion layer) facing the gate electrode 3 in the P channel formation region 4 from the N ⁺ source region 5. Then, a current flows through the N ⁺ drain region 9 via the N-type silicon substrate 1.

Here, in this embodiment, the low concentration impurity diffusion region 10 is formed in the surface layer portion of the silicon substrate 1 inside the channel formation region 4 and outside the source region 5. The low concentration impurity diffusion region 10 is formed by self-aligned diffusion from the opening 3 a of the gate electrode 3, is N-type (first conductivity type), and has an impurity concentration lower than that of the source region 5. That is, the low concentration impurity diffusion region (N ⁻ region) 10 is formed around the N ⁺ source region 5, shallower than the channel formation region 4 and deeper than the N ⁺ source region 5. Further, the impurity concentration of the low concentration impurity diffusion region 10 is 1 to 2 digits lower than the impurity concentration of the source region 5. Specifically, for example, the impurity concentration of the source region 5 is 3.9 × 10 ¹³ / cm ² , and the impurity concentration of the low-concentration impurity diffusion region 10 is 8 × 10 ¹² / cm ² .

In this way, by introducing the low concentration impurity diffusion region (N ⁻ region) 10 diffused deeper than the N ⁺ source region 5, the low concentration impurity diffusion region (N ⁻ region) 10 is also cornered by a two-dimensional effect. The concentration is lowered.

That is, the impurity profile of the low-concentration impurity diffusion region (N ⁻ region) 10 has a lower concentration in the corner portion of the gate electrode opening than in the straight portion. Further, regarding the lateral diffusion length L, in the channel formation region (P well region) 4, when the lateral diffusion length L 2 s in the straight portion and the lateral diffusion length L 2 c in the corner portion are compared, the lateral diffusion in the straight portion is compared. The lateral diffusion length L2c at the corner is shorter by ΔL2 than the length L2s. Similarly, in the low-concentration impurity diffusion region (N ⁻ region) 10, when the lateral diffusion length L 1 s in the straight portion and the lateral diffusion length L 1 c in the corner portion are compared, the lateral diffusion length L 1 s in the straight portion is obtained. In comparison, the lateral diffusion length L1c at the corner is shorter by ΔL1.

  2 and 3 show the substrate surface concentration with respect to the distance (lateral diffusion length L) from the edge of the gate electrode opening. That is, the horizontal axis represents the distance L (see FIG. 1) from the opening end of the gate electrode, and the vertical axis represents the substrate surface concentration. 2 and 3, both the impurity concentration at the corner and the impurity concentration at the straight line in the gate electrode opening are shown.

2 and 3, the channel formation region 4 on the substrate surface in the PN junction formed by the P channel formation region 4 and the low-concentration impurity diffusion region (N ⁻ region) 10 at the corner at the gate electrode opening. The impurity concentration (channel concentration) is indicated by “β ′”. 2 and 3, the impurity concentration of the channel formation region 4 at the substrate surface in the PN junction formed by the P channel formation region 4 and the N ⁺ source region 5 at the corner portion at the gate electrode opening ( Channel concentration) is indicated by “β”. Here, in this embodiment, a low concentration impurity diffusion region (N ⁻ region) 10 is formed, and the concentration of the low concentration impurity diffusion region 10 is low at the corner of the gate electrode opening 3a due to a two-dimensional effect. Therefore, the impurity concentration of the channel forming region 4 on the substrate surface at the PN junction can be changed to β ′ which is β in the present embodiment, which is β in the present embodiment.

2 and 3, the channel formation region 4 at the substrate surface in the PN junction formed by the P channel formation region 4 and the low concentration impurity diffusion region (N ⁻ region) 10 in the straight line portion at the gate electrode opening. The impurity concentration (channel concentration) is indicated by “α ′”. 2 and 3, the impurity concentration of the channel formation region 4 at the substrate surface in the PN junction formed by the P channel formation region 4 and the N ⁺ source region 5 in the straight line portion at the gate electrode opening ( Channel concentration) is indicated by “α”. Here, in this embodiment, a low concentration impurity diffusion region (N ⁻ region) 10 is formed, and the low concentration impurity diffusion region 10 has a high concentration because the two-dimensional effect does not work in the straight portion of the gate electrode opening 3a. Thus, in the present embodiment, the impurity concentration of the channel forming region 4 on the substrate surface at the PN junction can be reduced to α ′ that is thinner by Δα in the present embodiment.

As a result, as shown in FIG. 2, at the corner of the gate electrode opening, the substrate surface at the PN junction formed by the P channel formation region 4 and the low concentration impurity diffusion region (N ⁻ region) 10 A PN junction formed by the impurity concentration (channel concentration) β ′ of the channel forming region 4 and the P channel forming region 4 and the low concentration impurity diffusion region (N ⁻ region) 10 in the linear portion at the gate electrode opening. The impurity concentration (channel concentration) α ′ of the channel forming region 4 on the substrate surface in FIG.

Alternatively, as shown in FIG. 3, the channel at the substrate surface in the PN junction formed by the P channel formation region 4 and the low concentration impurity diffusion region (N ⁻ region) 10 in the straight line portion at the gate electrode opening. Compared with the impurity concentration (channel concentration) α ′ of the formation region 4, the PN junction formed by the P channel formation region 4 and the low concentration impurity diffusion region (N ⁻ region) 10 at the corner portion at the gate electrode opening. The impurity concentration (channel concentration) β ′ of the channel formation region 4 on the substrate surface in the portion can be increased by a predetermined amount Δ.

  In order to more easily satisfy this β ′ ≧ α ′, the ion concentration in the corner portion of the low concentration impurity diffusion region 10 is made smaller than that in the straight portion in the opening 3 a of the gate electrode 3.

In other words, in the low-concentration impurity diffusion region (N ⁻ region) 10, the concentration at the position where the threshold voltage Vt for punch-through on the substrate surface in the channel formation region 4 is determined is equal between the corner portion and the straight portion, or the corner The on-resistance can be lowered by making the portion darker than the straight portion and lowering the impurity concentration on the substrate surface of the channel forming region 4 in the straight portion to the concentration limit for punch-through.

Next, a manufacturing method is demonstrated using FIG.
First, as shown in FIG. 4A, an N-type silicon substrate 1 is prepared. Then, a LOCOS oxide film (or STI or the like) 8 is formed.

Further, as shown in FIG. 4B, a film for forming a gate electrode (polysilicon (or polysilicon and silicide)) is deposited on the silicon substrate 1 via the gate oxide film 2, and thereafter, is deposited on photolithography. The gate electrode 3 having the opening 3a in which the straight portion and the corner portion are formed is formed. Further, a channeling suppression film (SiO ₂ film or the like) (not shown) is formed on the gate electrode 3.

Then, as shown in FIG. 4C, ions are implanted from the opening 3a of the gate electrode 3 in order to form the P channel formation region 4. At this time, the ion implantation angle is set in the vertical direction (tilt angle at the time of ion implantation = 0 ° or 7 °, rotation angle = 0 °). This is for uniform injection. Subsequently, ions are implanted from the opening 3 a of the gate electrode 3 to form a low concentration impurity diffusion region (N ⁻ region) 10. At this time, an impurity of the same type as that for the source region is implanted so that the impurity concentration is at least 1 to 2 digits lower. In addition, a plurality of oblique ion implantations with a fixed tilt angle and a different rotation angle are performed on the gate electrode during ion implantation to reduce the amount of ion implantation into the corner portion compared to the straight portion (details will be described later). To do). Thereafter, diffusion is performed so that a desired diffusion depth is obtained by heat treatment. In this way, the P channel formation region 4 is formed in the surface layer portion of the silicon substrate 1 by self-aligned diffusion from the opening 3a of the gate electrode 3, and the self-alignment from the opening 3a of the gate electrode 3 is performed. N-type low-concentration impurity diffusion regions 10 are formed inside the channel formation region 4 in the surface layer portion of the silicon substrate 1 by the effective diffusion.

Subsequently, as shown in FIG. 4D, ion implantation is performed to form the source region 5 and the drain region 9, and then ion implantation is performed to form the P ⁺ contact region 6. Thereafter, heat treatment is performed so as to obtain a desired diffusion depth. In this manner, the source region 5 which is N-type and has a higher impurity concentration than the low-concentration impurity diffusion region 10 is formed in the surface layer portion of the silicon substrate 1 by self-aligned diffusion from the opening 3 a of the gate electrode 3. Is formed inside the low-concentration impurity diffusion region 10.

Further, as shown in FIG. 4E, after depositing an interlayer film (such as BPSG), a contact hole is formed by photolithography, and a source electrode 7 is formed in a subsequent wiring formation step.
In this way, the semiconductor device shown in FIG. 1 is obtained.

Next, a manufacturing method for comparison will be described with reference to FIG.
First, as shown in FIG. 21A, a LOCOS oxide film 8 (or STI or the like) is formed. Then, as shown in FIG. 21B, after depositing a gate electrode formation film (polysilicon (or polysilicon and silicide)), patterning is performed with photolithography to form the gate electrode 3 having the opening 3a. Thereafter, a channeling suppression film (SiO ₂ film or the like) is formed on the gate electrode 3.

  Then, as shown in FIG. 21C, ions are implanted to form the channel formation region 4. Ion implantation is set in the vertical direction (tilt angle = 0 ° or 7 °, rotation angle = 0 °). Thereafter, the channel formation region 4 is diffused so as to obtain a desired diffusion depth by heat treatment.

Subsequently, as shown in FIG. 21D, ion implantation is performed to form the source region 5 and the drain region 9, and then ion implantation is performed to form the P ⁺ contact region 6. Thereafter, heat treatment is performed so as to obtain a desired diffusion depth.

Further, as shown in FIG. 21E, after depositing an interlayer film (BPSG or the like), a contact hole is formed by photolithography, and a source electrode 7 is formed in a subsequent wiring formation process.
In contrast to the manufacturing process in the comparative example, in this embodiment, as shown in FIG. 4C, the low concentration impurity diffusion region (N ⁻ region) 10 is diffused in a self-aligned manner from the gate electrode opening 3a. Form with.

Next, a plurality of oblique ion implantations with different rotation angles when forming the low concentration impurity diffusion region (N ⁻ region) 10 will be described with reference to FIGS.
As shown in FIG. 5, the ion incident direction is defined by the tilt angle ψ and the rotation angle θ in the three-axis system coordinates of x, y, and z. Then, the tilt angle ψ is constant, and the rotation angle θ is ion-implanted every 90 ° by dividing one rotation (360 °) into four. That is, ions are implanted at a rotation angle of θ + 90 ° × n times (n = 0, 1, 2, 3).

  In the case of ion implantation in this way, when the height from the upper surface of the substrate to the upper surface of the gate electrode 3 is “T”, the linear portion of the gate electrode opening in FIG. 6 is as shown in the sectional view of FIG. In addition, ion implantation (first to fourth ion implantations) in four directions is performed.

First, in the first ion implantation, a predetermined tilt angle ψ, a predetermined rotation angle θ, and an angle formed with a normal to the substrate upper surface (z axis in FIG. 5) is tan ⁻¹ (sin ψ · sin θ). It becomes. Here, the rotation angle θ is an angle at which ion implantation is performed from the opened side (the right side in FIGS. 7 and 8) in the straight line portion of the gate electrode opening in the plan view of FIG.

In the second ion implantation, a predetermined tilt angle ψ and a predetermined rotation angle θ + 90 ° are obtained. In FIG. 7, the angle formed with the normal to the substrate upper surface (z axis in FIG. 5) is tan ⁻¹ (sin ψ · sin (θ + 90 °)). Here, θ + 90 ° is an angle when rotated 90 ° counterclockwise with respect to the angle θ in the above-described first ion implantation in FIG. 8, and the opening side in the straight portion at the gate electrode opening ( The angle at which ion implantation is performed from the right side of FIGS.

In the third ion implantation, a predetermined tilt angle ψ, a predetermined rotation angle θ + 180 °, and the angle formed with the normal to the substrate upper surface (z axis in FIG. 5) in FIG. 7 is tan ⁻¹ (sin ψ · sin (θ + 180 °)). Here, θ + 180 ° is an angle when rotated 90 ° counterclockwise with respect to the angle θ + 90 ° in the second ion implantation described above in FIG.

In the fourth ion implantation, a predetermined tilt angle ψ, a predetermined rotation angle θ + 270 °, and the angle formed with the normal to the substrate upper surface (z axis in FIG. 5) in FIG. 7 is tan ⁻¹ (sin ψ · sin (θ + 270 °)). Here, θ + 270 ° is an angle when rotated 90 ° counterclockwise with respect to the angle θ + 180 ° in the third ion implantation described above in FIG.

When ion implantation in the four directions (first to fourth ion implantation) is performed, as shown in FIGS. 7 and 8, the gate electrode opening is formed in the first and second ion implantations (θ, θ + 90 °). Ions are implanted in the immediate vicinity of the edge. In the third ion implantation (θ + 180 °), in a region away from the gate electrode opening end, specifically, in a region away from T · tan (tan ⁻¹ (sin ψ · sin (θ + 180 °))), Ions are implanted. In the fourth ion implantation (θ + 270 °), in a region away from the gate electrode opening end, specifically, in a region away from T · tan (tan ⁻¹ (sin ψ · sin (θ + 270 °))), Ions are implanted.

In this way, ions are implanted in the immediate vicinity of the gate electrode opening end by the first and second ion implantations (two of the four ion implantations). Further, the third ion implantation is performed at a distance of T · tan (tan ⁻¹ (sin ψ · sin θ + 180 °)) or more. Further, the fourth ion implantation is performed at a distance of T · tan (tan ⁻¹ (sin ψ · sin (θ + 270 °))) or more.

On the other hand, in the corner portion of the gate electrode opening in FIG.
In this case, as shown in the plan view of FIG. 10, ion implantation (first to fourth ion implantations) in four directions is performed.

  First, in the first ion implantation, a predetermined tilt angle ψ and a predetermined rotation angle θ are provided, and the rotation angle θ is an opening at a corner portion (a right-angle portion) in the gate electrode opening in FIG. This is an angle at which ion implantation is performed from the side (lower right side in FIG. 10).

  In the second ion implantation, a predetermined tilt angle ψ and a predetermined rotation angle θ + 90 ° are set, and θ + 90 ° is 90 counterclockwise with respect to the angle θ in the first ion implantation described above in the plan view of FIG. ° Angle when rotated.

  In the third ion implantation, a predetermined tilt angle ψ and a predetermined rotation angle θ + 180 ° are set, and θ + 180 ° is rotated 90 ° counterclockwise with respect to the angle θ + 90 ° in the second ion implantation described above in FIG. This is the angle when

  In the fourth ion implantation, a predetermined tilt angle ψ and a predetermined rotation angle θ + 270 ° are rotated, and θ + 270 ° rotates 90 ° counterclockwise with respect to the angle θ + 180 ° in the third ion implantation described above in FIG. This is the angle when

When ion implantation in these four directions (first to fourth ion implantations) is performed, as shown in FIG. 10, in the first ion implantation (θ), ions are located in the vicinity of the gate electrode opening end. Injected. In the second ion implantation (θ + 90 °), ions are implanted in the immediate vicinity of one surface of the corner of the gate electrode opening, but in the other region, specifically, T · Ions are implanted into a region separated by tan (tan ⁻¹ (sin ψ · sin (θ + 90 °))) or more. In the fourth ion implantation (θ + 270 °), ions are implanted in the immediate vicinity of the other surface of the corner at the gate electrode opening, but one surface is separated from the other surface, specifically, T · Ions are implanted into a region separated by tan (tan ⁻¹ (sinψ · sin (θ + 270 °)) or more. In the third ion implantation (θ + 180 °), specifically, T · tan (tan ⁻¹ (sinψ · sin (θ + 180) is formed in a region away from one surface and the other surface of the corner of the gate electrode opening. °))) Ions are implanted in the region farther away.

  In this way, ions are implanted by the first ion implantation in the immediate vicinity of the corner at the gate electrode opening (implanted once out of the four ion implantations). This is half of the straight line at the gate electrode opening.

  In this way, by performing a plurality of oblique ion implantations with different rotation angles, the amount of ion implantation into the corner portion is reduced by the projection effect of the gate electrode 3 as compared with the straight portion at the opening 3a of the gate electrode 3. Can do.

Note that the rotation angle may not be divided into four parts (360 °), but may be performed by a plurality of other oblique ion implantations such as six parts.
According to the above embodiment, the following effects can be obtained.

  (A) As a structure of the semiconductor device, as shown in FIG. 1, self-alignment from the opening 3 a of the gate electrode 3 in the surface layer portion of the silicon substrate 1 inside the channel formation region 4 and outside the source region 5. A low-concentration impurity diffusion region 10 that is N-type (first conductivity type) and has an impurity concentration lower than that of the source region 5 is provided. As a result, the concentration of the corner portion of the gate electrode opening 3a is lower than that of the straight portion at the time of self-aligned diffusion from the opening 3a of the gate electrode 3 with respect to the channel formation region 4, but the low concentration impurity diffusion region 10 Similarly, the corner portion of the gate electrode opening 3a has a lower concentration than the straight portion. Thereby, as shown in FIG. 2, the channel formation region 4 on the substrate surface in the PN junction formed by the channel formation region 4 and the low concentration impurity diffusion region 10 in the corner portion of the opening 3 a of the gate electrode 3. Can be made higher by Δβ than the impurity concentration β of the channel forming region 4 at the substrate surface at the PN junction formed by the channel forming region 4 and the source region 5, and punch through The breakdown voltage can be improved.

  Therefore, unlike the prior art, it is not necessary to set the channel formation region 4 to be darker in order to ensure the withstand voltage of the device (the channel formation region 4 in the straight portion of the gate electrode opening which becomes the most current path during device operation). An increase in on-resistance can be avoided (without increasing the density).

  In this way, the gate electrode 3 has the opening 3a in which the straight portion and the corner portion are formed, and the channel forming region 4 and the source region 5 are formed by self-aligned diffusion from the opening 3a of the gate electrode 3. In a semiconductor device having an LDMOS structure in which is formed, the breakdown voltage can be improved without causing an increase in on-resistance.

  (B) In particular, it is preferable that the impurity concentration of the low-concentration impurity diffusion region 10 is 1 to 2 digits lower than that of the source region 5 from the viewpoint of optimizing the concentration profile.

  (C) The impurity concentration of the channel formation region 4 at the substrate surface in the PN junction formed by the channel formation region 4 and the low concentration impurity diffusion region 10 is, as shown in FIG. It is preferable from the viewpoint of optimizing the density profile that the corner portion and the straight portion in FIG. 3 are equal, or as shown in FIG. 3, the corner portion is darker than the straight portion. Specifically, the threshold voltage Vt for punch-through can be equal in the straight line portion and the corner portion in the gate electrode opening 3a or higher in the corner portion, thereby forming the channel in the straight portion up to the concentration limit for punch-through. The on-resistance can be lowered by lowering the impurity concentration on the substrate surface in the region 4.

(D) As a method for manufacturing a semiconductor device, a plurality of oblique ion implantations with different rotation angles are performed (due to the projection effect of the gate electrode 3) to form the low-concentration impurity diffusion region 10. By including an ion implantation step in which the amount of ion implantation into the corner portion is smaller than that in the straight portion in 3a, the degree of freedom in designing the concentration profile can be improved.
(Second Embodiment)
Next, the second embodiment will be described focusing on the differences from the first embodiment.

A method for manufacturing a semiconductor device according to this embodiment instead of FIG. 4 will be described with reference to FIGS.
In the present embodiment, as shown in FIG. 12C, the sidewall 20 is formed in the opening 3 a of the gate electrode 3, and the outer peripheral edge of the source region 5 is located under the sidewall 20, so that the gate electrode 3 There is no source region 5 below, and a low-concentration impurity diffusion region 10 is provided below the gate electrode 3. In this case, by adjusting the width dimension of the sidewall 20, the impurity concentration of the channel formation region 4 at the substrate surface in the PN junction formed by the channel formation region 4 and the low concentration impurity diffusion region 10 is set to a desired value. Therefore, the degree of freedom in designing the density profile can be improved.

As a manufacturing process, first, as shown in FIG. 11A, a LOCOS oxide film 8 (or STI) is formed.
Then, as shown in FIG. 11B, after depositing polysilicon (or polysilicon and silicide) as a gate electrode forming film on the N-type silicon substrate 1 via the gate oxide film 2, a pattern is formed by photolithography. The gate electrode 3 having the opening 3a in which the straight portion and the corner portion are formed is formed. Thereafter, a channeling suppression film (SiO ₂ film or the like) is formed on the gate electrode 3.

Further, as shown in FIG. 11C, ion implantation for forming a shallow channel formation region (indicated by reference numeral 4a in FIG. 12A) is performed from the opening 3a of the gate electrode 3 to form a P-well implant. Form a layer. At this time, ion implantation from the vertical direction (tilt angle at the time of ion implantation = 0 ° or 7 °, rotation angle = 0 °) is set. This is for uniform injection. Thereafter, as shown in FIG. 11D, a sidewall 20 is formed in the opening of the gate electrode 3. In order to form an N-type low-concentration impurity diffusion region 10 from the opening 3a of the gate electrode 3 using this sidewall 20, it is the same type as the source region, and the impurity concentration is low by one to two digits. In order to form a concentration impurity diffusion layer, ion implantation from the vertical direction (tilt angle = 0 ° or 7 °, rotation angle = 0 °) is performed. Thereby, an N ^- implant layer is formed (first step).

Then, as shown in FIG. 12A, the shallow channel formation region 4a and the N-type low-concentration impurity diffusion region 10 are diffused by heat treatment until they have the same depth (second step).
Further, the ion implantation for forming the deep channel formation region 4b under the shallow channel formation region 4a from the opening 3a of the gate electrode 3 using the sidewall 20 is aimed at the vicinity below the channel formation region 4a. To do. Thereby, an additional P implantation layer is formed (third step).

Subsequently, as shown in FIG. 12B, ion implantation is performed to form the source region 5 and the drain region 9, and then ion implantation is performed to form the P ⁺ contact region 6. Thereafter, heat treatment is performed so as to obtain a desired diffusion depth, and as shown in FIG. 12C, a low concentration impurity is formed inside the channel formation region 4 composed of the shallow channel formation region 4a and the deep channel formation region 4b. The diffusion region 10 is located.

Then, after depositing an interlayer film (such as BPSG), a contact hole is formed by photolithography, and a source electrode 7 is formed in a subsequent wiring formation step.
Through such a process, the width dimension of the sidewall 20 is adjusted, so that the channel formation region 4 on the substrate surface in the PN junction formed by the channel formation region 4 and the low-concentration impurity diffusion region 10 The impurity concentration can be adjusted to a desired value, and the degree of freedom in designing the concentration profile can be improved. That is, the threshold voltage Vt for punch-through can be adjusted to a desired value by adjusting the width dimension of the sidewall 20 and adjusting the position of the outer peripheral edge of the low-concentration impurity diffusion region 10.
(Third embodiment)
Next, the third embodiment will be described focusing on the differences from the first and second embodiments.

FIG. 13 shows a semiconductor device according to this embodiment.
In the present embodiment, as compared with the semiconductor device of the first embodiment, a trench 59 is further provided, and the gate electrode 49 includes a planar gate electrode 52 formed on the silicon substrate 50 via a gate oxide film 51, and A trench gate electrode 61 is formed on the inner surface of the trench 59 through a gate oxide film 60. That is, the gate electrode 49 is formed not only on the silicon substrate 50 but also on the inner surface of the trench 59 via the gate oxide film 60.

This will be described in detail below.
A planar gate electrode 52 is formed on a main surface 50a of an N-type silicon substrate 50 as a first conductivity type semiconductor substrate through a gate oxide film 51 as a gate insulating film. The planar gate electrode 52 has an opening 52a in which a straight portion and a corner portion are formed.

  A P-type (second conductivity type) channel formation region 53 is formed in the surface layer portion of the silicon substrate 50. The channel forming region 53 is formed by self-aligned diffusion from the opening 52 a of the planar gate electrode 52.

An N-type (first conductivity type) source region 54 is formed in the surface layer portion of the silicon substrate 50 inside the channel formation region 53. The source region 54 is formed by self-aligned diffusion from the opening 52 a of the planar gate electrode 52. A P ⁺ contact region 55 is formed in the surface layer portion of the silicon substrate 50 inside the channel formation region 53.

  A source electrode 56 is disposed on the upper surface of the silicon substrate 50 in the opening 52 a of the planar gate electrode 52. The source electrode 56 is electrically connected to the source region 54 and the contact region 55.

On the main surface 50 a of the silicon substrate 50, an N ⁺ drain region 58 is formed in the surface layer portion at a position separated from the channel formation region 53. A LOCOS oxide film 57 is formed between the channel formation region 53 and the N ⁺ drain region 58.

  A trench 59 is dug from the main surface 50 a of the silicon substrate 50. The trench 59 has a rectangular shape as a planar shape, and is formed so as to penetrate the channel formation region 53 between the source region 54 and the drain region 58 in the direction from the source region 54 to the drain region 58 as a planar structure. Yes. A trench gate electrode 61 is formed on the inner surface of the trench 59 through a gate oxide film 60 as a gate insulating film.

  In the present embodiment, the low-concentration impurity diffusion region 10 is formed in the surface layer portion of the silicon substrate 50 inside the channel formation region 53 and outside the source region 54. The low-concentration impurity diffusion region 10 is formed by self-aligned diffusion from the opening 52 a of the planar gate electrode 52 and is N-type (first conductivity type) and has an impurity concentration lower than that of the source region 54.

When the LDMOS transistor is turned on, an inversion layer is formed at a portion facing the planar gate electrode 52 and a portion facing the trench gate electrode 61 in the P channel formation region 53. Then, from the N ⁺ source region 54 (low-concentration impurity diffusion region 10), as indicated by current (I) in the drawing, through a portion (inversion layer) facing the planar gate electrode 52 in the P channel formation region 53, N A current flows to the N ⁺ drain region 58 through the type silicon substrate 50. Further, from the N ⁺ source region 54 (low-concentration impurity diffusion region 10), as indicated by current (II) in the drawing, through a portion (inversion layer) facing the trench gate electrode 61 in the P channel formation region 53, N A current flows to the N ⁺ drain region 58 through the type silicon substrate 50. At this time, the current path is formed up to a deep part away from the surface, so that the on-resistance can be reduced. In this way, in an LDMOS transistor using both a planar gate and a trench gate, the on-resistance is reduced by flowing a current deeper and improving the channel density than an LDMOS transistor having only a planar gate. be able to.

Also in this LDMOS transistor, by providing the low-concentration impurity diffusion region (N ⁻ region) 10, the breakdown voltage can be improved without increasing the on-resistance.
(Fourth embodiment)
Next, the fourth embodiment will be described focusing on the differences from the third embodiment.

FIG. 14 shows a semiconductor device according to this embodiment.
The structure of the transistor is the same as that described with reference to FIG. 13, and detailed description thereof is omitted by attaching the same reference numerals. However, in this embodiment, the low-concentration impurity diffusion region (N ⁻ region) 10 is not formed, but instead has the following structure.

  In the present embodiment, as the relationship between the opening 52a of the planar gate electrode 52 and the trench 59, the corner of the opening 52a of the planar gate electrode 52 and the trench 59 overlap in a planar shape.

  Then, by overlapping the corner portion of the gate electrode opening 52a with the trench 59, when impurities forming the channel forming region 53 are diffused, the impurity strikes the trench gate electrode 61, thereby reducing the two-dimensional effect of diffusion. Concentration can be suppressed.

  That is, in the semiconductor device shown in FIG. 22 as a comparative example, when the impurity forming the channel formation region 53 diffuses, the corner portion has a lower concentration than the straight portion of the gate electrode opening 52a due to the two-dimensional effect of diffusion. It will become. In FIG. 22, the opening 52a of the gate electrode is rectangular and the corner is 90 °. However, in this embodiment of FIG. 14, the opening 52a of the gate electrode is not rectangular but wide at both ends on the long side. The corner portion and the trench 59 are overlapped with each other (the corner has an acute angle smaller than 90 °). Thereby, the malfunction by the density reduction by the two-dimensional effect in a corner part can be avoided.

Thus, in the present embodiment, in the corner portion of the gate electrode opening 52a, impurities cannot be diffused in the lateral direction in the self-aligned diffusion, and the channel concentration (impurity) in the corner portion of the gate electrode opening 52a can be prevented. Density) increases, and the threshold voltage Vt for punch-through can be kept high only at the corners. Therefore, the channel concentration (impurity concentration) that affects the on-resistance can be lowered as a whole, and as a result, the on-resistance can be reduced. Further, it is possible to suppress a decrease in the threshold voltage Vt at the corner without adding a dedicated N ⁻ layer.

According to the above embodiment, the following effects can be obtained.
In the semiconductor device including the planar gate electrode 52 and the trench gate electrode 61, the corner portion of the opening 52a of the planar gate electrode 52 and the trench 59 are overlapped with each other in the planar shape. At the corner portion, the impurity cannot be diffused in the lateral direction in the self-aligned diffusion of the channel forming region 53, and the channel concentration (impurity concentration) at the corner portion of the gate electrode opening 52a is increased. Therefore, conventionally, with respect to the channel concentration (impurity concentration), the corner portion of the gate electrode opening portion is lower than the straight portion, and in order to ensure the punch through breakdown voltage of the element, the channel formation region is set to be darker. For this reason, when the channel formation region in the linear portion of the gate electrode opening, which becomes the majority of the current path during device operation, is increased, the on-resistance increases, but in this embodiment, a straight line is formed in the gate electrode. On-resistance in a semiconductor device having an LDMOS structure, which has an opening having a corner portion and a corner portion, and in which a channel formation region and a source region are formed by self-aligned diffusion from the opening portion of the gate electrode The breakdown voltage can be improved without incurring an increase in.

  In FIG. 14, the planar shape of the trench 59 is rectangular. However, as shown in FIG. 15, the planar shape of the trench 59 is not a rectangular shape but a shape in which both ends on the long sides are widened. The corner portion of the opening 52 a of the planar gate electrode 52 may be in contact with the trench 59.

In the above description, the N-channel LDMOS is used. However, the present invention may be applied to a P-channel LDMOS. That is, in the above description, the first conductivity type is N type and the second conductivity type is P type. However, the first conductivity type is P type and the second conductivity type is N type. Also good. Specifically, the source region is N ⁺ in the case of N-channel LDMOS, but is P ⁺ in the case of P-channel LDMOS, and the channel formation region is P-type in the case of N-channel LDMOS. However, in the case of P-channel LDMOS, it is N-type, and the low-concentration impurity diffusion region 10 is N ⁻ in the case of N-channel LDMOS, but is P ⁻ in the case of P-channel LDMOS.

2A and 2B are a plan view and a cross-sectional structure of the semiconductor device according to the first embodiment. The figure which shows the substrate surface density | concentration about the distance L from the edge of a gate-electrode opening part. The figure which shows the substrate surface density | concentration about the distance L from the edge of a gate-electrode opening part. (A)-(e) is sectional drawing for demonstrating the manufacturing process of the semiconductor device in 1st Embodiment. The figure for demonstrating an ion incident direction. The perspective view which shows the linear part in a gate electrode opening part. Sectional drawing which shows the ion implantation state in the linear part in a gate electrode opening part. The top view which shows the ion implantation state in the linear part in a gate electrode opening part. The perspective view which shows the corner part in a gate electrode opening part. The top view which shows the ion implantation state in the corner part in a gate electrode opening part. (A)-(d) is sectional drawing for demonstrating the manufacturing process of the semiconductor device in 2nd Embodiment. (A)-(c) is sectional drawing for demonstrating the manufacturing process of the semiconductor device in 2nd Embodiment. The figure which shows the plane and sectional structure of the semiconductor device in 3rd Embodiment. The figure which shows the plane and sectional structure of the semiconductor device in 4th Embodiment. 2A and 2B illustrate a plan view and a cross-sectional structure of a semiconductor device. The top view of the semiconductor device for demonstrating background art. XX sectional drawing of FIG. 16 for demonstrating background art. 2A and 2B illustrate a plan view and a cross-sectional structure of a semiconductor device. The figure which shows the substrate surface density | concentration about the distance L from the edge of a gate-electrode opening part. The figure which shows the measurement result of the relationship between a threshold voltage and on-resistance. (A)-(e) is sectional drawing for demonstrating the manufacturing process of the semiconductor device for a comparison. The figure which shows the plane and sectional structure of the semiconductor device for a comparison.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... N-type silicon substrate, 2 ... Gate oxide film, 3 ... Gate electrode, 3a ... Opening part, 4 ... P channel formation area, 5 ... N ⁺ source region, 10 ... Low concentration impurity diffusion region, 20 ... Side wall, DESCRIPTION OF SYMBOLS 49 ... Gate electrode, 50 ... N-type silicon substrate, 50a ... Main surface, 51 ... Gate oxide film, 52 ... Planar gate electrode, 52a ... Opening, 53 ... Channel formation region, 54 ... N ⁺ source region, 59 ... Trench 60 ... gate oxide film, 61 ... trench gate electrode.

Claims (8)

A semiconductor device having an LDMOS structure,
A gate electrode (3) formed on a semiconductor substrate (1) of the first conductivity type via a gate insulating film (2) and having an opening (3a) in which a linear portion and a corner portion are formed;
A second conductivity type channel formation region (4) formed by self-aligned diffusion from the opening (3a) of the gate electrode (3) in the surface layer portion of the semiconductor substrate (1);
First conductivity type formed by self-aligned diffusion from the opening (3a) of the gate electrode (3) in the surface layer portion of the semiconductor substrate (1) inside the channel formation region (4). Source region (5) of
Self-aligned from the opening (3a) of the gate electrode (3) in the surface layer portion of the semiconductor substrate (1) inside the channel formation region (4) and outside the source region (5) A low-concentration impurity diffusion region (10) formed by diffusion, having a first conductivity type, and having an impurity concentration lower than that of the source region (5);
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the low-concentration impurity diffusion region has an impurity concentration that is one to two digits lower than that of the source region. The impurity concentration of the channel formation region (4) at the substrate surface in the PN junction formed by the channel formation region (4) and the low concentration impurity diffusion region (10) is determined by the opening (3a) of the gate electrode (3). 3. The semiconductor device according to claim 1, wherein the corner portion and the straight portion are the same, or the corner portion is darker than the straight portion. A side wall (20) is formed in the opening (3a) of the gate electrode (3), and an outer peripheral end of the source region (5) is located under the side wall (20) and below the gate electrode (3). The semiconductor device according to claim 1, wherein there is no source region (5) and the low-concentration impurity diffusion region (10) is present under the gate electrode (3). A channel between the source region (54) and the drain region (58) in the direction from the source region (54) to the drain region (58) as a planar structure is dug from the main surface (50a) of the semiconductor substrate (50). A trench (59) formed so as to penetrate the formation region (53);
The gate electrode (49) is formed not only on the semiconductor substrate (50) but also on the inner surface of the trench (59) via a gate insulating film (60). The semiconductor device of any one of -4. A planar gate electrode (52a) formed on the main surface (50a) of the first conductivity type semiconductor substrate (50) via the gate insulating film (51) and having straight and corner portions (52a). 52),
A second conductivity type channel formation region (53) formed by self-aligned diffusion from the opening (52a) of the planar gate electrode (52) in the surface layer portion of the semiconductor substrate (50);
First conductivity formed by self-aligned diffusion from the opening (52a) of the planar gate electrode (52) in the surface layer portion of the semiconductor substrate (50) inside the channel formation region (53). A source region (54) of the mold;
It is dug from the main surface (50a) of the semiconductor substrate (50) and has a planar structure between the source region (54) and the drain region (58) in the direction from the source region (54) to the drain region (58). A trench (59) formed to penetrate the channel formation region (53);
A trench gate electrode (61) formed on the inner surface of the trench (59) via a gate insulating film (60);
A semiconductor device having an LDMOS structure,
A semiconductor device characterized in that, in a planar shape, a corner portion of an opening (52a) of a planar gate electrode (52) overlaps or is in contact with the trench (59). A method of manufacturing a semiconductor device according to any one of claims 1 to 5,
Compared with the straight line portion at the opening (3a) of the gate electrode (3) by performing a plurality of oblique ion implantations with different rotation angles in order to form the low-concentration impurity diffusion region (10) of the first conductivity type. A method of manufacturing a semiconductor device, comprising an ion implantation step in which an ion implantation amount into a corner portion is small. A method of manufacturing a semiconductor device according to any one of claims 1 to 5,
After performing ion implantation for forming a shallow channel formation region (4a) from the opening (3a) of the gate electrode (3), a sidewall (20) is formed in the opening (3a) of the gate electrode (3). The first step of performing ion implantation for forming the first conductivity type low-concentration impurity diffusion region (10) from the opening (3a) of the gate electrode (3) using the sidewall (20). When,
A second step of diffusing until the shallow channel formation region (4a) and the first conductivity type low-concentration impurity diffusion region (10) have the same depth by heat treatment;
Ion implantation for forming a deep channel formation region (4b) under the shallow channel formation region (4a) is performed from the opening (3a) of the gate electrode (3) using the sidewall (20). A third step;
A method for manufacturing a semiconductor device, comprising:

Images