JP2007123646A - Structure of multilayer printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the generation of a void at the time of lamination in a multilayer printed wiring board. <P>SOLUTION: In the structure of a multilayer printed wiring board; a conductive wiring layer 3 that becomes an inner layer is formed, an area which is in the same layer as the conductive wiring layer 3 and in which conductive wiring is not formed at least is filled with a resin 5, the resin 5 is polished, and then an adhesive resin layer is laminated on a polished surface. In such a structure of the multilayer printed wiring board, a dummy conductive layer 4 is formed in the area which is in the same layer as the conductive wiring layer 3 and in which conductive wiring is not formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a laminated printed wiring board having a wiring circuit layer as an inner layer.

Conventionally, a printed wiring board with a laminated structure called a multilayer printed wiring board is made by alternately laminating a conductor circuit made of copper or the like and an interlayer insulating resin layer on a resin substrate reinforced with a glass cloth or the like called a core. It is made with.

For example, FIG. 5 shows a conventional process for manufacturing a typical multilayer printed wiring board. First, FIG. 5 (a)
Reference numeral 51 denotes the core described above, and conductive wiring layers 52 and 53 formed by a subtractive method or the like are provided on both main surfaces thereof. This is the core substrate 54. Also, copper foils 55 and 56 with resin are arranged above and below. These copper foils with resin are obtained by laminating adhesive resin layers 59 and 60 on copper foils 57 and 58, and are laminated by heating and pressing as shown in FIG.

Next, as shown in FIG. 5C, a recess 61 is formed by laser processing or the like over the pad for interlayer connection among the conductive wiring layers 52 and 53 formed on the core substrate 54. These recesses are formed so that the conductive wiring layers 52 and 53 are sufficiently exposed, and the residue remaining on the surface is removed with chemicals or the like.

Next, as shown in FIG. 5D, the outermost copper foils 57 and 58, the side surfaces of the recess 61, the conductive wiring layer 5
Panel plating with copper is performed so as to cover all the exposed surfaces of Nos. 2 and 53. Thereafter, FIG. 5 (e)
As shown in FIG. 5, by processing the conductive layers on both outer surfaces into a desired wiring shape by etching or the like, the outer wiring 63 is formed in addition to the conductive wiring layers 52 and 53 serving as the inner wiring, and the interlayer connection portion 64 is further formed Is done.

In recent years, an interlayer connection structure as shown in FIG. 6 has also been known (Patent Document 1). In this structure, as shown in FIG. 6 (a), copper foils with resin are arranged above and below the core substrate 54. In addition to the stacked layers 69 and 70, a conductive paste 71 is formed in a columnar shape corresponding to the position of the interlayer connection pad formed on the core substrate 54.

Thereafter, as shown in FIG. 6B, the core substrate 54 and the resin-coated copper foils 65 and 66 are laminated under heat and pressure, and panel plating is performed on both outer surfaces. Further, as shown in FIG. 6C, by processing the conductive layers on both outer surfaces into a desired wiring shape by etching or the like, the outer wiring 72 is formed in addition to the conductive wiring layers 52 and 53 to be the inner wiring, and further cured. An interlayer connection portion 73 made of the conductive paste is formed.

As described above, two typical examples of the laminated structure of the printed wiring board and the interlayer connection structure are given.
In recent years, there has been a strict requirement for the thickness limit of the printed wiring board required by the market for mobile terminals or the like, or a strict requirement for the thickness per layer from the high multilayer board market. It has become necessary to make it as thin as possible.

The following problems were caused by making the adhesive resin layer thinner from such a situation. This is shown in FIG. 7A and 7B show two examples of the above-described typical laminated structure. FIG. 7A shows an interlayer connection by plating a recess, and FIG. 7B shows a cross-sectional state of the interlayer connection by a conductive paste. .

Here, both adhesive resin layers 59, 60, 69, 70 are thinned to the limit,
This leads to an increase in the ratio of the thickness of the conductive wiring layers 52 and 53 to the thickness of the adhesive resin layer. Therefore, even when the adhesive resin layer has some fluidity when laminated under heating and pressurization, if the adhesive resin layer is thin, there will be a difference in pressure between the region with and without the conductive wiring layer. For this reason, voids are likely to occur in the regions indicated by a in FIG. 7A and b in FIG. 7B, and in an extreme example, delamination may occur in the subsequent heating step.

As one of measures against this problem, there is a known technique for filling unevenness caused by the conductive wiring layer with an insulating resin. In this method, the core substrate 5 on which the conductive wiring layers 52 and 53 are formed as shown in FIG.
A resin layer is formed on the main surface 4 by screen printing or the like, and the surface of the resin layer (coat resin) formed as shown in FIG. 8B is polished and smoothed. Hereinafter, this method is referred to as undercoat processing.

Japanese Patent Laying-Open No. 2005-209993 (FIG. 2)

If this undercoat process is performed, as shown in FIG. 9A, the pressure applied to the adhesive resin layer at the time of lamination can be made substantially uniform over the entire area of the substrate. In addition, in this example, the interlayer connection method in which the above-mentioned recess is plated, so that the undercoat polishing also leaves the coat resin on the upper part of the conductive wiring layer (indicated by symbol C), and the adhesive resin layer with the laser. The coating resin is removed all at once.
What is necessary is just to form a recess like (b).

On the other hand, when the interlayer connection method using the conductive paste described above is adopted, as shown in FIG. 10A, polishing is necessary until the surface of the conductive wiring layer is exposed when the coating resin is polished by undercoat processing. There is. In this case, the polishing is generally continued until the surface of the conductive wiring layer is removed by several μm. In this way, as shown in FIG. 10B, the pressure applied to the adhesive resin layer at the time of lamination can be made substantially uniform over the entire area of the substrate.

However, the coating resin in the undercoat process is easier to cut than the conductive wiring layer made of metal, and even when trying to process it flatly with a polishing machine, the conductive wiring layer has a wider range compared to the dense area of the conductive wiring layer. There is a tendency that the amount of polishing in a region without a layer or a sparse region increases.

As a result, the thickness of a region where there is no conductive wiring layer or a sparse region is thinned, and voids are likely to be generated in the portion indicated by reference character O in FIG. Here, the portion of the interlayer connection structure (FIG. 11 (a)) for plating the recess and the interlayer connection structure (FIG.
b)), the upper surface of the conductive wiring layer is several μm at the time of undercoat processing.
This problem appears remarkably in the form of FIG.

As a first aspect of the present invention, a conductive wiring layer serving as an inner layer is formed, a resin is filled in a region where at least conductive wiring is not formed in the same layer as the conductive wiring layer, and the polishing surface is formed after the resin is polished. A structure of a multilayer printed wiring board in which an adhesive resin layer is laminated, wherein a dummy conductive layer is formed in a region of the same layer as the conductive wiring layer where no conductive wiring is formed. A multilayer printed wiring board structure is provided.

According to a second aspect of the present invention, there is provided a multilayer printed wiring board structure according to the first aspect, wherein the dummy conductive layer is made of the same material as the conductive wiring layer.

Further, according to a third aspect of the present invention, the dummy conductive layer is formed in an arbitrary pattern shape, and in the region where the dummy conductive layer is formed, a conductive layer formation area and a conductive layer non-conductive region guided by the pattern shape are formed. The multilayer printed wiring according to the second aspect, wherein the ratio of the formation area is approximately approximate to the ratio of the conductive wiring formation area and the conductive wiring non-formation area in the region where the conductive wiring is formed Provides board structure.

According to the first aspect of the present invention, the amount of polishing at the time of undercoat processing is uniform throughout the printed wiring board, and the plate thickness after polishing is uniform. Therefore, even when this polished surface is laminated with the adhesive resin layer, generation of voids can be prevented.

Further, according to the second aspect of the present invention, the ease of polishing of the conductive wiring layer and the dummy conductive layer becomes equal per unit area, and it becomes easier to make the plate thickness after polishing more uniform.

Furthermore, according to the third aspect of the present invention, it becomes easier to equalize the region where the conductive wiring is provided and the region where the dummy conductive layer is provided, and the thickness after polishing can be made more uniform. It becomes easy.

Next, an embodiment of the structure of a multilayer printed wiring board according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a multilayer printed wiring board showing an embodiment according to the first aspect of the present invention.
Here, a multi-sided board in which a plurality of printed wiring boards, which are products, are combined on a single board for the purpose of rationalizing the production process is taken as an example.

In FIG. 1, reference numeral 1 denotes a base that is a unit in the production process, and is a combination of four multilayer printed wiring boards 2 that are products. These four sheets may be divided after the production process as a printed wiring board is completed, but it is often divided after the components are mounted as they are and the state is almost functionally close to completion. . In the division, a groove (not shown) or a slit (not shown) having a V-shaped cross section is provided at a cutting position on the surface of the substrate, or various known methods are adopted depending on the convenience of the substrate itself or equipment. .

Further, FIG. 1 shows the state of the surface of the core substrate after the conductive wiring layer 3 is formed and before lamination. Here, the conductive wiring layer 3 is a conductive wiring necessary for the function of a printed wiring board as a product, and a pad 3A for interlayer connection to other layers and a wiring that performs a two-dimensional connection function in this layer. It consists of pattern 3B. In other words, the conductive layer is an area necessary for product function.

On the other hand, a dummy conductive layer 4 which is not necessary for the product function is disposed in the other region. This situation is shown in a sectional view in FIG. Here, FIG. 2A shows a state before the undercoat process is performed, the conductive wiring layer 3 necessary for the product function on the left side of the paper and the dummy conductive layer 4 on the right side of the paper. In this example, the dummy conductive wiring image has a solid pattern shape.

FIG. 2B shows a state in which the coating resin 5 for undercoat processing is applied,
FIG. 2 (c) shows a state after polishing to remove and smooth the excess portion of the coating resin 5. FIG. Here, as shown in FIG. 2C, the upper surface of the interlayer connection pad 3A of the conductive wiring layer 3 must be surely exposed from the coating resin 5, so that the polishing progresses and the polishing tool is connected to the conductive wiring layer 3. Alternatively, the polishing is continued even after contacting the upper surface of the dummy conductive layer 4, and the polishing is further advanced by several μm.

At this time, if the dummy conductive layer 4 is not provided, the plate thickness on the right side of the sheet of the resin alone, which is easily polished, may be thinner than in a region where the conductive wiring layer 3 is present. Therefore, the dummy conductive layer 4
It is possible to make the plate thickness uniform over the entire area of the substrate, but it is wasteful to form the solid pattern on the entire substrate because it is necessary to perform the polishing of several μm over the entire pattern. It is recommended to appropriately adjust the area of the.

Next, an embodiment according to the second aspect of the present invention will be described. The dummy conductive layer 4 shown in FIG. 1 is formed simultaneously with the pattern formation of the conductive wiring layer 3. That is, when the unnecessary portion of the copper foil layer formed on the surface of the substrate 1 is removed by etching or the like, the solid pattern is left by masking or the like.

As a result, a dummy conductive layer 4 made of the same material as that of the conductive wiring layer 3 can be formed, and the resistance per unit area against polishing becomes equal. Therefore, it becomes easy to make the resistance to polishing of the entire substrate uniform by adjusting the area of the solid pattern described above. Further, it is not necessary to increase the number of steps for forming the dummy conductive layer 4.

Further, an embodiment according to the third aspect of the present invention will be described. FIG. 3 is a plan view of a core substrate substantially similar to the substrate 1 shown in FIG. 1, but the dummy conductive layer 4 indicated by reference numeral 4 in FIG. The conductive layer 7 is formed in a mesh pattern shape. Other identical components are denoted by the same reference numerals.

Here, by forming the dummy conductive layer 7 in a mesh shape, the dummy conductive layer can be disposed over a wide region without unnecessarily widening the polishing area of several μm. The pattern shape may be any shape such as a stripe, lattice, or dot, but a geometric pattern is easier to form. Also, a pattern shape that is extremely directional on a flat surface, such as the stripe, may affect the polishing result depending on the polishing method, and should be avoided.

4 shows the cross-sectional shape of the substrate shown in FIG. 3. If the resistance to the polishing of the entire substrate is made as uniform as possible, the conductive wiring formation area and the conductive wiring in the region where the conductive wiring layer 3 is present are shown. It is desirable that the ratio of the conductive layer formation area and the conductive layer non-formation area in the region where the dummy conductive layer 4 is present is approximately approximate to the ratio of the non-formation area.

This ratio can be derived by calculating electronically using CAD data, but if the wiring density in the region of the conductive wiring layer is sufficiently high, it is applied in the wiring design of the substrate. The pattern shape of the dummy conductive layer 7 can be easily designed by using the L / S (line / space) ratio of the wiring rule. Therefore, in this case, the uniformity of the plate thickness after the undercoat process can be obtained more easily.

The top view which shows embodiment of this invention Sectional drawing which shows the principal part which shows embodiment of this invention The top view which shows other embodiment of this invention Sectional drawing which shows the principal part which shows other embodiment of this invention. Sectional view showing conventional technology Sectional view showing conventional technology Sectional view showing conventional technology Sectional view showing conventional technology Sectional view showing conventional technology Sectional view showing conventional technology Sectional view showing conventional technology

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 6 Board | substrate 2 Printed wiring board 3 Conductive wiring layer 3A Interlayer connection pad 3B Wiring pattern 4, 7 Dummy conductive layer 5 Coat resin

Claims (3)

A multilayer in which a conductive wiring layer to be an inner layer is formed, a resin is filled in at least a region where the conductive wiring is not formed in the same layer as this conductive wiring layer, and an adhesive resin layer is laminated on the polished surface after the resin is polished A printed wiring board structure,
A structure of a multilayer printed wiring board, wherein a dummy conductive layer is formed in a region of the same layer as the conductive wiring layer where no conductive wiring is formed. The multilayer printed wiring board structure according to claim 1, wherein the dummy conductive layer is made of the same material as the conductive wiring layer. The dummy conductive layer is formed in an arbitrary pattern shape, and in the region where the dummy conductive layer is formed, the ratio of the conductive layer forming area and the conductive layer non-forming area guided by the pattern shape is the conductive wiring. The structure of the multilayer printed wiring board according to claim 2, wherein the structure is approximately approximate to a ratio of a conductive wiring formation area and a conductive wiring non-formation area in a region where the wiring is formed.

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