JP2007123636A - Nonvolatile memory device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a split gate cell for which an area per memory cell is further reduced. <P>SOLUTION: A serially arranged memory device is composed by serially arranging one or more memory cell pairs having two memory cells on the side of a first charge storage layer, and on the side of a second charge storage layer. The device comprises as a unit a semiconductor substrate where a first diffusion layer and a second diffusion layer of two impurity diffusion layers are arranged on a surface; the first charge storage layer arranged through a first insulating film and the second charge storage layer arranged through a second insulating film with the semiconductor substrate, which are two charge storage layers arranged in a region between the first diffusion layer and the second diffusion layer; a first control gate electrode arranged adjacently to the first charge storage layer, and capable of controlling the potential of the first charge storage layer; a second control gate electrode arranged adjacently to the second charge storage layer, and capable of controlling the potential of the second charge storage layer; and an auxiliary gate electrode arranged adjacently to the first control gate electrode and the second control gate electrode, and arranged through a third insulating film with the semiconductor substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device and a driving method thereof, and more particularly to a nonvolatile memory having a NAND array structure capable of hot electron writing.

  A general nonvolatile memory in which a charge storage layer is disposed on a channel region between a source and a drain of a semiconductor substrate via a gate insulating film, and a control gate electrode is disposed on the charge storage layer via an insulating film (hereinafter, referred to as “nonvolatile memory”). A non-volatile memory cell (hereinafter referred to as a split gate cell) having a control gate (CG) and an auxiliary gate (AG) between a pair of source and drain is known (for example, Patent Document 1). 1). The split gate cell has the advantage that low current and high speed writing is possible by the function of the auxiliary gate, and that over-erasing, which is a problem with a single gate transistor, does not occur.

  FIG. 15 is an explanatory diagram showing an example of a schematic cross-sectional structure of a conventional nonvolatile memory. FIG. 15A shows a sectional structure of the split gate cell. A portion surrounded by a chain line constitutes a memory cell unit. As shown in FIG. 15A, on the channel region between the source diffusion layer 129 and the drain diffusion layer 131 on the semiconductor substrate 101, a charge storage layer (SN) 123a and a control gate 125a are respectively interposed via insulating films. Be placed. An auxiliary gate electrode (AG) 127a is disposed on the side of the charge storage layer (SN) 123a and the control gate 125a. The source diffusion layer 129 is connected to the bit line (BL) 135 via a contact, and the source diffusion layer 133 of the adjacent memory cell is also commonly connected to the bit line 135.

  FIG. 15B shows the cross-sectional structure of the single gate cell described above. A portion surrounded by a chain line constitutes a memory cell unit. As shown in FIG. 15B, on the channel region between the source diffusion layer 109 and the drain diffusion layer 111 on the semiconductor substrate 101, the charge storage layer (SN) 103a and the control gate 105a are respectively interposed via insulating films. Be placed. The source diffusion layer 109 is connected to the bit line (BL) 115 via a contact, and the source diffusion layer 113 of the adjacent memory cell is also commonly connected to the bit line 115.

In a single gate nonvolatile memory cell, a so-called NAND type memory cell in which a pair of source / drain is shared by a plurality of memory cells is known. FIG. 16 is an explanatory diagram showing an example of a schematic structure of a conventional NAND cell array. As shown in FIG. 16, the conventional NAND type memory cell array is connected to the bit line via select transistors having different select gate electrodes SG3 and SG4, and via select transistors having different select gate electrodes SG1 and SG2. Are respectively connected to the source lines SL.
Japanese Patent Publication No. 2862434

  However, as compared with a standard nonvolatile memory cell formed of a single gate, an additional auxiliary gate area is required, and therefore further reduction of the area per unit memory cell is desired. The present invention provides a serially arranged memory device in which a pair of source / drain is shared by a plurality of memory cells without increasing the area per unit memory cell by forming an auxiliary gate in the split gate cell, and a plurality of the serially arranged memory devices. A matrix-arranged memory device, a serially-arranged memory device, and a method for driving the matrix-arranged memory device are provided.

This invention
(1) A semiconductor substrate in which two impurity diffusion layers, ie, a first diffusion layer and a second diffusion layer are disposed on the surface portion, and a region disposed between the first diffusion layer and the second diffusion layer. A first charge storage layer disposed through the semiconductor substrate and the first insulating film, a second charge storage layer disposed through the second insulating film, and a first charge A first control gate electrode arranged adjacent to the storage layer and capable of controlling the potential of the first charge storage layer, and a potential of the second charge storage layer arranged adjacent to the second charge storage layer A second control gate electrode, and an auxiliary gate electrode disposed adjacent to the first control gate electrode and the second control gate electrode and disposed via the semiconductor substrate and the third insulating film. A memory cell pair having two memory cells on the first charge storage layer side and the second charge storage layer side. Providing series arrangement memory device characterized by being arranged in series above.

Furthermore, this invention
(2) A plurality of the memory devices according to (1) are included, and each memory cell of the memory device is arranged in series in the X direction, and is included in the memory devices that are different from each other in the Y direction different from the X direction. A common first control gate line in which the first control gate electrodes of the memory cells to be connected to each other and a second control gate electrode of the memory cell included in the memory device different from each other in the Y direction different from the X direction. A common second control gate line connected to each other and a common auxiliary gate line to which auxiliary gate electrodes of memory cells included in the memory devices different from each other in the Y direction different from the X direction are connected to each other. A matrix arrangement memory device is provided.

Furthermore, this invention
(3) A plurality of serially arranged memory devices and select transistors arranged corresponding to the second diffusion layer of the memory cell pair arranged at the second diffusion layer side end of each serially arranged memory device. A selection transistor having a gate; one bit line connected to each second diffusion layer of the memory cell pair at the end of the second diffusion layer side through a corresponding selection transistor; A source line for connecting the first diffusion layers of the memory cell pair arranged at the end of the one diffusion layer side, one or more common auxiliary gate lines to which the corresponding auxiliary gates of the serially arranged memory devices are respectively connected, Provided is a matrix-arranged memory device configured in units of a serially-arranged memory unit including one or more common control gate lines to which corresponding control gates of the serially-arranged memory device are respectively connected. .

In addition, this invention
(4) A plurality of serially arranged memory devices, one bit line for mutually connecting the second diffusion layers of the memory cell pair arranged at the second diffusion layer side end of each serially arranged memory device, and each serially arranged device A plurality of source lines respectively connected corresponding to the first diffusion layer of the memory cell pair arranged at the first diffusion layer side end of the memory device and one auxiliary gate of each serially arranged memory device are connected to each other. A matrix-arranged memory device configured in units of series-arranged memory units each including one or more common auxiliary gate lines and one or more common control gate lines to which one control gate of each series-arranged memory device is connected to each other provide.

From a different point of view, the present invention
(5) A method of reading a selected memory cell in the memory cell pair arranged in the memory device of (1), wherein the first diffusion layer of the memory cell pair arranged at the end on the first diffusion layer side To the second diffusion layer of the memory cell pair disposed at the end on the second diffusion layer side, a voltage capable of flowing a channel current to the source is applied to the source, and the source or the drain is connected to each auxiliary gate electrode. A voltage is applied so as to extend, a voltage higher than a threshold voltage is applied to the control gate electrode of an unselected memory cell so as to extend the source or the drain, and the control gate electrode of the selected memory cell Provided is a method for applying a voltage capable of controlling a channel current according to the charge of a charge storage layer.
Here, the selected memory cell is one memory cell to be read, and the memory cell on the first diffusion layer side or the second diffusion layer side of one memory cell pair in the serially arranged memory device. One memory cell. The memory cell includes a charge storage layer, a control gate, and an auxiliary gate. The auxiliary gate is shared with the other memory cell of the same memory cell pair.

Furthermore, this invention
(6) A method for writing to a selected memory cell arranged on the first diffusion layer side in the memory cell pair arranged in the memory device of (1), wherein the write is performed at the end on the second diffusion layer side. The second diffusion layer of the arranged memory cell pair is used as a source, a write voltage is applied to the first diffusion layer of the memory cell pair arranged at the end on the first diffusion layer side, and the drain is used. A voltage is applied to the control gate electrode so as to extend the source or the drain, and a voltage is applied to each auxiliary gate electrode shared between unselected memory cells so as to extend the source or the drain. A method is provided in which a voltage for injecting charges into a charge storage layer of a selected memory cell is applied to a control gate electrode of the cell, and a voltage of about the threshold voltage is applied to an auxiliary gate electrode of the selected memory cell.

Furthermore, this invention
(7) A method for writing to a selected memory cell disposed on the second diffusion layer side in the memory cell pair disposed in the memory device of (1), wherein the write operation is performed at an end on the first diffusion layer side. The first diffusion layer of the arranged memory cell pair is used as a source, a write voltage is applied to the second diffusion layer of the memory cell pair arranged at the end on the second diffusion layer side to form a drain, and each of the unselected memory cells A voltage is applied to the control gate electrode so as to extend the source or the drain, and a voltage is applied to each auxiliary gate electrode shared between unselected memory cells so as to extend the source or the drain. A method is provided in which a voltage for injecting charges into a charge storage layer of a selected memory cell is applied to a control gate electrode of the cell, and a voltage of about the threshold voltage is applied to an auxiliary gate electrode of the selected memory cell.

In addition, this invention
(8) An erasing method for collectively erasing memory cells in the memory cell pair arranged in the memory device of (1), wherein a positive voltage is applied to the semiconductor substrate with respect to each control gate electrode. A method of extracting electrons from each charge storage layer to the semiconductor substrate.

In the memory device of (1), a plurality of memory cell pairs are arranged in series between the first diffusion layer and the second diffusion layer, and two memory cells in the memory cell pair share an auxiliary gate electrode. Since the gate is formed, the area per unit memory cell does not increase. Therefore, the area per unit memory cell can be reduced as compared with a configuration in which each memory cell has a diffusion layer as a source and a drain, a control gate electrode, and an auxiliary gate electrode.
Further, the memory cell pairs adjacent to each other may share the impurity diffusion layer. By sharing the impurity diffusion layer, the area per unit memory cell can be further reduced.

The first charge storage layer and the first control gate electrode are adjacent to each other through the fourth insulating film, and the second charge storage layer and the second control gate electrode are adjacent to each other through the fifth insulating film. Also good.
The first charge storage layer may be adjacent to the auxiliary gate electrode via a sixth insulating film, and the second charge storage layer may be adjacent to the auxiliary gate electrode via a seventh insulating film.
Further, the first control gate electrode may be disposed adjacently above the first charge storage layer, and the second control gate electrode may be disposed adjacently above the second charge storage layer.

  According to another aspect of the present invention, an impurity diffusion layer shared with one memory cell pair of memory cell pairs included in the memory device, and a region adjacent to the impurity diffusion layer are disposed via the semiconductor substrate and a third insulating film. A third charge storage layer, a third control gate electrode arranged adjacent to the third charge storage layer and capable of controlling the potential of the third charge storage layer, and adjacent to the third control gate. A single memory cell including the semiconductor substrate and an auxiliary gate electrode disposed via an eighth insulating film is arranged in series at one or both ends of the memory cell pair. A placement memory device is provided.

  The memory device of (2) includes a plurality of the serially arranged memory devices, and the memory cells in the serially arranged memory devices different from each other share the control gate electrode and the auxiliary gate electrode, respectively. Therefore, it is possible to realize a memory device in which memory cells having a small area per unit cell are arranged in a matrix in the XY direction.

  Furthermore, since the memory devices of (3) and (4) are each configured with a serially arranged memory unit including a plurality of serially arranged memory devices, memory cells having a small area per unit cell are connected in series. It is possible to realize a memory device that is configured with a placement memory unit as a unit.

In the reading method (5), a voltage is applied to each auxiliary gate electrode so as to extend the source or the drain, and the source or the drain is extended to the control gate electrode of the non-selected memory cell. A voltage higher than the threshold voltage is applied, and a voltage capable of controlling the channel current according to the charge in the charge storage layer of the selected memory cell is applied to the control gate electrode of the selected memory cell, so that the channel current of the selected memory cell is read out As a result, the state of the selected memory cell can be read out.
Here, the same voltage may be applied to each control gate electrode of the non-selected memory cell. Alternatively, a different voltage may be applied to each control gate electrode of an unselected memory cell. In either case, any voltage that extends the source or drain may be used.
Further, the same voltage may be applied to each auxiliary gate electrode shared between unselected memory cells. Alternatively, a different voltage may be applied to each auxiliary gate electrode shared between unselected memory cells. In either case, any voltage that extends the source or drain may be used.
Further, a voltage lower than the applied voltage of each control gate electrode on the second diffusion layer side than the selected memory cell may be applied to each control gate electrode on the first diffusion layer side of the selected memory cell.
Further, in each auxiliary gate electrode shared between non-selected memory cells, a voltage lower than the voltage applied to each auxiliary gate electrode on the second diffusion layer side than the selected memory cell is set to be the first diffusion than the selected memory cell. It may be applied to each auxiliary gate electrode on the layer side.

Furthermore, in the writing method of (6), each auxiliary gate electrode shared between unselected memory cells is applied by applying a voltage to each control gate electrode of the unselected memory cell so as to extend the source or the drain. A voltage is applied so as to extend the source or the drain, a voltage for injecting a charge into the charge storage layer of the selected memory cell is applied to the control gate electrode of the selected memory cell, and an auxiliary gate electrode of the selected memory cell is applied. By applying a voltage of about the threshold voltage, an SSI (Source-Side Injection) system that generates a high electric field in the channel region between the auxiliary gate electrode and the control gate electrode of the selected memory cell is realized, with high injection efficiency. Charges can be injected into the charge storage layer of the selected memory cell.
Here, the same voltage may be applied to each control gate electrode of the non-selected memory cell. Alternatively, a different voltage may be applied to each control gate electrode of an unselected memory cell. In either case, any voltage that extends the source or drain may be used.
Further, the same voltage may be applied to each auxiliary gate electrode shared between unselected memory cells. Alternatively, a different voltage may be applied to each auxiliary gate electrode shared between unselected memory cells. In either case, any voltage that extends the source or drain may be used.
Furthermore, a voltage higher than the voltage applied to each control gate electrode closer to the second diffusion layer than the selected memory cell may be applied to each control gate electrode closer to the first diffusion layer than the selected memory cell.
Further, in each auxiliary gate electrode shared between non-selected memory cells, a voltage higher than the voltage applied to each auxiliary gate electrode on the second diffusion layer side than the selected memory cell is set to be higher than that of the selected memory cell. It may be applied to each auxiliary gate electrode on the layer side.

  Alternatively, in the writing method of (7), a voltage is applied to each control gate electrode of an unselected memory cell so as to extend the source or the drain, and each auxiliary gate electrode shared between unselected memory cells is applied. A voltage for extending the source or the drain is applied, a voltage for injecting charges into the charge storage layer of the selected memory cell is applied to the control gate electrode of the selected memory cell, and the threshold voltage is about the auxiliary gate electrode of the selected memory cell Is applied to realize a SSI (Source-Side Injection) method in which a high electric field is generated in the channel region between the auxiliary gate electrode and the control gate electrode of the selected memory cell, and the selected memory cell is realized with high injection efficiency. Charge can be injected into the charge storage layer.

The erasing method (8) is a simple driving method in which a positive voltage is applied to the semiconductor substrate with respect to each control gate electrode, and the memory cells arranged in the serially arranged memory device are batched. Can be erased.
In the erasing method (8), each control gate electrode may be grounded. Alternatively, a negative bias voltage may be applied to each control gate electrode. Alternatively, a positive bias voltage may be applied to each control gate electrode.
Further, the auxiliary gate electrode may be grounded or a negative voltage may be applied. In this way, electrons can be extracted more efficiently.

Furthermore, the present invention provides an erasing method for erasing a selected memory cell on the first diffusion layer side in the memory cell pair arranged in the memory device of (1), wherein the selected memory cell is at the end on the first diffusion layer side. A positive voltage for extracting electrons from the charge storage layer of the selected memory cell is applied to the first diffusion layer of the arranged memory cell pair as a drain, and the control gate of the memory cell on the drain side of the selected memory cell A voltage higher than a threshold voltage is applied to the electrode so as to extend the drain, and a voltage is applied so as to extend the drain to the auxiliary gate electrode of the memory cell on the drain side from the selected memory cell. Provided is a method of applying a voltage for extracting electrons from the charge storage layer to the semiconductor substrate to a control gate electrode. According to this method, an arbitrary memory cell on the first diffusion layer side in the memory cell pair arranged in the memory device of (1) can be erased.
In the erasing method, the auxiliary gate electrode of the selected memory cell may be grounded or a negative voltage may be applied. In this way, the writing efficiency can be further increased.

Alternatively, the present invention provides an erasing method for erasing a selected memory cell on the second diffusion layer side in the memory cell pair arranged in the memory device of (1), wherein the selected memory cell is at the end on the second diffusion layer side. A voltage for withdrawing electrons from the charge storage layer of the selected memory cell is applied to the second diffusion layer of the arranged memory cell pair as a drain, and the control gate electrode of the memory cell on the drain side of the selected memory cell is applied to the drain A voltage higher than a threshold voltage is applied so as to extend the drain, a voltage is applied so as to extend the drain from the selected memory cell to the auxiliary gate electrode of the memory cell on the drain side, and a control gate of the selected memory cell Provided is a method of applying a voltage for extracting electrons from the charge storage layer to the semiconductor substrate. According to this method, an arbitrary memory cell on the first diffusion layer side in the memory cell pair arranged in the memory device of (1) can be erased.
In the erasing method, the auxiliary gate electrode of the selected memory cell may be grounded or a negative voltage may be applied. In this way, the writing efficiency can be further increased.

  The present invention is also an erasing method for erasing a selected memory cell on one side of the memory cell pair arranged in the memory device of (1), wherein diffusion at the one end of the memory device is performed. A voltage is applied to the layer to supply holes to the charge storage layer of the selected memory cell, and the threshold is set so that the potential of the diffusion layer at one end is extended to the control gate electrode on the one side of the selected memory cell. A voltage higher than the voltage is applied, a voltage is applied from the selected memory cell to the auxiliary gate electrode on the one side so as to extend the potential of the diffusion layer at the one end, and the control gate electrode of the selected memory cell A method of applying a voltage for injecting holes into the charge storage layer of a memory cell is provided. According to this method, an arbitrary memory cell in the memory cell pair arranged in the memory device of (1) can be erased.

  In the erasing method, the auxiliary gate electrode of the selected memory cell may be grounded or a negative voltage may be applied. In this way, the writing efficiency can be further increased.

  Furthermore, according to the present invention, the memory cells on the first diffusion layer side and the second diffusion layer side included in the selected memory cell pair among the memory cell pairs arranged in the memory device of (1) are collectively collected. An erasing method is a first method for extracting electrons from a charge storage layer on a first diffusion layer side of a selected memory cell pair into a first diffusion layer of a memory cell pair disposed at an end on the first diffusion layer side. A voltage is applied, and a second voltage for extracting electrons from the charge storage layer on the second diffusion layer side of the selected memory cell pair is applied to the second diffusion layer of the memory cell pair disposed at the end on the second diffusion layer side. A voltage higher than the threshold voltage is applied to the control gate electrode of the unselected memory cell pair so as to extend the potential of the first diffusion layer to which the first voltage is applied or the second diffusion layer to which the second voltage is applied. The first voltage is applied to the auxiliary gate electrode of the unselected memory cell pair. A voltage is applied to extend the potential of the applied first diffusion layer or the second diffusion layer to which a voltage is applied, and the charge of each charge storage layer is transferred to each control gate electrode of the selected memory cell pair. A method for applying a voltage to be pulled out is provided. According to this method, the memory cells on the first diffusion layer side and the second diffusion layer side included in an arbitrary memory cell pair in the memory device can be erased collectively.

  According to the present invention, when writing and verify reading are sequentially performed on each memory cell of the plurality of memory cell pairs in the memory device of (1), writing or verify reading is sequentially performed from the memory cells on the first diffusion layer side. And provide a way to do.

  Further, according to the present invention, when erasing and verify reading are sequentially performed on each memory cell of the plurality of memory cell pairs in the memory device of (1), the erasing or verify reading is sequentially performed from the memory cells on the first diffusion layer side. Provide a way to do.

  Alternatively, according to the present invention, when data is written to the selected memory cell on the second diffusion layer side of the memory cell pair in the serially arranged memory unit in the memory device of (3), the other non-serially arranged memory devices A write blocking method for blocking writing to a selected memory cell, wherein the source line is grounded to function as a source, and the selection transistor is connected to a selection gate of a selection transistor corresponding to a serially arranged memory device including the selected memory cell. Applying a connection voltage to turn on and connecting to a bit line, and applying a write voltage to the bit line to cause it to function as a drain, except for a select transistor in which the connection voltage is applied to a select gate A voltage for turning off the selection transistor is applied to the selection gate of the selection transistor to prevent writing to the unselected memory cell. To provide a method for. According to this write blocking method, writing to each unselected memory cell in the serially arranged memory device that does not include the selected memory cell can be blocked.

  Furthermore, according to the present invention, when data is written to the selected memory cell on the first diffusion layer side of the memory cell pair in the serially arranged memory unit in the memory device of (3), the other non-serially arranged memory devices A write blocking method for blocking writing to a selected memory cell, wherein a voltage for turning on the selected transistor is applied to a selection gate of a selection transistor corresponding to a serially arranged memory device including the selected memory cell and connected to a bit line. The bit line is grounded to function as a source, and when writing is performed by applying a write voltage to the source line and functioning as a drain, source lines other than the source line to which the write voltage is applied are grounded. A method of preventing writing to unselected memory cells. According to this write blocking method, writing to each unselected memory cell in the serially arranged memory device that does not include the selected memory cell can be blocked.

  Furthermore, according to the present invention, when data is written to the selected memory cell on the second diffusion layer side of the memory cell pair in the serially arranged memory unit of the memory device of (4), the non-serially connected memory device of A write blocking method for blocking writing to a selected memory cell, wherein the source line of a serially arranged memory device including the selected memory cell is grounded as a source, and a write voltage is applied to a bit line to perform writing as a drain. In this case, a method is provided in which a voltage as a counter bias is applied to a source line other than the grounded source line to prevent writing to an unselected memory cell. According to this write blocking method, writing to each unselected memory cell in the serially arranged memory device that does not include the selected memory cell can be blocked.

  Further, according to the present invention, when data is written to the selected memory cell on the first diffusion layer side of the memory cell pair in the serially arranged memory unit of the memory device of (4), other serially arranged memory devices are not selected. A write blocking method for blocking writing to a memory cell, wherein a bit line is grounded as a source, and a write voltage is applied to the source line of a serially arranged memory device including a selected memory cell to perform writing as a drain. In addition, a method is provided in which writing to an unselected memory cell is prevented by grounding a source line other than the source line to which the write voltage is applied. According to this write blocking method, writing to each unselected memory cell in the serially arranged memory device that does not include the selected memory cell can be blocked.

The semiconductor substrate is made of, for example, a p-type Si substrate, but the material is not limited to this, and a compound semiconductor substrate such as GaAs can be used. For the auxiliary gate and the control gate, materials that are normally used as electrodes can be used, but polysilicon is preferable. The charge storage layer can be formed using SiN or polysilicon (Poly-Si). The insulating film between the semiconductor substrate and the auxiliary gate electrode is formed of, for example, a SiO ₂ film, and the film thickness is preferably about 2 to 10 nm. The insulating film on the side walls of the first and second auxiliary gate electrodes is formed of, for example, a SiO ₂ film, and the film thickness is preferably about 2 to 10 nm. The SiO ₂ film can be formed by a known method such as a CVD method using SiH ₄ or SiH ₂ Cl ₂ or a thermal oxidation method. Further, the material of the insulating film is not limited to SiO _2, and a material normally used as an insulating film can be used.

  Hereinafter, the present invention will be described in more detail with reference to the drawings. The following description will provide a better understanding of the present invention. In addition, this invention is not limited by the following description.

(Structure of serially arranged memory device)
FIG. 1 is an explanatory diagram showing an example of a schematic cross-sectional structure of a serially arranged memory device (serial memory array) according to the present invention. Of the configuration examples of the serial memory array of the present invention, the simplest configuration example is a case where two memory cells are connected in series as shown in FIG. First, the configuration of the serial memory array will be described with reference to FIG. In the serial memory array 10 shown in FIG. 1A, a first diffusion layer 9 and a second diffusion layer 11 are formed on the surface portion of the semiconductor substrate 1, and the first diffusion layer 9 and the second diffusion layer 11 are formed. A first control gate electrode (CG1) 5a and a second control gate electrode (CG2) 5b for controlling the potential of the first charge storage layer 3a, the second charge storage layer 3b, the first charge storage layer 3a on the semiconductor substrate. An auxiliary gate electrode (AG) 7 is disposed. The auxiliary gate electrode is disposed adjacent to the first control gate electrode 5a and the second control gate electrode 5b. A memory cell pair (split gate cell) according to the present invention is constituted by the above-described units. Of these, the first charge storage layer 3a, the first control gate 5a, and the auxiliary gate electrode 7 disposed on the first diffusion layer side constitute one memory cell C1, and the second charge layer 3a disposed on the second diffusion layer side. The charge storage layer 3b, the second control gate 5b, and the auxiliary gate electrode 7 constitute one memory cell C2. The auxiliary gate electrode 7 is shared by the two memory cells. The two memory cells share the first diffusion layer 9 and the second diffusion layer 11, one of which functions as a source and the other functions as a drain. Thus, in the serial memory array configured by arranging a plurality of memory cells between a pair of source / drain, the auxiliary gate electrode 7 can be formed in the space between the control gate electrodes. There is no increase in cell area due to the formation of.

  FIGS. 1B, 1C, and 1D are explanatory views showing a schematic cross-sectional structure of a serial memory array 10 in which four or more cells are connected in series. In FIGS. 1B, 1C, and 1C, a portion surrounded by a chain line constitutes a unit of a memory cell pair. FIG. 1B shows a serial memory cell array in which n split gate cells P1 to Pn are connected in series. The split gate cell at the end on the first diffusion layer 9 side is P1, and the second diffusion layer 11 side is shown. The split gate cell at the end of Pn is Pn. In FIG. 1C, n−1 split gate cells P1 to P (n−1) are connected in series, and a single memory cell M1 is arranged at the end of the first diffusion layer 9 side. 11 is a serial memory cell array in which a single memory cell M2 is arranged at the end on the 11th side. A single memory cell shares a diffusion layer with an adjacent split gate cell, a charge storage layer adjacent to the shared diffusion layer, a control gate electrode capable of controlling the potential of the charge storage layer, and adjacent to the control gate electrode And the diffusion layer adjacent to the auxiliary gate electrode. For example, the single memory cell M1 shares the diffusion layer 13a with the adjacent split gate cell P1, has the charge storage layer 3a adjacent to the diffusion layer 13a, and the charge storage layer 3a above the charge storage layer 3a. A control gate electrode 7a capable of controlling the potential of the first diffusion layer 9 is disposed adjacent to the control gate electrode 7a. FIG. 1D shows a serial memory cell array in which n-1 split gate cells P1 to P (n-1) are connected in series, and a single memory cell M is arranged at the end on the second diffusion layer 11 side. It is.

  As shown in FIGS. 1B, 1C, and 1D, a series memory array configured by arranging a plurality of split gate cells in series and arranging a single memory cell or no arrangement at both ends thereof, Since the auxiliary gate electrode 7 can be formed in the space between the control gate electrodes, there is no increase in cell area due to the formation of the auxiliary gate.

(Reading memory cells)
FIG. 2 is an explanatory diagram showing a driving method in the case of reading a selected memory cell in the serial memory array of the present invention. Note that the voltage values in the following description are merely examples, and are not limited to these values. 2A corresponds to the serial memory array of FIG. 1B, where DL1 is the first diffusion layer 9, CG1 is the first control gate electrode 5a, AG1 is the auxiliary gate electrode 7a, and CG2 is the first. 2 corresponds to each control gate electrode 5b. 2B corresponds to the serial memory array of FIG. 1C, DL1 is in the diffusion layer 9 of the single memory cell M1, AG1 is in the auxiliary gate 7a of the single memory cell M1, and CG1 is in the single memory cell M1. CG4 corresponds to the control gate 5n of the single memory cell M2, AG3 corresponds to the auxiliary gate 7n of the single memory cell M2, and DL2 corresponds to the diffusion layer 11 of the single memory cell M2. 2B and 2C exemplify the case of reading the selected cell C2 (memory cell having the control gate CG2) in the serial memory array. Application to other memory cells based on the examples is easy for those skilled in the art.

Referring to FIG. 2A, in order to read the selected cell C2, 0V is applied as a read voltage to the gate CG2 of C2 (that is, grounded), and the control gates CG1 and CG3 of the unselected memory cells C1, C3, and C4. , CG4 is applied with a voltage of 6V, which is larger than the threshold value, as the third voltage, and the non-selected memory cell is turned on. Further, a voltage of 5 V is applied as a second voltage to all the auxiliary gates AG1 and AG2 so as to turn on the channel region below the auxiliary gates AG1 and AG2. In this way, if the threshold value of the selected memory cell C2 is lower than the read voltage, C2 is turned on, and if it is higher, C2 is turned off. An electric field is applied so that a channel current flows by applying a voltage of 0 V to the first diffusion layer DL1 as the source and a voltage of 2 V as the first voltage to the second diffusion layer DL2 as the drain. Then, a channel current may or may not flow depending on the state of the charge accumulated in the charge accumulation layer of the memory cell C2. The state of the memory cell C2 can be read by detecting the channel current.
In the above-described embodiment, the same voltage (third voltage) is applied to the control gate electrodes CG1, CG3, and CG4 of the non-selected memory cells, but different voltages may be applied. The voltage is not limited to the same voltage as long as the voltage extends the source or drain.
Also in FIG. 2B, the applied voltages to the corresponding parts are the same. It should be noted that application to the reading method to the memory cell of FIG. 1D is easy from FIGS. 2B and 2C.

(Write to memory cell)
FIG. 3 is an explanatory diagram showing a driving method when writing to a selected memory cell in the serial memory array of the present invention. FIG. 3A corresponds to the serial memory array of FIG. 1B and does not have a single memory cell at both ends. FIG. 3B corresponds to the serial memory array of FIG. 1C and has a single memory cell at both ends. 3B and 3C exemplify a case where data is written to the selected cell C1 in the serial memory array and a case where data is written to C2. Application to other memory cells based on the example is easy.

  In FIG. 3A, a case where data is written to the cell C1 will be described as a typical example when the selected cell is a memory cell on the first diffusion layer side among the split gate cells. In this case, 4.5 V is applied as the write voltage (fifth voltage) to the first diffusion layer 9, and the second diffusion layer DL2 is grounded. Then, a voltage of 12V sufficiently larger than the threshold is applied as the sixth voltage to the control gates CG2, CG3, and CG4 of the unselected memory cells, and the seventh voltage is applied to the auxiliary gate electrode AG2 shared between the unselected memory cells. A voltage of 8V is applied so as to work as an extension of the second diffusion layer DL2 as a drain. On the other hand, a voltage of 12V is applied as the eighth voltage for injecting charges into the control gate electrode CG1 of the selected cell C1, and a voltage of 1V, which is about the threshold value, is applied as the ninth voltage to the auxiliary gate AG1 adjacent to the selected cell C1. Apply. As a result, a high voltage is generated in the channel region between the auxiliary gate AG1 and the control gate CG1, and writing to the cell C1 can be performed with high injection efficiency.

  Next, as a representative example of the case where the selected cell is a memory cell on the first diffusion layer side among the split gate cells, a case where writing to the cell C2 is performed will be described. In this case, 4.5 V is applied as a write voltage (fifth voltage) to the second diffusion layer DL2, and the first diffusion layer DL1 is grounded. Then, a voltage of 12V, which is sufficiently higher than the threshold, is applied as the sixth voltage to the control gate electrodes of the non-selected memory cells, that is, CG1, CG3, CG4, and the auxiliary gate electrode AG2 shared between the non-selected memory cells is 7V is applied as 8V so that the first diffusion layer DL1 as the source and the second diffusion layer DL2 as the drain are extended. On the other hand, a voltage of 12V is applied as the eighth voltage for injecting charges into the control gate electrode CG2 of the selected cell C2, and a voltage of 1V, which is about the threshold value, is applied as the ninth voltage to the auxiliary gate AG1 adjacent to the selected cell C2. Is applied. As a result, a high voltage is generated in the channel region between the auxiliary gate AG1 and the control gate CG2, and writing to the cell C2 can be performed with high injection efficiency.

Next, a driving method in the case where data is written to the selected cells C1 and C2 in the serial memory array of FIG.
In FIG. 3B, a case where data is written to the cell C2 will be described as a typical example when the selected cell is a memory cell on the first diffusion layer side among the split gate cells. In this case, 4.5 V is applied to the first diffusion layer 9 as a write voltage (fifth voltage), and the second diffusion layer 11 is grounded. Then, a voltage of 12V sufficiently larger than the threshold is applied as the sixth voltage to the control gates CG1, CG3, and CG4 of the unselected memory cells, and the seventh voltage is applied to the auxiliary gate electrodes AG1 and AG3 shared between the unselected memory cells. A voltage of 8V is applied as a voltage so that the first diffusion layer DL1 as a source and the second diffusion layer DL2 as a drain are extended. On the other hand, a voltage of 12V is applied as the eighth voltage for injecting charges into the control gate electrode CG1 of the selected cell C1, and a voltage of 1V, which is about the threshold value, is applied as the ninth voltage to the auxiliary gate AG2 adjacent to the selected cell C1. Is applied. As a result, a high voltage is generated in the channel region between the auxiliary gate AG2 and the control gate CG2, and writing to the cell C2 can be performed with high injection efficiency.

  Next, as a representative example in the case where the selected cell is a single memory cell on the first diffusion layer side, a case where writing to the cell C1 is performed will be described. In this case, 4.5 V is applied as a write voltage (fifth voltage) to the second diffusion layer DL2, and the first diffusion layer DL1 is grounded. Then, a voltage of 12V sufficiently higher than the threshold value is applied as the sixth voltage to the control gate electrodes of the non-selected memory cells, that is, CG2, CG3, CG4, and the auxiliary gate electrodes AG2, AG3 shared between the non-selected memory cells. 8V is applied as a seventh voltage to act as an extension of the source and drain. On the other hand, a voltage of 12V is applied as the eighth voltage for injecting charges into the control gate electrode CG1 of the selected cell C1, and a voltage of 1V, which is about the threshold value, is applied as the ninth voltage to the auxiliary gate AG1 adjacent to the selected cell C1. Is applied. As a result, a high voltage is generated in the channel region between the auxiliary gate AG1 and the control gate CG1, and writing to the cell C1 can be performed with high injection efficiency.

(Erase memory cells)
FIG. 4 is an explanatory diagram showing an example of a driving method for erasing all the memory cells in the serial memory array of the present invention. As shown in FIGS. 4A and 4B, in order to erase the memory cells all together, a high voltage of 20 V is applied to the semiconductor substrate 1, and all the control gates CG1 to CG4 and auxiliary gates AG1 to AG2 are turned on. Ground. As a result, electrons can be extracted from the charge storage layers 3a, 3b, 3c, and 3d to the semiconductor substrate 1 to lower the threshold value of each memory cell.

  FIG. 5 is an explanatory diagram showing an example of a driving method for selectively erasing memory cells in the serial memory array of the present invention. For example, the case of erasing the memory cell C1 will be described as an example of erasing the memory cell on the first diffusion layer DL1 side in the memory cell pair in the serial memory array 10 in FIG. In this case, 5V is applied as the 11th voltage to the first diffusion layer DL1, and −10V is applied as the 14th voltage to the control gate CG1 of the selected cell C1, and the charge storage layer 3a of the selected cell C1 is adjacent to it. Electrons are extracted to the first diffusion layer DL1. At this time, if a voltage of −10 V is applied as the fifteenth voltage to the auxiliary gate electrode AG1 adjacent to the selected cell C1, erasing can be performed more efficiently. Further, the control gate electrodes CG2, CG3, and CG4 of the non-selected memory cells on the second diffusion layer DL2 side from the selected cell C1 have the twelfth voltage as a voltage that suppresses electrons from being extracted from the corresponding charge storage layer. Apply voltage. Further, when the thirteenth voltage is applied to the auxiliary gate electrode AG2 that is closer to the second diffusion layer DL2 than the selected cell C1 and is shared among the non-selected memory cells, the second diffusion layer DL2 is grounded. Good.

  In addition, in FIG. 5A, the case of erasing the memory cell C2 will be described as a representative example of erasing the memory cell on the second diffusion layer DL2 side in the memory cell pair in the serial memory array 10. In this case, a voltage of 5 V for extracting electrons from the charge storage layer of the memory cell C2 is applied to the second diffusion layer DL2 as an eleventh voltage so as to function as a drain, and the second diffusion layer DL2 side of the memory cell C2 A voltage of 11V higher than the threshold voltage is applied as the twelfth voltage to extend the drain to the control gate electrodes CG3 and CG4 of the memory cell, and the auxiliary gate electrode of the memory cell on the second diffusion layer DL2 side from the selected memory cell C2 A voltage of 8V extending the drain is applied as a thirteenth voltage to AG2. Then, a voltage of −10 V is applied as the 14th voltage to the control gate CG2 of the selected cell C2, and electrons are extracted from the charge storage layer 3b of the selected cell C2 to the adjacent diffusion layer 13 side. The diffusion layer 13 functions as an extended drain. At this time, if a voltage of −10 V is applied as the fifteenth voltage to the auxiliary gate electrode AG1 adjacent to the selected cell C2, erasing can be performed more efficiently. The twelfth voltage is applied to the control gate electrode CG1 of the non-selected memory cell on the first diffusion layer DL1 side of the memory cell C2 as a voltage for suppressing electrons from being extracted from the corresponding charge storage layer. . The first diffusion layer DL1 is preferably grounded.

  Further, in FIG. 5A, when the memory cells C1 and C2 in the same split gate cell are erased at once, the control gates CG3 and CG4 of the non-selected cells are shared by 11V and the non-selected cells. A voltage of 8 V is applied to the auxiliary gate AG2 to act as an extension of the first diffusion layer DL1 and the second diffusion layer DL2, and electrons are transferred from the charge storage layer of the selected memory cell to the first diffusion layer DL1 and the second diffusion layer DL2. A voltage of 5 V is applied, and a voltage of -11 V is applied to the control gates CG1 and CG2 of the selected cell and the auxiliary gate AG1 adjacent to the selected cell. In this way, electrons in the charge storage layer 3a of the selected cells C1 and C2 may be extracted to the first diffusion layer 9, and electrons in the charge storage layer 3b may be extracted to the diffusion layer 13.

  FIG. 5B shows a driving method for selectively erasing the cell C1 or C2 and driving for simultaneously erasing C1 and C2 in the serial memory array having the structure corresponding to FIG. The method is shown. For example, in FIG. 5B, the memory cell C2 is erased as a representative example of erasing the memory cell on the first diffusion layer DL1 side in the memory cell pair in the serial memory array 10 in FIG. 5A. The case where it does is demonstrated. In this case, a voltage of 5 V for extracting electrons from the charge storage layer of the memory cell C2 is applied to the first diffusion layer DL1 as an eleventh voltage so as to function as a drain, so that the first diffusion layer DL1 side of the memory cell C2 is closer to the first diffusion layer DL1. A voltage of 11V higher than the threshold voltage is applied to the control gate electrode CG1 of the memory cell as the twelfth voltage so as to extend the drain, and the auxiliary gate electrode AG1 of the memory cell on the first diffusion layer DL1 side from the selected memory cell C2 is applied. A voltage of 8V extending the drain is applied as the thirteenth voltage. Then, a voltage of −10 V is applied as the 14th voltage to the control gate CG2 of the selected cell C2, and electrons are extracted from the charge storage layer 3b of the selected cell C2 to the adjacent diffusion layer 13a. The diffusion layer 13a functions as an extended drain. At this time, the auxiliary gate electrode AG2 adjacent to the selected cell C2 may be grounded. The twelfth voltage is applied to the control gate electrode CG1 of the non-selected memory cell on the first diffusion layer DL1 side of the memory cell C2 as a voltage for suppressing electrons from being extracted from the corresponding charge storage layer. . The first diffusion layer DL1 is preferably grounded. Further, if the voltage of −10 V, for example, is applied as the fifteenth voltage instead of grounding AG2, erasing can be performed more efficiently.

FIG. 6 shows a method of lowering the threshold value by injecting hot holes generated in the diffusion layer formed on the substrate into the storage area. In the case of a memory cell using SNi or the like for the charge storage layer, the erase mechanism is explained by injection of hot holes into the charge storage layer. On the other hand, when the charge storage layer is a floating gate using SiO ₂ or the like, as described in FIG. 5, the erasing mechanism is explained by the extraction of electrons from the charge storage layer.

  Electrons and holes have complementary positive and negative polarities, and the driving method for extracting electrons from the charge storage layer and the driving method for injecting holes into the charge storage layer result in the same voltage applied to each terminal. become.

That is, in FIG. 6A, when erasing the cell C1 having the auxiliary gate electrode on the second diffusion layer 11 side, 5V is applied as the 17th voltage to the first diffusion layer 9, and the auxiliary gate of the selected cell C1 is applied. A voltage of −10V is applied as a 20th voltage to AG1 and control gate CG1, respectively, and holes are injected from the source diffusion layer 9 into the charge storage layer 3a of the selected cell C1. At this time, 11V is applied as the 18th voltage to the control gate electrodes CG2, CG3, and CG4 of the non-selected cells, and 8V is applied as the 19th voltage to the auxiliary gate electrode AG2 adjacent to the non-selected cells. 2 Extend the diffusion layer 11.
In addition, when the selected cell C2 is erased, the driving conditions for simultaneously erasing C1 and C2 are shown in FIG.

(Write verification order)
Writing to the memory cells can be sequentially performed by the writing method shown in FIG. At this time, writing may be performed in order from the memory cell on the first diffusion layer 9 side. For example, the serial memory array of FIG. 3A is written in the order of the memory cells C1, C2, C3, and C4, and the verify read after the write is sequentially performed from the memory cells on the first diffusion layer 9 side as described above. By doing so, it is possible to suppress the influence of the adjacent cell on the first diffusion layer 9 side with respect to the write target cell. Therefore, variation in threshold after writing can be suppressed.

  Alternatively, also in the case of erasing, by performing erasing and verify reading after erasing sequentially from the memory cell on the first diffusion layer 9 side, the influence of the adjacent cell on the first diffusion layer 9 side with respect to the cell to be erased Can be suppressed. Therefore, variation in threshold after erasing can be suppressed.

(Configuration of memory device)
7 to 9 show the configuration of a matrix arrangement memory device (XY memory array) including a plurality of the serial memory arrays of the present invention, the structure of the XY memory array, and writing to selected memory cells in the XY memory array. It is explanatory drawing which shows the drive condition in a case. As shown in FIG. 7, the XY memory array includes memories arranged in a matrix in the X direction and the Y direction, and the serial memory arrays are arranged in the X direction. In the Y direction, the control gate electrode and the auxiliary gate electrode of the memory cells in each serial memory array are connected in common.

  In the XY memory array shown in FIG. 7, as shown in FIG. 7A, different serial memory arrays are connected to the bit line BL1 or BL2 through two selection transistors each having selection gate electrodes SG1 and SG2. Thus, a serially arranged memory unit is configured. All serial memory arrays are connected to one source line SL. FIG. 7B shows driving conditions for writing to the cells C11 and C21 in the XY memory array shown in FIG. First, when writing to the cell C11, a writing voltage of 4.5 V is applied to the source line SL. A voltage of 8V, which is sufficiently higher than the threshold, is applied to the gate SG1 of the selection transistor connected to the selected bit line BL1, and a voltage of 0V is applied to the gate SG2 of the selection transistor of the unselected bit line BL2. Further, a voltage of 2V is applied to the unselected bit line BL2 to prevent erroneous writing. Other applied voltages are the same as in the case of writing to the cell C1 in FIG. 3A, and specific applied voltages are as shown in FIG. 7B.

  When writing to the cell C21, a 4.5V write voltage is applied to the selected bit line BL1, an 8V voltage sufficiently higher than the threshold is applied to SG1, and SG2 and SL are grounded. Other applied voltages are the same as in the case of writing to the cell C2 in FIG. 3A, and specific applied voltages are as shown in FIG. 7B.

In FIG. 8, one bit line BL1 or BL2 is connected to the drain of the serial memory array via a selection transistor having the same selection gate electrode SG, and connected to the same bit line to constitute a serially arranged memory unit. It is explanatory drawing which shows an example of a structure at the time of enabling it to apply a different voltage to the source of each serial memory array to perform, and write conditions. First, when writing to the cell C11, a write voltage of 4.5V is applied to the source line SL1 of the serial memory array including the selected cell C11, and the bit line BL1 commonly connected to the serial memory array including the selected cell C11 is grounded. To do. On the other hand, a voltage of 2V is applied to the unselected bit line BL2 to prevent erroneous writing. Further, the unselected source line SL2 is grounded. Then, a voltage of 8V sufficiently higher than the threshold is applied to the gate SG of the selection transistor. The voltages applied to the other parts are as shown in FIG.
When writing to the cell C21, a 4.5V write voltage is applied to BL1, a 2V voltage is applied to SL2 to prevent erroneous writing, and SL1 is grounded.

  FIG. 9 is an explanatory diagram showing a configuration when the XY memory array has a structure corresponding to the serial memory array of FIG. 1C, and driving conditions for reading and writing of memory cells. In the XY memory array shown in FIG. 9, the selection gate is formed simultaneously with AG.

(Method for manufacturing memory device)
Next, an example of a method for manufacturing an XY memory array comprising the serial memory array of the present invention will be described.

<< First Embodiment >>
FIG. 10 is a plan view showing a schematic structure of an XY memory array in which a plurality of the serial memory arrays are arranged in the YY ′ direction, taking the serial memory array of FIG. It is each sectional drawing of a X ', YY' direction. 10A is a plan view, and FIG. 10B is a cross-sectional view corresponding to FIG. 1A, and is a cross-sectional view of a serial memory array arranged in the XX ′ direction perpendicular to the control gates CG1 and CG2. FIG. 10C is a cross-sectional view in the YY ′ direction along the control gate in FIG.

  11 and 9-2 are manufacturing process diagrams showing the order of processes for manufacturing the XY memory array according to the present invention. 11 and 9-2, each drawing in the left column shows an X-X 'cross section, and each drawing in the right column shows a Y-Y' cross section.

  First, as shown in FIGS. 11A and 11B, after the trench element isolation regions 21a, 21b, and 21c are formed on the semiconductor substrate 1 made of Si of the first conductivity type (here, p-type). Then, thermal oxidation is performed to form a fifth insulating film (gate insulating film) 9 having a thickness of about 5 to 15 nm, a first polysilicon film 22 having a thickness of about 50 nm, and a silicon vagina having a thickness of about 50 nm. A film (SiN film) 3 is sequentially deposited. Here, the charge storage layer of the XY memory array is made of SiN. However, the charge storage layer may be another trapping film or a floating gate such as polysilicon.

  Subsequently, a sixth insulating film 23 made of an oxide film and a polysilicon film to be the control electrode 5 are further deposited on the SiN film 3, and a resist is applied thereon, followed by patterning the resist using a lithography technique. A resist pattern 27 is formed. Then, the portions of the control electrode 5, the sixth insulating film 23, the first silicon vaginaization film 3 and the first polysilicon film 22 where the resist 27 is removed by patterning are removed by etching, and then the resist pattern 27 is peeled off. Thus, as shown in FIGS. 11C and 11D, a plurality of charge storage layers 3 and control gate electrodes 5 extending along the Y-Y ′ direction are formed.

Next, the channel region for forming the auxiliary gate AG is covered with a resist 29, and ion implantation is performed to form the diffusion layers 9 and 11 (FIG. 11E).
Subsequently, polysilicon as the second electrode is deposited, and the auxiliary gate AG7 is embedded between the control gates CG1 and CG2 by an etch back technique (FIG. 11 (g)).
In the above description of the manufacturing process, an insulating film is formed between the silicon vagina film 3 and the semiconductor substrate 1 or between the silicon vagina film 3 and the control electrode 5. One or both insulating films may not be formed.

<< Second Embodiment >>
13 and 10-2 are manufacturing process diagrams illustrating different examples of the manufacturing process of the XY memory array. In FIGS. 13 and 10-2, each drawing in the left column shows an XX ′ section, and each drawing in the right column shows a YY ′ section.

  In this embodiment, first, as shown in FIGS. 13A and 13B, trench element isolation regions 21a and 21b are formed on a semiconductor substrate 1 made of Si of a first conductivity type (here, p-type). After forming 21c, thermal oxidation is performed to form a fifth insulating film (gate insulating film) 9 having a thickness of about 5 to 15 nm, and then a polysilicon film 3 having a thickness of about 50 nm is sequentially deposited.

  Subsequently, a resist is applied on the polysilicon film 3 and then patterned using a lithography technique to form a resist pattern 31. Then, the portion of the polysilicon film 3 from which the resist 31 has been removed by patterning is removed by etching, and then the resist pattern 31 is peeled off. As a result, as shown in FIGS. 13C and 13D, the charge storage layers 3 separated in the X-X ′ direction and the Y-Y ′ direction are formed.

  Thereafter, a sixth insulating film 23 made of an oxide film and a polysilicon film to be the control electrode 5 are further deposited on the polysilicon film 3, and a resist is applied thereon, followed by patterning the resist using a lithography technique. A resist pattern 27 is formed. Then, the portion of the control electrode 5 where the resist 27 is removed by patterning is removed by etching, and then the resist pattern 27 is peeled off. Thus, as shown in FIGS. 13C and 13D, a plurality of control gates 5 extending along the Y-Y ′ direction are formed.

Next, the channel region for forming the auxiliary gate AG is covered with a resist 29, and ion implantation is performed to form the diffusion layers 9 and 11 (FIG. 13E).
Subsequently, polysilicon as the second electrode is deposited, and an auxiliary gate AG7 is embedded between the control gates CG1 and CG2 by an etch back technique (FIG. 13G).

  In addition to the above-described embodiments, it is apparent that there can be various modifications of the present invention. Such variations are not to be construed as not belonging to the features and scope of the invention. It will be apparent to those skilled in the art that such variations are intended to be included within the scope of the claims of this invention.

It is explanatory drawing which shows the typical cross-section of the serial memory array of this invention. It is explanatory drawing which shows the drive method in the case of performing reading of the selection memory cell in the serial memory array of this invention. It is explanatory drawing which shows the drive method in the case of writing in the selection memory cell in the serial memory array of this invention. It is explanatory drawing which shows an example of the drive method in the case of batch-erasing the memory cell in the serial memory array of this invention. It is explanatory drawing which shows an example of the drive method which selectively erases the memory cell C1 in the serial memory array of this invention. When erasing the selected cell C2 in the serial memory array of this invention, it is explanatory drawing which shows the drive conditions in the case of erasing C1 and C2 simultaneously. It is explanatory drawing which shows the structure of the XY memory array which contains multiple serial memory arrays of this invention, and the example of drive conditions. It is explanatory drawing which shows the example from which the structure of the XY memory array which contains multiple serial memory arrays of this invention, and a drive condition differ. It is explanatory drawing which shows the further different example of the structure of the XY memory array which contains multiple serial memory arrays of this invention, and a drive condition. 1 is a plan view showing a schematic structure of an XY memory array according to the present invention, and sectional views in X-X ′ and Y-Y ′ directions. It is a manufacturing process figure which shows the example of the process of manufacturing XY memory array based on this invention. (Part 1) It is a manufacturing process figure which shows the example of the process of manufacturing XY memory array based on this invention. (Part 2) It is a manufacturing process figure which shows the example from which the process of manufacturing XY memory array which concerns on this invention differs. (Part 1) It is a manufacturing process figure which shows the example from which the process of manufacturing XY memory array which concerns on this invention differs. (Part 2) It is explanatory drawing which shows an example of typical sectional structure of the conventional non-volatile memory. It is explanatory drawing which shows an example of the typical structure of the conventional NAND cell array.

Explanation of symbols

1, 101, 121 Semiconductor substrate 3, 3a, 3b, 3c, 3d, 3n Charge storage layer 5, 5a, 5b, 5c, 5d, 5n Control gate electrode 7, 7a, 7c, 7e, 7n Auxiliary gate electrode 9 1st Diffusion layer 10 Serial memory array 11 Second diffusion layer 13, 13a, 13c, 13n Diffusion layer 21a, 21b, 21c Trench element isolation region 22 First polysilicon film 23 Sixth insulating film 27, 29, 31 Resist pattern 109, 113 129, 133 Source diffusion layer 111, 131 Drain diffusion layer 115, 135 Bit line

Claims (37)

A semiconductor substrate in which a first diffusion layer and a second diffusion layer, which are two impurity diffusion layers, are disposed on a surface portion;
Two charge storage layers disposed in a region between the first diffusion layer and the second diffusion layer, wherein the first charge storage layer and the second insulation are disposed via the semiconductor substrate and the first insulating film. A second charge storage layer disposed through the film;
A first control gate electrode disposed adjacent to the first charge storage layer and capable of controlling the potential of the first charge storage layer;
A second control gate electrode disposed adjacent to the second charge storage layer and capable of controlling the potential of the second charge storage layer;
The first charge storage layer side and the first control gate electrode are arranged adjacent to the first control gate electrode and the second control gate electrode, and the auxiliary gate electrode is disposed through the semiconductor substrate and the third insulating film. A serially arranged memory device comprising one or more memory cell pairs each having two memory cells on the side of two charge storage layers.   The memory device according to claim 1, wherein the memory cell pairs adjacent to each other share the impurity diffusion layer. The first charge storage layer and the first control gate electrode are adjacent to each other through the fourth insulating film;
The memory device according to claim 1, wherein the second charge storage layer and the second control gate electrode are adjacent to each other via a fifth insulating film.   2. The memory device according to claim 1, wherein the first charge storage layer is adjacent to the auxiliary gate electrode via a sixth insulating film, and the second charge storage layer is adjacent to the auxiliary gate electrode via a seventh insulating film. . A first control gate electrode is disposed adjacent to and above the first charge storage layer;
The memory device according to claim 1, wherein the second control gate electrode is disposed adjacent to and above the second charge storage layer. An impurity diffusion layer shared with a memory cell pair at one end of the memory cell pair included in the memory device according to claim 1;
A third charge storage layer disposed in a region adjacent to the impurity diffusion layer via the semiconductor substrate and a third insulating film;
A third control gate electrode disposed adjacent to the third charge storage layer and capable of controlling the potential of the third charge storage layer;
A single memory cell, which is disposed adjacent to the third control gate and includes the semiconductor substrate and an auxiliary gate electrode disposed via an eighth insulating film, is arranged in series at one or both ends of the memory cell pair. A serially arranged memory device characterized by comprising: A method for reading a selected memory cell in the memory cell pair disposed in the memory device according to claim 1,
Using the first diffusion layer of the memory cell pair arranged at the end of the first diffusion layer side as a source,
Applying a voltage capable of causing a channel current to flow to the source to the second diffusion layer of the memory cell pair disposed at the end on the second diffusion layer side, to form a drain,
A voltage is applied to the auxiliary gate electrode of all memory cells so as to extend the source or the drain,
A voltage higher than a threshold voltage is applied to the control gate electrode of an unselected memory cell so as to extend the source or the drain,
A method of applying a voltage capable of controlling a channel current to a control gate electrode of a selected memory cell in accordance with a charge in a charge storage layer of the selected memory cell.   8. The method according to claim 7, wherein the same voltage is applied to each control gate electrode of an unselected memory cell.   8. The method of claim 7, wherein the same voltage is applied to each auxiliary gate electrode shared between unselected memory cells.   8. The read method according to claim 7, wherein a voltage lower than an applied voltage of each control gate electrode on the second diffusion layer side than the selected memory cell is applied to each control gate electrode on the first diffusion layer side than the selected memory cell. .   In each auxiliary gate electrode shared between non-selected memory cells, a voltage lower than the applied voltage of each auxiliary gate electrode on the second diffusion layer side than the selected memory cell is set to the first diffusion layer side than the selected memory cell. The readout method according to claim 7, wherein the readout is applied to each auxiliary gate electrode. A method for writing to a selected memory cell arranged on the first diffusion layer side in the memory cell pair arranged in the memory device according to claim 1,
Using the second diffusion layer of the memory cell pair arranged at the end on the second diffusion layer side as a source,
Applying a write voltage to the first diffusion layer of the memory cell pair arranged at the end on the first diffusion layer side to form a drain;
A voltage is applied to each control gate electrode of an unselected memory cell so as to extend the source or the drain,
A voltage is applied to each auxiliary gate electrode shared between unselected memory cells so as to extend the source or the drain,
A voltage for injecting charges into the charge storage layer of the selected memory cell is applied to the control gate electrode of the selected memory cell,
A method of applying a voltage about the threshold voltage to the auxiliary gate electrode of the selected memory cell.   13. The writing method according to claim 12, wherein the same voltage is applied to each control gate electrode of an unselected memory cell.   13. The writing method according to claim 12, wherein the same voltage is applied to each auxiliary gate electrode shared between unselected memory cells.   13. The writing method according to claim 12, wherein a voltage higher than a voltage applied to each control gate electrode on the second diffusion layer side than the selected memory cell is applied to each control gate electrode on the first diffusion layer side relative to the selected memory cell. .   In each auxiliary gate electrode shared between unselected memory cells, a voltage higher than the applied voltage of each auxiliary gate electrode on the second diffusion layer side than the selected memory cell is set on the first diffusion layer side than the selected memory cell. The writing method according to claim 12, wherein the writing is applied to each auxiliary gate electrode. A method for writing to a selected memory cell arranged on the second diffusion layer side in the memory cell pair arranged in the memory device according to claim 1,
Using the first diffusion layer of the memory cell pair arranged at the end of the first diffusion layer side as a source,
A write voltage is applied to the second diffusion layer of the memory cell pair disposed at the end on the second diffusion layer side to form a drain,
A voltage is applied to each control gate electrode of an unselected memory cell so as to extend the source or the drain,
A voltage is applied to each auxiliary gate electrode shared between unselected memory cells so as to extend the source or the drain,
A voltage for injecting charges into the charge storage layer of the selected memory cell is applied to the control gate electrode of the selected memory cell,
A method of applying a voltage about the threshold voltage to the auxiliary gate electrode of the selected memory cell. An erasing method for collectively erasing memory cells in the memory cell pair arranged in the memory device according to claim 1,
A method in which a positive voltage is applied to the semiconductor substrate with respect to each control gate electrode to extract electrons from each charge storage layer to the semiconductor substrate.   19. The erasing method according to claim 18, wherein each control gate electrode is grounded.   19. The erase method according to claim 18, wherein a negative bias voltage is applied to each control gate electrode.   19. The erasing method according to claim 18, wherein a positive bias voltage is applied to each control gate electrode.   19. The erasing method according to claim 18, wherein each auxiliary gate electrode is grounded or a negative voltage is applied. An erasing method for erasing selected memory cells on the first diffusion layer side in the memory cell pair arranged in the memory device according to claim 1,
Applying a voltage for extracting electrons from the charge storage layer of the selected memory cell to the first diffusion layer of the memory cell pair disposed at the end of the first diffusion layer side to form a drain;
A voltage higher than a threshold voltage is applied so as to extend the drain to the control gate electrode on the drain side of the selected memory cell;
A voltage is applied to extend the drain from the selected memory cell to the auxiliary gate electrode on the drain side,
A method of applying a voltage for extracting electrons from the charge storage layer to the semiconductor substrate to a control gate electrode of a selected memory cell.   The erase method according to claim 23, wherein the auxiliary gate electrode of the selected memory cell is grounded or a negative voltage is applied. An erasing method for erasing a selected memory cell on the second diffusion layer side in the memory cell pair arranged in the memory device according to claim 1,
A voltage for extracting electrons from the charge storage layer of the selected memory cell is applied to the second diffusion layer of the memory cell pair disposed at the end on the second diffusion layer side to form a drain,
Applying a voltage higher than a threshold voltage to extend the drain to the control gate electrode of the memory cell on the drain side than the selected memory cell,
A voltage is applied so as to extend the drain to the auxiliary gate electrode of the memory cell on the drain side from the selected memory cell,
A method of applying a voltage for extracting electrons from the charge storage layer to the semiconductor substrate to a control gate electrode of a selected memory cell. An erasing method for erasing a selected memory cell on one side of the memory cell pair arranged in the memory device according to claim 1,
A voltage for supplying holes to the charge storage layer of the selected memory cell is applied to the diffusion layer on one end of the memory device;
A voltage higher than a threshold voltage is applied to the control gate electrode on one side of the selected memory cell so as to extend the potential of the diffusion layer on the one side end,
A voltage is applied to the auxiliary gate electrode on the one side from the selected memory cell so as to extend the potential of the diffusion layer on the one side,
A method of applying a voltage for injecting holes into the charge storage layer of the memory cell to the control gate electrode of the selected memory cell.   27. The erasing method according to claim 26, wherein the auxiliary gate electrode of the selected memory cell is grounded or a negative voltage is applied. A memory cell on a first diffusion layer side and a second diffusion layer side included in a selected memory cell pair among the memory cell pairs arranged in the memory device according to claim 1. A method of batch erasing,
Applying a first voltage for extracting electrons from the charge storage layer on the first diffusion layer side of the selected memory cell pair to the first diffusion layer of the memory cell pair disposed on the end of the first diffusion layer side;
Applying a second voltage for extracting electrons from the charge storage layer on the second diffusion layer side of the selected memory cell pair to the second diffusion layer of the memory cell pair disposed on the end of the second diffusion layer side;
A voltage higher than a threshold voltage is applied to the control gate electrode of the unselected memory cell pair so as to extend the potential of the first diffusion layer to which the first voltage is applied or the second diffusion layer to which the second voltage is applied,
A voltage is applied to the auxiliary gate electrode of the unselected memory cell pair so as to extend the potential of the first diffusion layer to which the first voltage is applied or the second diffusion layer to which the voltage is applied,
A method of applying a voltage for extracting the charge of each charge storage layer to the semiconductor substrate to each control gate electrode of the selected memory cell pair. When performing sequential writing and verify reading to each memory cell of the plurality of memory cell pairs in the memory device according to claim 1,
A method of performing writing or verify reading sequentially from the memory cells on the first diffusion layer side. When sequentially performing erase and verify read on each memory cell of the plurality of memory cell pairs in the memory device according to claim 1,
A method of performing erasing or verify reading sequentially from the memory cells on the first diffusion layer side. Comprising a plurality of memory devices according to claim 1 or 6;
Each memory cell of the memory device is arranged in series in the X direction,
A common first control gate line in which first control gate electrodes of memory cells included in the memory devices different from each other in the Y direction different from the X direction are connected to each other;
A common second control gate line in which second control gate electrodes of memory cells included in the memory devices different from each other in the Y direction different from the X direction are connected to each other;
A matrix-arranged memory device comprising: a common auxiliary gate line in which auxiliary gate electrodes of memory cells included in the memory devices different from each other in the Y direction different from the X direction are connected to each other. A plurality of serially arranged memory devices according to any one of claims 1 to 6;
A select transistor having a select gate, the select transistor being arranged corresponding to the second diffusion layer of the memory cell pair arranged at the second diffusion layer side end of each serially arranged memory device;
One bit line connected to each second diffusion layer of the memory cell pair at the end on the second diffusion layer side via a corresponding selection transistor;
One or more source lines connecting the first diffusion layers of the memory cell pairs arranged at the first diffusion layer side end of each serially arranged memory device and the corresponding auxiliary gates of each serially arranged memory device are respectively connected. A common auxiliary gate line;
A matrix-arranged memory device configured as a unit of a serially-arranged memory unit including at least one common control gate line to which a corresponding control gate of each serially-arranged memory device is connected 33. When writing to a selected memory cell on the second diffusion layer side of a memory cell pair in a serially arranged memory unit of a memory device according to claim 32, writing to an unselected memory cell of another serially arranged memory device A method of blocking writing,
The source line is grounded to function as a source,
A connection voltage for turning on the selection transistor is applied to a selection gate of the selection transistor corresponding to the serially arranged memory device including the selection memory cell, and connected to the bit line;
When writing by applying a write voltage to the bit line to function as a drain,
A method of preventing writing to an unselected memory cell by applying a voltage for turning off the selection transistor to a selection gate of another selection transistor other than the selection transistor to which the connection voltage is applied to the selection gate. 33. When writing to a selected memory cell on the first diffusion layer side of a memory cell pair in a serially arranged memory unit of the memory device according to claim 32, writing to an unselected memory cell of another serially arranged memory device A method of blocking writing,
Applying a voltage for turning on the selection transistor to the selection gate of the selection transistor corresponding to the serially arranged memory device including the selection memory cell, and connecting to the bit line,
Ground the bit line to function as a source,
When writing by applying a write voltage to the source line to function as a drain,
A method of preventing writing to an unselected memory cell by grounding a source line other than the source line to which the write voltage is applied. A plurality of serially arranged memory devices according to any one of claims 1 to 6;
One bit line for connecting the second diffusion layers of the memory cell pair disposed at the end of the serially arranged memory device on the second diffusion layer side;
A plurality of source lines respectively connected corresponding to the first diffusion layer of the memory cell pair disposed on the first diffusion layer side end of each serially arranged memory device;
One or more common auxiliary gate lines to which one auxiliary gate of each serially arranged memory device is connected to each other;
A matrix-arranged memory device configured in units of a serially-arranged memory unit including one or more common control gate lines to which one control gate of each serially-arranged memory device is connected. 36. When writing to a selected memory cell on the second diffusion layer side of a memory cell pair in the serially arranged memory unit of the memory device according to claim 35, writing to an unselected memory cell of another serially arranged memory device A method of blocking writing,
The source line of the serially arranged memory device including the selected memory cell is grounded as a source,
When writing as a drain by applying a write voltage to the bit line,
A method of applying a voltage as a counter bias to a source line other than the grounded source line to prevent writing to an unselected memory cell. 36. When writing to a selected memory cell on the first diffusion layer side of a memory cell pair in a serially arranged memory unit of a memory device according to claim 35, writing to an unselected memory cell of another serially arranged memory device A method of blocking writing,
Ground the bit line as the source,
When writing as a drain by applying a write voltage to the source line of a serially arranged memory device including a selected memory cell,
A method of preventing writing to an unselected memory cell by grounding a source line other than the source line to which the write voltage is applied.