JP2007123504A - Electronic component and semiconductor device - Google Patents

Electronic component and semiconductor device Download PDF

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JP2007123504A
JP2007123504A JP2005312901A JP2005312901A JP2007123504A JP 2007123504 A JP2007123504 A JP 2007123504A JP 2005312901 A JP2005312901 A JP 2005312901A JP 2005312901 A JP2005312901 A JP 2005312901A JP 2007123504 A JP2007123504 A JP 2007123504A
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electronic component
dielectric film
substrate
chip
power supply
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JP4816896B2 (en
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Katsuhiko Hayashi
克彦 林
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TDK Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H01L2224/16267—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive

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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component to be held between a package substrate and an IC chip, having a structure capable of evading dielectric coupling between signal terminals and reducing a waveform distortion, and to provide a semiconductor device using the component. <P>SOLUTION: A dielectric film 9a and vertical conductive films 21, 23 constituting a capacitor are formed between a positive power source terminal 17 and a ground power source terminal 18 which are arranged on a surface at the side of the IC chip in the substrate 3a of the electronic component. Regions 13 without a dielectric film 9b formed thereon are arranged in the circumference of the signal terminals 19 arranged on the surface at the side of the IC chip in the substrate 3a. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、パッケージ基板とＩＣチップとの間に介装され、ＩＣチップ側表面に電源ラインの電圧を安定化させるコンデンサ、いわゆるデカップリングコンデンサを形成したインターポーザと称される電子部品に係わり、特に誘電体膜の形成構造に関する。   The present invention relates to an electronic component called an interposer which is interposed between a package substrate and an IC chip and which has a capacitor for stabilizing the voltage of a power supply line on the IC chip side surface, a so-called decoupling capacitor. The present invention relates to a structure for forming a dielectric film.

多層回路基板等からなるパッケージ基板上にＣＰＵ用等のＩＣチップを搭載した電子部品において、パッケージ基板からＩＣチップへの電源ラインの電圧を安定化させるため、従来は基板と別に設けたコンデンサをパッケージ基板の表面や側面に取付けて供給電圧の安定化を行なっていた。しかしながら、この構造では、ＩＣチップとコンデンサとの距離が大きくなり、近年の高速ＣＰＵでは、高速化に伴う電圧変動の高速化に対して十分に機能させることができないという不具合がある。この不具合を解決するため、特許文献１では、パッケージ基板とＩＣチップとの間に、電圧安定化のためのコンデンサ、いわゆるデカップリングコンデンサを含むインターポーザと称される電子部品をサンドイッチ状に介在させて構成したものが開示されている。   In an electronic component in which an IC chip for a CPU or the like is mounted on a package substrate composed of a multilayer circuit substrate or the like, in order to stabilize the voltage of the power line from the package substrate to the IC chip, conventionally, a capacitor provided separately from the substrate is packaged. It was mounted on the surface or side of the substrate to stabilize the supply voltage. However, with this structure, the distance between the IC chip and the capacitor is increased, and a recent high-speed CPU has a problem that it cannot function sufficiently for increasing the voltage fluctuation accompanying the increase in speed. In order to solve this problem, in Patent Document 1, an electronic component called an interposer including a capacitor for voltage stabilization, a so-called decoupling capacitor, is sandwiched between a package substrate and an IC chip. What has been configured is disclosed.

前記電子部品を構成する場合、図６の断面図と図７の斜視図に示すように、コンデンサが形成される。図６、図７において、４０は電子部品（インターポーザ）の基板であり、この基板４０には、パッケージ基板やＩＣチップ（いずれも図示せず）の正極電源端子とグランド電源端子に両端がそれぞれ接続されるスルーホール導体４１、４２と、パッケージ基板やＩＣチップの信号端子（データ端子を含む）にそれぞれ接続されるスルーホール導体４３が形成される。   When the electronic component is configured, a capacitor is formed as shown in the sectional view of FIG. 6 and the perspective view of FIG. 6 and 7, reference numeral 40 denotes a substrate for an electronic component (interposer). Both ends of the substrate 40 are connected to a positive power supply terminal and a ground power supply terminal of a package substrate and an IC chip (both not shown), respectively. Through-hole conductors 41 and 42 and through-hole conductors 43 connected to signal terminals (including data terminals) of the package substrate and the IC chip are formed.

また、電子部品の基板４０のＩＣチップ側の表面には、前記スルーホール導体４１（または４２）に導通するように下部導体膜４４を形成し、その上に図７に示すように基板全面にわたって誘電体膜４５を形成し、さらにその上に前記スルーホール導体４２（または４１）に導通させて上部導体膜４６を形成し、これらによりコンデンサを構成する。この場合、図７に示すように、誘電体膜４５を全面に形成していた。４７は保護膜である。   Further, a lower conductor film 44 is formed on the surface of the electronic component substrate 40 on the IC chip side so as to be electrically connected to the through-hole conductor 41 (or 42), and on the entire surface of the substrate as shown in FIG. A dielectric film 45 is formed, and an upper conductor film 46 is formed on the dielectric film 45 to be conducted to the through-hole conductor 42 (or 41) thereon, thereby constituting a capacitor. In this case, as shown in FIG. 7, the dielectric film 45 is formed on the entire surface. 47 is a protective film.

特開２００１−３２６３０５号公報JP 2001-326305 A

前記電子部品基板４０上に搭載されるＩＣチップがＣＰＵを構成するものである場合、パッケージ基板やＩＣチップが有する外部接続用端子は、駆動用の電源とデータをやりとりするための端子であって、その総数が数千に上る場合がある。しかしその９０％が電源用（正極側とグランドとの対）端子である。この電子部品には下記のような問題点がある。   When the IC chip mounted on the electronic component substrate 40 constitutes a CPU, the external connection terminals of the package substrate and the IC chip are terminals for exchanging data with the driving power source. , The total number may be in the thousands. However, 90% of the terminals are terminals for power supply (a pair of positive electrode side and ground). This electronic component has the following problems.

図６、図７に示すコンデンサの誘電体膜４５はスパッタリング法あるいはゾルゲル法等の薄膜形成技術を用いて、電子部品基板４０の全面に形成される。そのため、ＩＣ駆動用の電源用にコンデンサを形成する方法としては好ましい方法であった。しかしながら、スルーホール導体４３のＩＣチップ側の信号端子４８は、複数本のデータラインをまとめた形（データバス）で信号の入出力を行なうため、隣り合う信号端子４８、４８間にとっては、高誘電率系の構成材料である誘電体膜４５により端子４８、４８間の誘電結合を起こすため、前記誘電体膜４５が信号端子４８、４８の周囲まで形成されることは好ましくなかった。   The capacitor dielectric film 45 shown in FIGS. 6 and 7 is formed on the entire surface of the electronic component substrate 40 by using a thin film forming technique such as sputtering or sol-gel. Therefore, this is a preferable method for forming a capacitor for a power source for driving an IC. However, since the signal terminal 48 on the IC chip side of the through-hole conductor 43 performs input / output of signals in a form in which a plurality of data lines are collected (data bus), it is difficult to connect the signal terminals 48, 48 adjacent to each other. Since the dielectric film 45, which is a dielectric material, causes dielectric coupling between the terminals 48 and 48, it is not preferable that the dielectric film 45 is formed to the periphery of the signal terminals 48 and 48.

また、各信号端子４８はホット端子とグランド端子に相当するコールド端子とが対をなして設けられるが、これらのホット端子とコールド端子間をとってみても、誘電体膜４５が存在することは、ホット端子とコールド端子間の容量が大きくなることになり、信号端子の伝送路のインピーダンスを低下させることになるため、通過するデジタル信号（矩形波）を歪ませる原因になりやすかった。   Each signal terminal 48 is provided with a pair of a hot terminal and a cold terminal corresponding to the ground terminal. Even when these hot terminals and the cold terminals are taken, the dielectric film 45 is present. Since the capacity between the hot terminal and the cold terminal is increased and the impedance of the transmission path of the signal terminal is lowered, the digital signal (rectangular wave) passing therethrough is likely to be distorted.

さらに、近年のＣＰＵの性能向上は著しく、ＩＣチップの外部接続端子の数は増え、一方、ＩＣチップの形状は維持される傾向にあるため、前記外部接続端子間のピッチは狭くなってきている。そのため、信号端子４８、４８間の距離も近づく傾向にあり、さらにクロック信号の高速化も急激であるため、前記誘電体膜４５による構造は、信号端子にとっては極めて好ましくない構造となっていた。   Further, the performance of CPUs in recent years has been remarkably improved, and the number of external connection terminals of IC chips has increased. On the other hand, since the shape of IC chips tends to be maintained, the pitch between the external connection terminals has become narrower. . For this reason, the distance between the signal terminals 48 and 48 tends to be closer, and the speed of the clock signal is rapidly increased. Therefore, the structure using the dielectric film 45 is extremely undesirable for the signal terminal.

本発明は、上記問題点に鑑み、パッケージ基板とＩＣチップとの間に介装される電子部品において、信号端子間の誘電結合を回避することができ、かつ信号の波形歪を低減することができる構造の電子部品とこれを用いた半導体装置を提供することを目的とする。また、本発明は、誘電体膜を電子部品基板の全面に設けなくても、電子部品の信号端子の高さを、電源端子の高さと同一にすることができ、ＩＣチップとの接続を安定的に行える構造の電子部品とこれを用いた半導体装置を提供することを目的とする。   In view of the above problems, the present invention can avoid dielectric coupling between signal terminals and reduce signal waveform distortion in an electronic component interposed between a package substrate and an IC chip. An object of the present invention is to provide an electronic component having a structure and a semiconductor device using the electronic component. Further, according to the present invention, the height of the signal terminal of the electronic component can be made the same as the height of the power supply terminal without providing the dielectric film on the entire surface of the electronic component substrate, and the connection with the IC chip is stabilized It is an object of the present invention to provide an electronic component having a structure that can be performed automatically and a semiconductor device using the same.

（１）本発明の電子部品は、パッケージ基板とＩＣチップとの間に介装される電子部品であって、
前記電子部品の基板に、前記パッケージ基板と前記ＩＣチップにそれぞれ備えられた正極電源端子、グランド電源端子および信号端子どうしをそれぞれ接続する内蔵導体および電子部品の基板の両面に設けられた正極電源端子、グランド電源端子および信号端子とを有し、
前記電子部品の基板のＩＣチップ側の面に設けられた正極電源端子とグランド電源端子の間に、コンデンサを構成する誘電体膜および上下の導体膜を形成し、
前記電子部品の基板のＩＣチップ側の面に設けられた信号端子の周囲に、前記誘電体膜が形成されていない領域を設けたことを特徴とする。 (1) An electronic component of the present invention is an electronic component interposed between a package substrate and an IC chip,
A positive power supply terminal provided on both surfaces of the substrate of the electronic component, a built-in conductor for connecting the positive power supply terminal, the ground power supply terminal, and the signal terminal provided in the package substrate and the IC chip, respectively, and the electronic component substrate, respectively. A ground power supply terminal and a signal terminal,
Between the positive power supply terminal and the ground power supply terminal provided on the IC chip side surface of the substrate of the electronic component, a dielectric film and upper and lower conductive films constituting a capacitor are formed,
A region where the dielectric film is not formed is provided around a signal terminal provided on the surface of the substrate of the electronic component on the IC chip side.

（２）また、本発明の電子部品は、前記（１）に記載の電子部品において、
前記電子部品のＩＣチップ側信号端子の周囲に、前記誘電体膜を環状に形成したことを特徴とする。 (2) Moreover, the electronic component of the present invention is the electronic component according to (1),
The dielectric film is formed in an annular shape around an IC chip side signal terminal of the electronic component.

（３）また、本発明の電子部品は、前記（２）に記載の電子部品において、
前記環状に残した誘電体膜の周囲に、誘電体膜を形成していない領域を環状に設けたことを特徴とする。 (3) Moreover, the electronic component of the present invention is the electronic component according to (2),
A region where no dielectric film is formed is provided in a ring shape around the ring-shaped dielectric film.

（４）本発明の半導体装置は、前記（１）から（３）までのいずれかに記載の電子部品と、該電子部品を挟むように設けたパッケージ基板およびＩＣチップからなることを特徴とする。   (4) A semiconductor device according to the present invention includes the electronic component according to any one of (1) to (3) above, and a package substrate and an IC chip provided so as to sandwich the electronic component. .

本発明においては、パッケージ基板とＩＣチップ間に介在させる電子部品における信号端子間に、誘電体膜が形成されていない領域を設けたので、信号端子間の誘電結合を回避することができる。また、誘電体膜が形成されていない領域を設けたので、信号端子の対をなすホット端子とコールド端子間の容量が低下し、信号の波形歪みを低下させることができる。このため、近年における端子間の高密度配置と高速化に対応できる。   In the present invention, since the region where the dielectric film is not formed is provided between the signal terminals in the electronic component interposed between the package substrate and the IC chip, dielectric coupling between the signal terminals can be avoided. Further, since the region where the dielectric film is not formed is provided, the capacitance between the hot terminal and the cold terminal forming a pair of signal terminals is reduced, and the waveform distortion of the signal can be reduced. For this reason, it is possible to cope with high-density arrangement and high speed between terminals in recent years.

また、前記誘電体膜を環状に残して、電子部品の電源端子と信号端子の高さを等しくしたので、ＩＣチップと電子部品との接続を安定化させることが可能となる。   Further, the height of the power supply terminal and the signal terminal of the electronic component is made equal by leaving the dielectric film in a ring shape, so that the connection between the IC chip and the electronic component can be stabilized.

図１は本発明による電子部品の一実施の形態を示す側面図である。１はＩＣパッケージとして用いられるパッケージ基板、２は例えばＣＰＵとして構成されたＩＣチップ、３はインターポーザとして用いられる電子部品、４はパッケージ基板１と電子部品３の対応する端子間を接続するバンプ、５は電子部品３とＩＣチップ２の対応する端子どうしを接続するためのバンプである。前記パッケージ基板１は、樹脂製基板内に配線を内蔵したもので、マザー基板（図示せず）に接続される端子１ａに対し、電子部品３に対する接続回路の総数を増加させた（例えば端子１ａの数約５００本に対し、電子部品３側に対向する面に接続端子を約５０００本設けた）ものである。   FIG. 1 is a side view showing an embodiment of an electronic component according to the present invention. 1 is a package substrate used as an IC package, 2 is an IC chip configured as a CPU, for example, 3 is an electronic component used as an interposer, 4 is a bump for connecting between corresponding terminals of the package substrate 1 and the electronic component 3, 5 These are bumps for connecting corresponding terminals of the electronic component 3 and the IC chip 2. The package substrate 1 includes a wiring in a resin substrate, and the total number of connection circuits for the electronic component 3 is increased with respect to the terminal 1a connected to the mother substrate (not shown) (for example, the terminal 1a). The number of connection terminals is about 5000 on the surface facing the electronic component 3 side.

図２は前記電子部品３の基板３ａに形成されるコンデンサ形成のための誘電体膜の配置を示す斜視図である。該基板３ａは、セラミックスやシリコン等の無機材料からなる。７は電源端子形成領域、８は信号端子（データ端子を含む。）形成領域である。電源端子形成領域７においては、誘電体膜９ａは領域全面（ただし後述の第１、第２のスルーホール導体１０、１１につながる端子形成部分は除く。）に形成される。一方、信号端子形成領域８においては、誘電体膜９ｂは後述の第３のスルーホール導体１２の形成部分のＩＣチップ側端部の周囲のみ環状に形成され、さらにその周囲に誘電体膜９ｂを形成していない領域１３が環状に囲んでいる。なお、ここで、誘電体膜とは、比誘電率が２００以上（好ましくは３００以上）の比較的高い比誘電率を有する膜を意味する。   FIG. 2 is a perspective view showing the arrangement of dielectric films for forming capacitors formed on the substrate 3a of the electronic component 3. As shown in FIG. The substrate 3a is made of an inorganic material such as ceramics or silicon. Reference numeral 7 denotes a power supply terminal formation region, and reference numeral 8 denotes a signal terminal (including data terminal) formation region. In the power supply terminal formation region 7, the dielectric film 9a is formed on the entire surface of the region (however, excluding terminal formation portions connected to first and second through-hole conductors 10 and 11 described later). On the other hand, in the signal terminal formation region 8, the dielectric film 9b is formed in an annular shape only around the end portion of the IC chip side of the formation portion of the third through-hole conductor 12 to be described later, and further the dielectric film 9b is formed around the dielectric film 9b. The area | region 13 which is not formed encloses cyclically | annularly. Here, the dielectric film means a film having a relatively high relative dielectric constant having a relative dielectric constant of 200 or more (preferably 300 or more).

図３は電子部品３の断面図である。該基板３ａには、スルーホールの内壁に導体をメッキするかあるいは導体を充填することにより形成された第１、第２、第３のスルーホール導体１０、１１、１２が形成される。   FIG. 3 is a cross-sectional view of the electronic component 3. The substrate 3a is formed with first, second, and third through-hole conductors 10, 11, and 12 formed by plating or filling a conductor on the inner wall of the through-hole.

図３において、下側がパッケージ基板１に接続される面で、端子１４、１５、１６はそれぞれ前記バンプ４によりパッケージ基板１に接続される正極電源端子、グランド電源端子、信号端子となる。また、１７、１８、１９はそれぞれＩＣチップ２に前記バンプ５により接続される正極電源端子、グランド電源端子、信号端子となる。なおこれらの端子１４〜１９には半田層が蒸着等により被着される。   In FIG. 3, the lower side is a surface connected to the package substrate 1, and the terminals 14, 15, and 16 become a positive power supply terminal, a ground power supply terminal, and a signal terminal connected to the package substrate 1 by the bumps 4, respectively. Reference numerals 17, 18 and 19 denote a positive power supply terminal, a ground power supply terminal, and a signal terminal connected to the IC chip 2 by the bumps 5, respectively. A solder layer is deposited on these terminals 14 to 19 by vapor deposition or the like.

２０、２１、２２はそれぞれ前記基板３ａの上面における前記第１、第２、第３のスルーホール導体１０、１１、１２の周囲にそれぞれこれらに接続して形成された下部導体膜である。９ａはコンデンサ構成用の誘電体膜である。該誘電体膜９ａは、前記第２のスルーホール導体１１に接続して形成された下部導体膜２１上に形成される。９ｂは前記信号端子１９の下の下部導体膜２２の周囲に内周部を重ねて、信号端子１９を包囲するように環状に形成された誘電体膜である。該誘電体膜９ｂの周囲に、図２に示したように、誘電体膜９ｂが形成されていない領域１３が環状に形成される。   Reference numerals 20, 21, and 22 denote lower conductor films formed around the first, second, and third through-hole conductors 10, 11, and 12 on the upper surface of the substrate 3 a, respectively. Reference numeral 9a denotes a dielectric film for capacitor construction. The dielectric film 9 a is formed on the lower conductor film 21 formed in connection with the second through-hole conductor 11. Reference numeral 9 b denotes a dielectric film formed in an annular shape so as to surround the signal terminal 19 with the inner peripheral portion being overlapped around the lower conductor film 22 below the signal terminal 19. As shown in FIG. 2, a region 13 where the dielectric film 9b is not formed is formed in an annular shape around the dielectric film 9b.

２３は前記下部導体膜２１と誘電体膜９ｂとによりコンデンサを構成する上部導体膜である。該上部導体膜２３は第１のスルーホール導体１０上に相当する部分で前記正極電源端子１７を構成する。２４は下部導体膜２１上の第２のスルーホール導体１１上の部分に重ねて形成された上部導体膜であり、前記グランド電源端子１８を構成するものである。２５は前記信号端子１９を形成するために、前記第３のスルーホール導体１２上の下部導体膜２２上および誘電体膜９ｂ上に形成した上部導体膜である。   Reference numeral 23 denotes an upper conductor film constituting a capacitor by the lower conductor film 21 and the dielectric film 9b. The upper conductor film 23 constitutes the positive power supply terminal 17 at a portion corresponding to the first through-hole conductor 10. Reference numeral 24 denotes an upper conductor film formed on the second through-hole conductor 11 on the lower conductor film 21 so as to constitute the ground power supply terminal 18. Reference numeral 25 denotes an upper conductor film formed on the lower conductor film 22 and the dielectric film 9b on the third through-hole conductor 12 in order to form the signal terminal 19.

２６は電子部品基板３ａの誘電体膜９ｂを形成しない領域等の保護および露出した電極などを保護する目的で表面に形成された保護膜である。この保護膜２６は、シリカ、アルミナ等の無機材料、またはエポキシ、ポリイミド等の有機材料等の低誘電率材料を用いて形成される。   Reference numeral 26 denotes a protective film formed on the surface for the purpose of protecting an area where the dielectric film 9b of the electronic component substrate 3a is not formed and protecting exposed electrodes. The protective film 26 is formed using an inorganic material such as silica or alumina, or a low dielectric constant material such as an organic material such as epoxy or polyimide.

図４、図５は本実施の形態の電子部品３の製造工程を示す図である。以下これらの図により製造工程を説明する。   4 and 5 are diagrams showing a manufacturing process of the electronic component 3 according to the present embodiment. The manufacturing process will be described below with reference to these drawings.

（下部導体膜の形成）
まず、図４（Ａ）に示すように、スルーホール導体１０〜１２を設けた基板３ａの上面に、前記下部導体膜２０〜２２を形成するための導体膜３０を形成する。この導体膜３０の材質としては、導電性の材料であればいかなるものでもよいが、図４（Ｃ）に示す後述の誘電体膜３１形成の際に、酸化雰囲気で熱処理されるため、少なくとも耐酸化性の金、白金が好ましい。導体膜３０の形成は、スパッタリング法のような薄膜形成法や、有機金属化合物である金レジネートを塗布後、熱処理して有機成分を分解する等の厚膜形成法等が用いられる。 (Formation of lower conductor film)
First, as shown in FIG. 4A, a conductor film 30 for forming the lower conductor films 20-22 is formed on the upper surface of the substrate 3a provided with the through-hole conductors 10-12. Any material may be used for the conductor film 30 as long as it is a conductive material. However, since the heat treatment is performed in an oxidizing atmosphere when the dielectric film 31 described later shown in FIG. Chemical gold and platinum are preferred. The conductor film 30 is formed by a thin film formation method such as sputtering, or a thick film formation method such as applying a gold resinate, which is an organometallic compound, followed by heat treatment to decompose organic components.

（導体膜パターニング）
下部導体膜２０〜２２を形成するため、前記導体膜３０上にフォトリソグラフィ技術によりエッチングレジストパターンを形成し、ドライエッチング等によりエッチングを行い、図４（Ｂ）に示すように、コンデンサを構成するための前記下部導体膜２１を、スルーホール導体１１と接続した状態で、第１のスルーホール導体１０の周囲の部分を除いて略全面に形成する。同時に、正極電源端子と信号端子に接続されるスルーホール導体１０、１２に対しては、その上にそのまま下部導体膜２０、２２が重なった状態でパターニングを行なう。これにより、各スルーホール導体１０〜１２上の導体膜の高さは同一となる。 (Conductor film patterning)
In order to form the lower conductor films 20 to 22, an etching resist pattern is formed on the conductor film 30 by a photolithography technique, and etching is performed by dry etching or the like to constitute a capacitor as shown in FIG. The lower conductor film 21 is formed on substantially the entire surface except for a portion around the first through-hole conductor 10 in a state of being connected to the through-hole conductor 11. At the same time, the through-hole conductors 10 and 12 connected to the positive power supply terminal and the signal terminal are patterned in a state in which the lower conductor films 20 and 22 are superimposed on the through-hole conductors 10 and 12 as they are. Thereby, the height of the conductor film on each through-hole conductor 10-10 becomes the same.

（誘電体膜形成）
図４（Ｃ）に示すように、次に誘電体膜３１の形成を行う。この誘電体膜３１の形成方法としては、ＭＯＤ（メタル・オーガニック・デコンポジション）法等の溶液法や、スパッタリング法等が利用できる。誘電体膜３１の材料は特に限定されず、例えばＢａＳｒＴｉＯ３以外にＢｉ層状化合物、またはＢａＴｉＯ３、ＳｒＴｉＯ３あるいはこれらに他の金属を添加したり、置換した化合物等で、前記比誘電率が得られるものが好ましい。 (Dielectric film formation)
Next, as shown in FIG. 4C, a dielectric film 31 is formed. As a method of forming the dielectric film 31, a solution method such as a MOD (metal organic organic composition) method, a sputtering method, or the like can be used. The material of the dielectric film 31 is not particularly limited. For example, a Bi layer compound other than BaSrTiO 3 , BaTiO 3 , SrTiO 3 , or a compound obtained by adding or substituting another metal to these, the relative dielectric constant can be obtained. Are preferred.

（誘電体膜パターニング）
前記誘電体膜３１上にフォトリソグラフィ技術によりエッチングレジストパターンを形成し、ドライエッチング等により図４（Ｄ）に示すようにエッチングを行ない、コンデンサを構成するための誘電体膜９ａの形成と、信号端子１９の下の環状の誘電体膜９ｂの形成を行う。また、このとき、同時に、前記誘電体膜９ｂを形成していない領域１３を形成する。また、スルーホール導体１０、１１上の下部導体膜２０、２１については、端子１７、１８を形成するためにスルーホール導体１０、１１の上に相当する下部導体膜２０、２１上の部分３２、３３を露出させる。 (Dielectric film patterning)
An etching resist pattern is formed on the dielectric film 31 by a photolithography technique, and etching is performed as shown in FIG. 4D by dry etching or the like to form a dielectric film 9a for constituting a capacitor, An annular dielectric film 9b under the terminal 19 is formed. At the same time, a region 13 where the dielectric film 9b is not formed is formed. Further, for the lower conductor films 20 and 21 on the through-hole conductors 10 and 11, a portion 32 on the lower conductor films 20 and 21 corresponding to the through-hole conductors 10 and 11 to form the terminals 17 and 18, 33 is exposed.

（上部導体膜形成）
図５（Ａ）に示すように、前記下部導体膜形成について述べた方法、材料を用いて、上部導体膜３４を形成する。 (Upper conductor film formation)
As shown in FIG. 5A, the upper conductor film 34 is formed using the method and material described for the formation of the lower conductor film.

（導体膜パターニング）
前記下部導体膜形成の場合と同様に、フォトリソグラフィ技術によりエッチングレジストパターンを形成し、ドライエッチング等のエッチングを行ない、図５（Ｂ）に示すように、上部導体膜２３、２４、２５を形成する。これらの上部導体膜２３、２４、２５の高さは同一となる。このため、上部導体膜２３、２４、２５により形成された端子１７、１８、１９の高さは略同一となる。 (Conductor film patterning)
As in the case of forming the lower conductor film, an etching resist pattern is formed by photolithography, and etching such as dry etching is performed to form upper conductor films 23, 24, and 25 as shown in FIG. To do. These upper conductor films 23, 24, and 25 have the same height. For this reason, the heights of the terminals 17, 18, and 19 formed by the upper conductor films 23, 24, and 25 are substantially the same.

（保護膜形成）
コンデンサを構成する上部導体膜２３等を保護するため、図５（Ｃ）に示すように保護膜３５を形成する。この保護膜３５の材料としては、シリカ、アルミナ等の無機材料、またはエポキシ、ポリイミド等の有機材料等を用いることが可能であるが、前記ＣＰＵ等の用途においては、比誘電率が１５以下程度の低誘電率材料であることが好ましい。また、その形成方法としては、無機材料を用いる場合には、前記ＭＯＤ法やゾルゲル法等の溶液法や、スパッタリング法等が利用できる。また、有機材料を用いる場合は、前記有機材料の塗料をスピンコート法等でコーティングし、硬化させる。 (Protective film formation)
In order to protect the upper conductor film 23 and the like constituting the capacitor, a protective film 35 is formed as shown in FIG. As the material of the protective film 35, inorganic materials such as silica and alumina, or organic materials such as epoxy and polyimide can be used. However, in applications such as the CPU, the relative dielectric constant is about 15 or less. The low dielectric constant material is preferable. As the formation method, when an inorganic material is used, a solution method such as the MOD method or the sol-gel method, a sputtering method, or the like can be used. When an organic material is used, the organic material paint is coated by a spin coating method or the like and cured.

（保護膜パターニング）
図５（Ｄ）に示すように、フォトリソグラフィ技術によりエッチングレジストパターンを形成し、ドライエッチングまたはウエットエッチング等によりエッチングを行ない、前記ＩＣチップ２に接続する端子１７〜１９を形成するために、前記上部導体膜２３、２４、２５を露出させるパターニングを行う。 (Protective film patterning)
As shown in FIG. 5D, an etching resist pattern is formed by a photolithography technique, and etching is performed by dry etching or wet etching to form the terminals 17 to 19 connected to the IC chip 2. Patterning for exposing the upper conductor films 23, 24 and 25 is performed.

このように、電子部品基板３ａ上のＩＣチップ２との対向面に形成された信号端子１９の周囲に、誘電体膜９ｂの形成されていない領域１３を設けたので、パッケージ基板１とＩＣチップ２間に介在させる電子部品における信号端子間に、信号端子１９、１９間の誘電結合を回避することができる。また、誘電体膜９ｂが形成されていない領域１３を設けたので、信号端子１９のホット端子とコールド端子間の容量が低下し、信号の波形歪みを低下させることができる。このため、近年における端子間の高密度配置と高速化に対応できる。   Thus, since the region 13 where the dielectric film 9b is not formed is provided around the signal terminal 19 formed on the surface of the electronic component substrate 3a facing the IC chip 2, the package substrate 1 and the IC chip are provided. The dielectric coupling between the signal terminals 19 and 19 can be avoided between the signal terminals in the electronic component interposed between the two. Further, since the region 13 where the dielectric film 9b is not formed is provided, the capacitance between the hot terminal and the cold terminal of the signal terminal 19 is reduced, and the waveform distortion of the signal can be reduced. For this reason, it is possible to cope with high-density arrangement and high speed between terminals in recent years.

上記実施の形態において、前記上部導体膜２３〜２５により構成される端子１７〜１９の面積、形状は、誘電体膜３１のパターニングにより形成される開口部の面積、形状により決定される。従って、これらＩＣチップ接続用の端子１７〜１９の面積をスルーホール導体１０〜１２の面積より大きくパターニングする場合は、誘電体膜３１の開口部の面積をスルーホール導体１０〜１２より広くすることになるが、その際、信号端子１９を形成するための高さが問題となる。本実施の形態においては、信号端子１９付近には、上部導体膜２５の下に誘電体膜９ｂが環状に残っているため、信号端子１９の高さは、誘電体膜９ｂ上に一部重ねて形成される上部導体膜２３、２４からなる前記電源端子１７、１８の高さと同じとなる。そのため、ＩＣチップ２接続用のバンプ５に対し、全端子１７〜１９を安定的に接続することができる。   In the above embodiment, the areas and shapes of the terminals 17 to 19 constituted by the upper conductor films 23 to 25 are determined by the area and shape of the opening formed by patterning the dielectric film 31. Therefore, when patterning the area of these IC chip connection terminals 17-19 larger than the area of the through-hole conductors 10-12, the area of the opening of the dielectric film 31 should be wider than the through-hole conductors 10-12. However, the height for forming the signal terminal 19 becomes a problem at that time. In the present embodiment, since the dielectric film 9b remains in the annular shape under the upper conductor film 25 in the vicinity of the signal terminal 19, the height of the signal terminal 19 is partially overlapped on the dielectric film 9b. Thus, the height of the power supply terminals 17 and 18 formed of the upper conductor films 23 and 24 is the same. Therefore, all the terminals 17 to 19 can be stably connected to the bump 5 for connecting the IC chip 2.

本発明を実施する場合、基板３ａとして、内蔵導体としてスルーホール導体のみではなく、配線パターンを有する多層基板を用いてもよい。   When practicing the present invention, not only the through-hole conductor but also a multilayer substrate having a wiring pattern may be used as the substrate 3a.

本発明による電子部品の一実施の形態を示す側面図である。It is a side view which shows one Embodiment of the electronic component by this invention. 図１の電子部品の誘電体膜のパターンを示す斜視図である。It is a perspective view which shows the pattern of the dielectric film of the electronic component of FIG. 図１の電子部品の断面図である。It is sectional drawing of the electronic component of FIG. 図３の電子部品の前半の製造工程図である。FIG. 4 is a manufacturing process diagram of the first half of the electronic component of FIG. 3. 図３の電子部品の後半の製造工程図である。FIG. 4 is a manufacturing process diagram in the latter half of the electronic component in FIG. 3. 従来の電子部品の断面図である。It is sectional drawing of the conventional electronic component. 従来の電子部品の誘電体膜のパターンを示す斜視図である。It is a perspective view which shows the pattern of the dielectric film of the conventional electronic component.

符号の説明Explanation of symbols

１：基板、２：ＩＣチップ、３：電子部品、３ａ：電子部品の基板、４、５：バンプ、７：電源端子形成領域、８：信号端子形成領域、９ａ、９ｂ：誘電体膜、１０：第１のスルーホール導体、１１：第２のスルーホール導体、１２：第３のスルーホール導体、１３：誘電体膜非形成領域、１４：正極電源端子、１５：グランド電源端子、１６：信号端子、１７：正極電源端子、１８：グランド電源端子、１９：信号端子、２０〜２２：下部導体膜、２３〜２５：上部導体膜、２６：保護膜、３０：導体膜、３１：誘電体膜、３２、３３：下部導体膜露出部、３４：導体膜、３５：保護膜 1: substrate, 2: IC chip, 3: electronic component, 3a: substrate of electronic component, 4, 5: bump, 7: power terminal formation region, 8: signal terminal formation region, 9a, 9b: dielectric film, 10 : 1st through-hole conductor, 11: 2nd through-hole conductor, 12: 3rd through-hole conductor, 13: Dielectric film non-formation area, 14: Positive power supply terminal, 15: Ground power supply terminal, 16: Signal Terminal: 17: Positive power supply terminal, 18: Ground power supply terminal, 19: Signal terminal, 20-22: Lower conductor film, 23-25: Upper conductor film, 26: Protective film, 30: Conductor film, 31: Dielectric film , 32, 33: exposed portion of the lower conductor film, 34: conductor film, 35: protective film

Claims (4)

パッケージ基板とＩＣチップとの間に介装され電子部品であって、
前記電子部品の基板に、前記パッケージ基板と前記ＩＣチップにそれぞれ備えられた正極電源端子、グランド電源端子および信号端子どうしをそれぞれ接続する内蔵導体および電子部品の基板の両面に設けられた正極電源端子、グランド電源端子および信号端子とを有し、
前記電子部品の基板のＩＣチップ側の面に設けられた正極電源端子とグランド電源端子の間に、コンデンサを構成する誘電体膜および上下の導体膜を形成し、
前記電子部品の基板のＩＣチップ側の面に設けられた信号端子の周囲に、前記誘電体膜が形成されていない領域を設けたことを特徴とする電子部品。 An electronic component interposed between the package substrate and the IC chip,
A positive power supply terminal provided on both surfaces of the substrate of the electronic component, a built-in conductor for connecting the positive power supply terminal, the ground power supply terminal, and the signal terminal provided in the package substrate and the IC chip, respectively, and the electronic component substrate, respectively. A ground power supply terminal and a signal terminal,
Between the positive power supply terminal and the ground power supply terminal provided on the IC chip side surface of the substrate of the electronic component, a dielectric film and upper and lower conductive films constituting a capacitor are formed,
An electronic component, wherein a region where the dielectric film is not formed is provided around a signal terminal provided on a surface of the electronic component substrate on the IC chip side. 請求項１に記載の電子部品において、
前記電子部品のＩＣチップ側信号端子の周囲に、前記誘電体膜を環状に形成したことを特徴とする電子部品。 The electronic component according to claim 1,
An electronic component, wherein the dielectric film is formed in an annular shape around an IC chip side signal terminal of the electronic component. 請求項２に記載の電子部品において、
前記環状に残した誘電体膜の周囲に、誘電体膜を形成していない領域を環状に設けたことを特徴とする電子部品。 The electronic component according to claim 2,
An electronic component characterized in that a region where no dielectric film is formed is provided in a ring around the ring-shaped dielectric film. 請求項１から３までのいずれかに記載の電子部品と、該電子部品を挟むように設けたパッケージ基板およびＩＣチップからなることを特徴とする半導体装置。   A semiconductor device comprising the electronic component according to claim 1, a package substrate and an IC chip provided so as to sandwich the electronic component.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010182708A (en) * 2009-02-03 2010-08-19 Nec Corp Capacitor structure and method for manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060115A (en) * 2001-08-20 2003-02-28 Fujitsu Ltd Circuit board with built-in capacitor and method for manufacturing the same
JP2005123250A (en) * 2003-10-14 2005-05-12 Fujitsu Ltd Interposer, its manufacturing method and electronic device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060115A (en) * 2001-08-20 2003-02-28 Fujitsu Ltd Circuit board with built-in capacitor and method for manufacturing the same
JP2005123250A (en) * 2003-10-14 2005-05-12 Fujitsu Ltd Interposer, its manufacturing method and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010182708A (en) * 2009-02-03 2010-08-19 Nec Corp Capacitor structure and method for manufacturing the same

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