JP2007123415A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for lowering a contact resistance by enlarging a contact area with a contact even in the projected semiconductor layer having a small cross-sectional area. <P>SOLUTION: The semiconductor device comprises a projected semiconductor layer formed on a semiconductor substrate, and a contact area which is in contact with a ceiling surface of the projected semiconductor layer and a part of the side wall thereof and is electrically connected to the projected semiconductor layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a contact portion for connecting a convex semiconductor layer formed on a semiconductor substrate to a metal wiring portion.

  Examples of components of the semiconductor integrated circuit include circuit elements such as a resistance element, a capacitor element, and a transistor. At present, these elements mainly have a planar structure with respect to a semiconductor substrate, a so-called planar structure. The degree of integration of planar structure elements is limited by the resolution limit of photolithography technology. As a technique for achieving the next-generation integration without depending on the resolution limit of the photolithography technique, there is a demand for a three-dimensional semiconductor element technique.

  As an example of a three-dimensional semiconductor element technology, an S-SGT (Stacked-Surround Gate Transistor) flash memory having a columnar structure has been proposed (for example, see Patent Document 1).

FIG. 16 is an explanatory diagram showing an example of the structure of a conventional S-SGT flash memory. The S-SGT flash memory shown in FIG. 16 has two transistors and three memory cells on the side wall of a columnar convex semiconductor layer formed on the silicon substrate 1. Then, an n + type impurity introduction layer 10 is formed on the top surface of the columnar convex semiconductor layer, and the impurity introduction layer 10 and the metal wiring portion 12 are electrically connected. A three-dimensional structure element using a convex semiconductor layer, such as an S-SGT flash memory, has a contact portion that connects the top surface of the convex semiconductor layer and a metal wiring portion.
JP-A-4-79369

  In order to improve the integration degree of the three-dimensional structure element formed by forming the convex semiconductor layer on the semiconductor substrate as described above, it is desirable to reduce the cross-sectional area of the convex semiconductor layer. However, when the cross-sectional area of the convex semiconductor layer is reduced, the area of the top surface of the convex semiconductor layer is also reduced, and the contact area with the contact portion is reduced. As a result, the contact resistance is increased, which causes deterioration of the operating characteristics of the semiconductor element, for example, a decrease in the driving current of the transistor. From the above, it is desirable to reduce the contact resistance while reducing the cross-sectional area of the convex semiconductor layer.

  The present invention provides a technique capable of suppressing contact resistance to a low level by increasing the contact area with a contact portion even with a convex semiconductor layer having a small cross-sectional area.

  The present invention includes a convex semiconductor layer formed on a semiconductor substrate, and a contact portion that contacts the top surface and a part of the side wall of the convex semiconductor layer and is electrically connected to the convex semiconductor layer. A semiconductor device is provided.

  Further, from a different point of view, the present invention includes a step of forming a convex semiconductor layer on a semiconductor substrate, and a step of embedding the formed convex semiconductor layer to the top surface and depositing an insulating film so that the surface is flattened. Forming a contact hole by selectively etching the insulating film by anisotropic etching so as to expose the top surface and part of the side wall of the embedded convex semiconductor layer, and the formed contact hole A method of manufacturing a semiconductor device, comprising: depositing a conductive film on the top surface of the convex semiconductor layer and bringing the conductive film into contact with a part of the side wall.

  Furthermore, the present invention includes a step of forming a convex semiconductor layer on a semiconductor substrate, a step of embedding the formed convex semiconductor layer to the top surface, and depositing a first insulating film so that the surface is flattened; Etching back the first insulating film so as to expose the top surface and part of the side wall of the embedded convex semiconductor layer, and etching the back of the first insulating film and the exposed convex semiconductor layer. Depositing a second insulating film on the surface, depositing a third insulating film on the second insulating film, filling the convex semiconductor layer up to the top surface, and flattening the surface; and embedding Forming a contact hole by selectively etching the third insulating film by anisotropic etching so as to expose the top surface and part of the side wall of the protruding semiconductor layer. Contact To provide a method of manufacturing a semiconductor device characterized by comprising the steps of: Le in depositing a conductive film contacting the conductive film and a portion of the top surface and the side wall of the protruding semiconductor layer.

  Since the semiconductor device of the present invention includes the contact portion that contacts the top surface of the convex semiconductor layer and a part of the side wall, even the convex semiconductor layer having a small top surface area has a large contact with the contact portion. The contact resistance can be kept low by securing the area.

  Here, the convex semiconductor layer is a convex semiconductor layer formed on at least a part of the surface of the semiconductor substrate. The shape of the convex semiconductor layer may be cylindrical, but is not limited thereto, and may have a shape such as a prism. Further, the vertical cross section of the convex semiconductor layer may be trapezoidal. The material of the convex semiconductor layer may be, for example, p-type silicon, but is not limited thereto, and may be n-type silicon, or a semiconductor other than silicon such as germanium or GaAs. The material is preferably the same as that of the semiconductor substrate, but is not necessarily limited thereto.

  The cross-sectional shape of the contact portion may be circular, but is not limited thereto, and may be, for example, elliptical, rectangular, or polygonal.

In addition, the semiconductor device of the present invention further includes an insulating layer that covers the periphery of the contact portion connected to the convex semiconductor layer, and a wiring portion formed on the insulating layer, and the contact portion includes The insulating layer may be embedded in the insulating layer so as to penetrate up and down and have one end connected to the convex semiconductor layer and the other end connected to the wiring portion.
The conductive material is preferably the same as the material used for the wiring portion, but is not limited thereto. The conductive material used for the contact portion may be aluminum, but is not limited thereto, and may be a metal such as copper, gold, or silver. Alternatively, a conductive material other than metal may be used.

  Furthermore, one or more circuit elements may be formed on a part or all of the periphery of the side wall of the convex semiconductor layer, and the circuit elements further include a resistor element, a capacitor element, a diode, a transistor, and a thyristor. It may be any element of the memory cell or a combination thereof.

  The shape of the contact portion may be determined so that the contact area with the convex semiconductor layer is larger than the area of the top surface of the convex semiconductor layer. In this case, since the total contact area of the contact portion combining the top surface of the convex semiconductor layer and a part of the side wall is larger than the contact area with the convex semiconductor layer, only the top surface is provided. A semiconductor device having a low contact resistance can be obtained as compared with the conventional structure in which the contact portion contacts.

  Further, when the material of the convex semiconductor layer is silicon, the top surface thereof may be silicided. In this way, the contact resistance can be further reduced by siliciding the contact surface with the contact portion. The metal used for silicidation may be, for example, cobalt, but is not limited thereto, and may be, for example, tungsten, molybdenum, tantalum, titanium, nickel, or platinum.

Alternatively, the contact portion is formed such that a cross-sectional area in a horizontal plane passing through the top surface of the convex semiconductor layer is larger than an area of the top surface of the convex semiconductor layer, and an upper portion of the side wall of the convex semiconductor layer It may come into contact so as to surround the entire circumference. In this way, the contact portion contacts the entire periphery of the upper portion of the convex semiconductor layer side wall so that the contact area between the contact portion and the convex semiconductor layer is larger than the area of the top surface of the convex semiconductor layer. And a semiconductor device with low contact resistance can be obtained. Further, when forming the contact hole, even if the alignment with respect to the convex semiconductor layer is slightly deviated, the contact portion contacts so as to surround the entire circumference of the upper side of the convex semiconductor layer, so that exact alignment is required. It will not be done. Therefore, a low contact resistance can be stably obtained, the performance of the semiconductor device is stabilized, and the yield is improved. An example of the relationship between the contact portion and the convex semiconductor layer is that when the contact portion and the convex semiconductor layer are both cylindrical, the diameter of the contact portion is 1. It is desirable to be 1 to 1.3 times.
However, since the diameter of the contact portion is determined by the alignment margin when forming the contact hole, it is actually limited by the performance of the device used.

  The area of the cross section of the contact portion in a horizontal plane passing through the top surface of the convex semiconductor layer is equal to or smaller than the area of the top surface of the convex semiconductor layer, and the convex semiconductor layer It may be formed so as to be in contact with a part of the upper part of the side wall. In this way, even when the cross-sectional area is equal to or smaller than the area of the top surface of the convex semiconductor layer, the contact portion is brought into contact with a part of the upper portion of the side wall of the convex semiconductor layer. Thus, a contact area larger than the area of the top surface of the convex semiconductor layer can be ensured.

  Also, in the manufacturing method of the present invention, the insulating film is selectively etched by anisotropic etching so as to expose the top surface and part of the side wall of the embedded convex semiconductor layer, thereby forming a contact hole. And a step of depositing a conductive film in the formed contact hole and bringing the conductive film into contact with the top surface and a part of the side wall of the convex semiconductor layer. Not only the top surface of the convex semiconductor layer but also the side wall can be contacted.

  Further, the manufacturing method of the present invention includes a step of depositing a third insulating film on the second insulating film to bury the convex semiconductor layer up to the top surface and flatten the surface, and the embedded convex semiconductor. A contact hole forming step of selectively etching the third insulating film by anisotropic etching so as to expose a top surface of the layer and a part of the side wall, and forming a contact hole in the formed contact hole; Depositing and contacting the conductive film with the top surface of the convex semiconductor layer and a part of the side wall, so that the second insulating film serves as a stopper and a part of the side wall of the convex semiconductor layer is predetermined. The insulating film that becomes a contact portion by accurately exposing to the depth can be brought into contact with not only the top surface of the convex semiconductor layer but also the side wall.

  The contact hole forming step may be a step using the second insulating film as an etching stopper.

  From the above, it is possible to sufficiently secure the contact area of the contact part by electrically connecting the metal wiring part not only to the top surface of the convex semiconductor layer but also to the side wall, and as a result, the contact resistance is reduced. It can be lowered.

  As described above, according to the method of manufacturing a semiconductor device of the present invention, in a convex semiconductor layer formed on a semiconductor substrate, for example, an S-SGT flash memory, a contact portion that connects the convex semiconductor layer and a metal wiring portion. The contact area can be increased and the contact resistance can be lowered.

  In addition, although it does not specifically limit regarding the convex semiconductor layer on a semiconductor substrate, For example, S-SGT flash etc. are mentioned. However, the shape is not necessarily limited thereto, and the shape is not limited as long as it is a convex semiconductor layer arranged on a semiconductor substrate.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view and a plan view of a contact portion 205 that connects the convex semiconductor layer 300 and the metal wiring portion 201 according to the first embodiment. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. In the first embodiment, the diameter of the contact portion 205 is made larger than the diameter of the convex semiconductor layer 300, and not only the top surface of the convex semiconductor layer 300 but also a region near the top surface of the side wall is used as the contact surface of the contact portion 205. As a result, the contact resistance is lowered.

2 to 3 are process sectional views showing a method of forming the contact portion 205 shown in FIG.
First, the convex semiconductor layer 300 is formed on the semiconductor substrate 100. A known method can be applied to the formation of the convex semiconductor layer 300. For example, a part of the surface of the semiconductor substrate 100 is etched using a known anisotropic etching method such as a photolithography technique and a reactive ion etching method (hereinafter referred to as RIE) technique, and the semiconductor substrate 100 is dug down to have a convex shape. This is a method for forming the semiconductor layer 300. Alternatively, the convex semiconductor layer 300 may be formed on the semiconductor substrate 100 by a selective epitaxial growth method.
Then, an insulating film 200 such as a silicon oxide film is deposited so as to completely cover the convex semiconductor layer 300 formed on the semiconductor substrate 100. Further, the surface of the silicon oxide film 200 is planarized using CMP (Chemical Mechanical Polishing) or the like (see FIG. 2).

Next, using the resist 202 patterned by a known photolithography technique as a mask, anisotropic etching is performed so that the upper part of the convex semiconductor layer 300, in other words, the side wall as well as the top surface of the convex semiconductor layer 300 is exposed. Then, contact holes 206 are formed (see FIG. 3).
The processing dimensions of the contact hole 206 are as follows. The hole diameter is desirably about 1.1 to 1.3 times the diameter of the convex semiconductor layer 300, but is not necessarily limited to that range as long as it is larger than the diameter of the convex semiconductor layer 300 (FIG. 1B). )reference).

  There are two advantages by making the hole diameter larger than the diameter of the convex semiconductor layer 300. The first is that the contact area of the contact portion 205 is increased, and the second is that the contact area does not change even if the position of the contact hole is shifted in the photolithography process, in other words, the alignment margin of the photolithography process is increased. That is.

  FIG. 4 is an explanatory diagram showing a contact area S between the contact portion 205 and the convex semiconductor layer 300 and a cross-sectional area Sc of the contact hole in a horizontal plane passing through the top surface of the convex semiconductor layer 300. As shown in FIG. 4, the contact portion 205 has a bottom surface at a depth d from the top surface of the convex semiconductor layer 300, and the contact area S with the convex semiconductor layer 300 is equal to that of the convex semiconductor layer 300. This is the sum of the area St of the top surface and the area Sp of the contact portion 205 covering the entire circumference of the side wall of the convex semiconductor layer with the depth d. On the other hand, the cross-sectional area of the contact portion 205 in a horizontal plane passing through the top surface of the convex semiconductor layer 300 is Sc. The contact portion 205 is desirably formed so that the contact area S = St + Sp with the convex semiconductor layer 300 is larger than the cross-sectional area Sc, but is not necessarily limited to that range.

  Further, as described above, in order to form the contact portion 205, the silicon oxide film 200 is selectively removed by anisotropic etching to form a contact hole, and the top surface and the upper portion of the sidewall of the convex semiconductor layer 300 are formed. And expose. Since the exposed upper portion of the convex semiconductor layer 300 becomes a contact area of the contact portion 205, the depth d of the contact hole is preferably as deep as possible from the viewpoint of reducing contact resistance. However, the height of the convex semiconductor layer 300 is determined based on a balance with the size of the element formed on the side wall of the convex semiconductor layer 300 because there are restrictions due to etching anisotropy and the time required for the process, that is, cost. It should be.

  Next, after siliciding the upper part of the convex semiconductor layer 300 used as the contact part 205 with cobalt or the like, the contact part 205 is formed, and the metal wiring part 201 is formed, whereby the contact part shown in FIG. 1 is formed. . In the first embodiment, the cylindrical convex semiconductor layer has been described as an example, but the shape is not limited as long as it is a convex semiconductor layer.

(Second embodiment)
FIG. 5 is a cross-sectional view and a plan view of a contact portion 205 that connects the convex semiconductor layer 300 and the metal wiring portion 201 according to the second embodiment of the present invention. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line II ′ of FIG. 5A.
In the second embodiment, the contact portion 205 has a diameter larger than that of the convex semiconductor layer 300, and not only the top surface of the convex semiconductor layer 300 but also the side wall is used as the contact surface of the contact portion 205, thereby improving the contact resistance. Lower.

  Furthermore, by using an etching stopper in the process of forming the contact hole, process damage on the convex semiconductor layer 300 used as a contact surface of the contact portion is reduced, and the depth of the contact hole is processed with high accuracy. Is possible.

6 to 11 are process sectional views showing a method of forming the contact portion 205 shown in FIG.
First, a first insulating film 200, for example, a silicon oxide film is deposited so as to completely cover the convex semiconductor layer 300 formed on the semiconductor substrate 100.
Further, the surface of the silicon oxide film 200 is planarized using CMP (Chemical Mechanical Polishing) or the like (see FIG. 6), and only the top of the convex semiconductor layer 300, in other words, the top surface of the convex semiconductor layer 300 is used. Etchback is performed so that the side wall is exposed instead (see FIG. 7).

  Note that the etching amount of the silicon oxide film 200 is desirably etched to a depth at which the contact area S of the contact portion 205 becomes larger than the horizontal sectional area Sc of the contact hole. However, the range is not necessarily limited (see FIG. 4). Further, since the exposed upper portion of the convex semiconductor layer 300 is a contact area of the contact portion 205, it is desirable that the etching amount is larger.

  Next, a second insulating film 203, for example, a silicon nitride film is deposited to a thickness of about 10 to 200 nm (see FIG. 8). The silicon nitride film 203 is an insulating film for stopping contact hole etching in a later process at a set position, a so-called etch stopper.

  Next, a third insulating film 204, for example, a silicon oxide film is deposited so as to completely cover the convex semiconductor layer portion, and the surface of the silicon oxide film 204 is planarized using CMP (chemical mechanical polishing) or the like. (See FIG. 9). Using the resist 202 patterned by a known photolithography technique as a mask, the silicon oxide film 204 is etched by anisotropic etching (see FIG. 10).

  The contact hole diameter is preferably about 1.1 to 1.3 times the diameter of the convex semiconductor layer 300, but is not necessarily limited to that range as long as it is larger than the diameter of the convex semiconductor layer 300 (FIG. 5). (See (b)).

  There are two advantages by making the hole diameter larger than the diameter of the convex semiconductor layer 300. The first is that the contact area of the contact portion 205 is increased, and the second is that the alignment margin of the photolithography process is increased. Next, the silicon nitride film 203 is etched by etching having a high selection ratio with the silicon oxide films 200 and 204, for example, wet etching (see FIG. 11).

Note that etching damage to the convex semiconductor layer 300 can be reduced because etching with high selectivity such as wet etching is used.
Next, after the upper portion of the convex semiconductor layer 300 used as the contact portion 205 is silicided with cobalt or the like, the contact portion 205 is formed, and the metal wiring portion 201 is formed, whereby the contact portion shown in FIG. 5 is formed. . In the second embodiment, a cylindrical convex semiconductor layer has been described as an example, but the shape is not limited as long as it is a convex semiconductor layer.

(Third embodiment)
12 and 13 are a cross-sectional view and a plan view of a contact portion 205 connecting the convex semiconductor layer 300 and the metal wiring portion 201 according to the third embodiment of the present invention. FIG. 13 differs from FIG. 12 in that there is a silicon vagina film 203 and a silicon oxide film 204, which corresponds to FIG. 1 (see the first embodiment) in FIG. 5 (see the second embodiment). Respond to differences. 12A is a plan view, and FIG. 12B is a cross-sectional view taken along the line BB ′ of FIG. 12A. 13A is a plan view, and FIG. 13B is a cross-sectional view taken along the line BB ′ of FIG. 13A.

  As shown in FIGS. 12 and 13, in this embodiment, a part of the side wall of the convex semiconductor layer 300 and the metal wiring have the same diameter as that of the convex semiconductor layer 300 or smaller than that of the convex semiconductor layer 300. The part 201 is electrically connected. As shown in FIGS. 12B and 13B, the centers of the convex semiconductor layer 300 and the contact hole 205 are shifted, and a part of the side wall of the convex semiconductor layer 300 is used as a contact surface of the contact portion 205. As a result, compared with the case where only the top surface is used as the contact surface, a wide contact area is secured and the contact resistance is lowered. The basic structure and manufacturing process of FIG. 12 are the same as those of the first embodiment, and the basic structure and manufacturing process of FIG. 13 are the same as those of the second embodiment.

  In the embodiments so far, the convex semiconductor layer on the semiconductor substrate has been described as an example. Next, an example in which an S-SGT flash memory and a FinFET are taken as examples of a three-dimensional structure element using a convex semiconductor layer will be described.

(Fourth embodiment)
FIG. 14 is an explanatory diagram showing an example in which an S-SGT flash memory is formed on the convex semiconductor layer of the semiconductor device according to the present invention. A gate oxide film 207, a floating gate 208, an ONO (Oxide Nitride Oxide) film 209, and a control gate 210 are formed in the memory cell portion of the columnar convex semiconductor layer 300, and a gate is formed in the transistor portion of the columnar convex semiconductor layer 300. An oxide film 207 and a gate electrode 213 are formed.

A source diffusion layer 211 is formed on the bottom of the columnar convex semiconductor layer 300, and a drain diffusion layer 212 is formed on the top surface of the columnar convex semiconductor layer 300. As shown in FIG. 13, the contact portion 205 of the S-SGT flash memory uses a part of the side wall of the columnar convex semiconductor layer 300 as a contact surface.
In FIG. 14, a part of the side wall of the columnar convex semiconductor layer 300 is connected to the metal wiring part 201 with a contact hole diameter equal to or smaller than the diameter of the columnar convex semiconductor layer 300 (third). (See the embodiment).

  The contact portion of the S-SGT flash memory is not limited to the above case, and the contact hole diameter is larger than the diameter of the columnar convex semiconductor layer 300 and the upper portion of the columnar convex semiconductor layer 300 and the metal wiring portion. 201 may be connected (see the first and second embodiments). In FIG. 14, two transistors and two memory cells are formed on the sidewall of the convex semiconductor layer 300, but the number of transistors and memory cells is not limited.

(Fifth embodiment)
FIG. 15 is an explanatory view showing an example in which a FinFET (Fin Field Effect Transistor) is formed on the convex semiconductor layer of the semiconductor device according to the present invention. 15A is a plan view, and FIG. 15B is a cross-sectional view taken along the line AA ′ of FIG. 15A. As shown in FIG. 15A, there is a FinFET 215 where the gate electrode 213 and the convex semiconductor layer 214 on the semiconductor substrate intersect. The present invention is used for the gate contact 216, the source contact 217, and the drain contact 218 of the FinFET.

  FIG. 15A shows a case in which a part of the side wall of the convex semiconductor layer 214 is connected to the metal wiring part 201 with a contact hole width equal to or smaller than the width of the convex semiconductor layer 214 (third). (See the embodiment). Note that the source contact portion 217 of the FinFET is not limited to the above case, and the upper portion of the convex semiconductor layer 214 is connected to the metal wiring portion 201 with a contact hole width larger than the width of the convex semiconductor layer 214. (Refer to the first and second embodiments).

FIG. 4 is a cross-sectional view and a plan view of a contact portion 205 that connects a convex semiconductor layer 300 and a metal wiring portion 201 according to the present invention. (First embodiment) FIG. 10 is a process cross-sectional view illustrating a process according to a method for forming contact portion 205 shown in FIG. (First embodiment) FIG. 10 is a process cross-sectional view illustrating different processes according to the method for forming the contact portion 205 illustrated in FIG. 1. (First embodiment) 4 is an explanatory diagram showing a contact area S between a contact portion 205 and a convex semiconductor layer 300 and a cross-sectional area Sc of a contact hole in a horizontal plane passing through the top surface (cross-sectional area St) of the convex semiconductor layer 300. FIG. (First embodiment) FIG. 4 is a cross-sectional view and a plan view of a contact portion 205 that connects a convex semiconductor layer 300 and a metal wiring portion 201 according to the present invention. (Second embodiment) FIG. 6 is a process cross-sectional view illustrating a process according to a method for forming the contact portion 205 illustrated in FIG. 5. (Second embodiment) FIG. 6 is a process cross-sectional view illustrating different processes according to the method for forming the contact portion 205 illustrated in FIG. 5. (Second embodiment) FIG. 6 is a process cross-sectional view illustrating still another process related to the method for forming the contact portion 205 illustrated in FIG. 5. (Second embodiment) FIG. 6 is a process cross-sectional view illustrating still another process related to the method for forming the contact portion 205 illustrated in FIG. 5. (Second embodiment) FIG. 6 is a process cross-sectional view illustrating still another process related to the method for forming the contact portion 205 illustrated in FIG. 5. (Second embodiment) FIG. 6 is a process cross-sectional view illustrating still another process related to the method for forming the contact portion 205 illustrated in FIG. 5. (Second embodiment) FIG. 6 is a cross-sectional view and a plan view of an example of a contact portion 205 that connects the convex semiconductor layer 300 and the metal wiring portion 201 according to the present invention. (Third embodiment) FIG. 6 is a cross-sectional view and a plan view of another example of a contact portion 205 that connects the convex semiconductor layer 300 and the metal wiring portion 201 according to the present invention. (Third embodiment) It is explanatory drawing which shows the example in which the S-SGT flash memory was formed in the convex-shaped semiconductor layer of the semiconductor device based on this invention. (Fourth embodiment) It is explanatory drawing which shows the example by which FinFET was formed in the convex-shaped semiconductor layer of the semiconductor device based on this invention. (Fifth embodiment) It is explanatory drawing which shows an example of the structure of the conventional S-SGT flash memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 200 1st insulating film, silicon oxide film 201 Metal wiring part 202 Resist 203 Second insulating film, silicon vagina film 204 Third insulating film, silicon oxide film 205 Contact part 206 Contact hole 207 Gate oxide film 208 floating gate 209 ONO film 210 control gate 211 source diffusion layer 212 drain diffusion layer 213 gate electrode 214 convex semiconductor 215 FinFET
216 Gate contact 217 Source contact 218 Drain contact 300 Convex semiconductor layer

Claims (11)

A convex semiconductor layer formed on a semiconductor substrate;
A semiconductor device comprising: a contact portion that is in contact with a top surface of the convex semiconductor layer and part of a side wall and is electrically connected to the convex semiconductor layer. An insulating layer covering the periphery of the contact portion connected to the convex semiconductor layer;
A wiring portion formed on the insulating layer;
The contact portion is embedded in the insulating layer so as to penetrate the insulating layer vertically and have one end connected to the convex semiconductor layer and the other end connected to the wiring portion. Semiconductor device.   The semiconductor device according to claim 1, wherein one or more circuit elements are formed in part or all of the periphery of the side wall of the convex semiconductor layer.   The semiconductor device according to claim 3, wherein the circuit element is any one of a resistor element, a capacitor element, a diode, a transistor, a thyristor, and a memory cell, or a combination thereof.   The semiconductor device according to claim 1, wherein a shape of the contact portion is determined so that a contact area with the convex semiconductor layer is larger than an area of a top surface of the convex semiconductor layer.   The semiconductor device according to claim 1, wherein a top surface of the convex semiconductor layer is silicided.   The contact portion is formed such that a cross-sectional area in a horizontal plane passing through the top surface of the convex semiconductor layer is larger than an area of the top surface of the convex semiconductor layer, and the entire upper portion of the side wall of the convex semiconductor layer is formed. The semiconductor device according to claim 2, which makes contact so as to surround the circumference.   A cross-sectional area of the contact portion in a horizontal plane passing through the top surface of the convex semiconductor layer is equal to or smaller than an area of the top surface of the convex semiconductor layer, and the side wall of the convex semiconductor layer 3. The semiconductor device according to claim 2, wherein the semiconductor device is formed so as to be in contact with a part of an upper portion of the semiconductor device. Forming a convex semiconductor layer on a semiconductor substrate;
Burying the formed convex semiconductor layer to the top surface and depositing an insulating film so that the surface is flat; and
Forming the contact hole by selectively etching the insulating film by anisotropic etching so as to expose the top surface and part of the side wall of the embedded convex semiconductor layer;
And a step of depositing a conductive film in the formed contact hole and bringing the conductive film into contact with a top surface and a part of the side wall of the convex semiconductor layer. Forming a convex semiconductor layer on a semiconductor substrate;
Burying the formed convex semiconductor layer to the top surface and depositing a first insulating film so that the surface is flat; and
Etching back the first insulating film so as to expose the top surface and part of the sidewall of the embedded convex semiconductor layer;
Depositing a second insulating film on the etched back first insulating film and the exposed surface of the convex semiconductor layer;
Depositing a third insulating film on the second insulating film to bury the convex semiconductor layer up to the top surface to flatten the surface;
A contact hole forming step of forming a contact hole by selectively etching the third insulating film by anisotropic etching so as to expose a top surface and a part of the side wall of the embedded convex semiconductor layer;
And a step of depositing a conductive film in the formed contact hole and bringing the conductive film into contact with a top surface and a part of the side wall of the convex semiconductor layer.   The manufacturing method according to claim 10, wherein the contact hole forming step is a step of using the second insulating film as an etching stopper.

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