JP2007123023A - Organic el display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent generation of visible stripe-like display irregularity in a display image when an upper surface emission type organic EL display device is sealed by using a sealing substrate. <P>SOLUTION: This upper surface emission type organic EL display device is provided with: an array substrate AS having an insulation substrate SUB and an insulation pattern layer PI; the sealing substrate CS facing to the array substrate AS by interposing the insulation pattern layer PI; and a sealing layer SS interlaid between the array substrate AS and the sealing substrate CS and surrounding the insulation pattern layer PI. The insulation pattern layer PI includes a barrier rib part located in a display region, and a spacer part located in a peripheral region; the respective facing surfaces of the barrier rib part and the spacer part to the sealing substrate CS come into contact with the sealing substrate CS; when viewed from a direction vertical to the principal surface of the insulation substrate SUB, an area ratio of the spacer part to a part located between the sealing layer SS and the display region out of the peripheral region is smaller than the area ratio of the barrier rib part to the display region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an organic EL (electroluminescence) display device.

  An organic EL element easily deteriorates when it comes into contact with moisture or oxygen. Therefore, in the organic EL display device, the organic EL element is sealed to prevent contact between the organic EL element and moisture or oxygen.

  As a sealing method of the organic EL element, there are hollow sealing and thin film sealing. In the hollow sealing, for example, a sealing substrate such as glass is disposed so as to face the surface of the array substrate on which the organic EL element is formed and to be separated from the array substrate. And the opposing surface peripheral parts of these board | substrates are bonded together with an adhesive agent, and a hollow body is formed. The internal space of the hollow body is filled with an inert gas or is evacuated, for example. In this case, typically, a bottom emission type is adopted for the organic EL display device, and a desiccant is further disposed in the inner space.

  As described above, when hollow sealing is performed, it is common to adopt a bottom emission type for an organic EL display device. On the contrary, the present inventors performed sealing using a sealing substrate in a top emission type organic EL display device. As a result, the present inventors have found that in a top emission type organic EL display device, when sealing is performed using a sealing substrate, striped display unevenness may occur in a display image.

  An object of the present invention is to prevent striped display unevenness that can be visually recognized from occurring in a display image when sealing is performed using a sealing substrate in a top emission type organic EL display device. .

  According to a first aspect of the present invention, an insulating substrate, an insulating pattern layer disposed on one main surface of the insulating substrate and provided with a plurality of openings, on the main surface of the insulating substrate, Each includes a first electrode disposed at a position corresponding to the opening, a second electrode covering the insulating pattern layer and facing the first electrode, and an organic material layer interposed between the first and second electrodes. An array substrate including a plurality of organic EL elements, a sealing substrate facing the array substrate with the insulating pattern layer interposed therebetween, and the insulating pattern interposed between the array substrate and the sealing substrate. A sealing layer surrounding the layer, and the insulating pattern layer is located in a partition wall located in a display area where the plurality of organic EL elements are arranged, and in a peripheral area surrounding the display area Special Each facing surface of the partition wall and the spacer portion with the sealing substrate is in contact with the sealing substrate through a layer including the second electrode, or the sealing The spacer for a portion of the peripheral area located between the seal layer and the display area when viewed from a direction perpendicular to the main surface of the insulating substrate and in direct contact with the substrate A top emission organic EL display device is provided in which the area ratio of the portion is smaller than the area ratio of the partition wall to the display region.

  According to a second aspect of the present invention, an insulating substrate, an insulating pattern layer disposed on one main surface of the insulating substrate and provided with a plurality of openings, on the main surface of the insulating substrate, Each includes a first electrode disposed at a position corresponding to the opening, a second electrode covering the insulating pattern layer and facing the first electrode, and an organic material layer interposed between the first and second electrodes. An array substrate including a plurality of organic EL elements, a sealing substrate facing the array substrate with the insulating pattern layer interposed therebetween, and the insulating pattern interposed between the array substrate and the sealing substrate. A sealing layer surrounding the layer, and the insulating pattern layer is located in a partition wall located in a display area where the plurality of organic EL elements are arranged, and in a peripheral area surrounding the display area Special Each facing surface of the partition wall and the spacer portion with the sealing substrate is in contact with the sealing substrate through a layer including the second electrode, or the sealing In a state where the substrate is in direct contact with the array substrate and the sealing substrate and separated from each other, the spacer portion has a height relative to the main surface of the insulating substrate as compared with the partition wall portion. There is provided a top emission type organic EL display device characterized by having a lower value.

  According to the present invention, when sealing using a sealing substrate is performed in a top emission type organic EL display device, it is possible to prevent striped display unevenness that can be visually recognized from occurring in a display image.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the component which exhibits the same or similar function, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a plan view schematically showing an organic EL display device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II of the organic EL display device shown in FIG. FIG. 3 is an enlarged cross-sectional view showing a part of the organic EL display device shown in FIG. FIG. 4 is an enlarged cross-sectional view showing another part of the organic EL display device shown in FIG. FIG. 5 is an equivalent circuit diagram of the organic EL display device shown in FIG.

  2 to 4, the organic EL display device is illustrated such that its display surface, that is, the front surface or the light emitting surface faces upward, and the back surface faces downward. Further, as will be described later, FIG. 3 shows the structure in the display area of the insulating pattern layer PI, and FIG. 4 shows the structure in the peripheral area of the insulating pattern layer PI.

  This organic EL display device is a top emission type organic EL display device adopting an active matrix driving method. As shown in FIGS. 1 and 2, the organic EL display device includes an array substrate AS and a sealing substrate CS. The array substrate AS and the sealing substrate CS are disposed so as to face each other, and the central portions of the opposing surfaces are in contact with each other. A frame-shaped seal layer SS is interposed between the peripheral portions of the opposing surfaces of the array substrate AS and the sealing substrate CS.

  The array substrate AS includes, for example, an insulating substrate SUB such as a glass substrate.

On the substrate SUB, as shown in FIGS. 3 and 4, for example, a SiN _x layer and a SiO _x layer are sequentially stacked as the undercoat layer UC. On the undercoat layer UC, for example, a gate insulating film GI that can be formed using a semiconductor layer SC that is a polysilicon layer in which a channel and a source / drain are formed, for example, TEOS (TetraEthyl OrthoSilicate), etc., and MoW, for example, The gate electrodes G are sequentially stacked, and they constitute a top gate type TFT. In this example, these TFTs are p-channel TFTs, and are used as the drive control element DR and switches SW1 to SW3 included in the pixel PX of FIG.

  On the gate insulating film GI, scanning signal lines SL1 and SL2 that can be formed in the same process as the gate electrode G are further arranged. As shown in FIG. 5, each of the scanning signal lines SL1 and SL2 extends in the row direction (X direction) of the pixels PX, and is alternately arranged in the column direction (Y direction) of the pixels PX. These scanning signal lines SL1 and SL2 are connected to the scanning signal line driver YDR.

As shown in FIGS. 3 and 4, the gate insulating film GI, the gate electrode G, and the scanning signal lines SL1 and SL2 are covered with an interlayer insulating film II made of, for example, SiO _x formed by a plasma CVD method or the like. Yes. A source electrode SE and a drain electrode DE are disposed on the interlayer insulating film II, and are embedded with a passivation film PS made of, for example, SiN _x . The source electrode SE and the drain electrode DE have, for example, a three-layer structure of Mo / Al / Mo, and are electrically connected to the source and drain of the TFT through contact holes provided in the interlayer insulating film II. ing.

  A video signal line DL that can be formed in the same process as the source electrode SE and the drain electrode DE is further disposed on the interlayer insulating film II. As shown in FIG. 5, the video signal lines DL each extend in the Y direction and are arranged in the X direction. These video signal lines DL are connected to a video signal line driver XDR. Typically, the power supply line PSL of FIG. 5 is laid between the layers where the scanning signal lines SL1 and SL2 are arranged, or between the layers where the video signal lines DL are arranged.

  On the passivation film PS, a planarization layer FL is formed as shown in FIGS. On the flattening layer FL, a reflective layer RF is disposed. As a material of the planarizing layer FL, for example, a hard resin can be used. As a material of the reflective layer RF, for example, a metal material such as Al can be used.

  The planarization layer FL and the reflection layer RF are covered with the light extraction layer OC. The light extraction layer OC is not necessarily provided. However, when the light extraction layer OC is provided, the traveling direction of light propagating in the film surface direction can be changed while repeating reflection inside an organic EL element OLED described later. . In this way, light emitted from the light emitting layer of the organic EL element OLED can be extracted with high efficiency to the outside of the organic EL element OLED. As the light extraction layer OLED, for example, a light scattering layer or a diffraction grating can be used.

  On the light extraction layer OLED, the light transmissive first electrodes PE are juxtaposed apart from each other as a back electrode. Each first electrode PE is a pixel electrode and is disposed to face the reflective layer RF. Further, each first electrode PE is connected to the drain electrode DE through a through hole provided in the passivation film PS, the planarization layer FL, and the light extraction layer OC.

  The first electrode PE is an anode in this example. As a material of the first electrode PE, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide) can be used.

  An insulating pattern layer PI is further disposed on the light extraction layer OC. In the insulating pattern layer PI, a portion located in the display region surrounded by the alternate long and short dash line L shown in FIG. 1 is a partition wall portion, and a portion located in the peripheral region surrounding the display region is a spacer portion. FIG. 3 shows a partition portion of the insulating pattern layer PI, and FIG. 4 shows a spacer portion of the insulating pattern layer PI.

  In the partition portion of the insulating pattern layer PI, a through hole is provided at a position corresponding to the first electrode PE, or a slit is provided at a position corresponding to the column or row formed by the first electrode PE. . Here, as an example, the partition portion of the insulating pattern layer PI is provided with a through hole at a position corresponding to the first electrode PE.

  In addition, the spacer portion of the insulating pattern layer PI is composed of one layer opened at a plurality of locations, or is composed of a plurality of island-shaped portions separated from each other. When viewed from a direction perpendicular to the main surface of the substrate SUB, the area ratio of the spacer portion to the portion of the peripheral region located between the seal layer SS and the display region is the area ratio of the partition wall portion to the display region. Smaller than That is, the spacer portion has a smaller surface density when viewed from a direction perpendicular to the main surface of the substrate SUB than the partition wall portion.

  The insulating pattern layer PI is, for example, an organic insulating layer. The insulating pattern layer PI can be formed using, for example, a photolithography technique.

  An organic layer ORG including a light emitting layer is disposed on the first electrode PE. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, or blue. The organic layer ORG can further include layers other than the light emitting layer. For example, the organic layer ORG may further include a buffer layer that serves to mediate hole injection from the first electrode PE to the light emitting layer. The organic layer ORG can further include a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like.

  The insulating pattern layer PI and the organic layer ORG are covered with a light transmissive second electrode CE which is a front electrode. In this example, the second electrode CE is a cathode provided continuously in common with each pixel. For example, the second electrode CE is formed on the same layer as the video signal line DL through contact holes provided in the passivation film PS, the planarization layer FL, the light extraction layer OC, and the insulating pattern layer PI. It is electrically connected to electrode wiring (not shown). Each organic EL element OLED includes a first electrode PE, an organic layer ORG, and a second electrode CE.

  Each pixel PX includes an organic EL element OLED and a pixel circuit. In this example, the pixel circuit includes a drive control element DR, an output control switch SW1, a video signal supply control switch SW2, a diode connection switch SW3, and a capacitor C as shown in FIG. As described above, in this example, the drive control element DR and the switches SW1 to SW3 are p-channel TFTs.

  The drive control element DR, the output control switch SW1, and the organic EL element OLED are connected in series in this order between the first power supply terminal ND1 and the second power supply terminal ND2. In this example, the first power supply terminal ND1 is a high potential power supply terminal, and the second power supply terminal ND2 is a low potential power supply terminal.

  The gate of the output control switch SW1 is connected to the scanning signal line SL1. The video signal supply control switch SW2 is connected between the video signal line DL and the drain of the drive control element DR, and its gate is connected to the scanning signal line SL2. The diode connection switch SW3 is connected between the drain and gate of the drive control element DR, and the gate thereof is connected to the scanning signal line SL2. The capacitor C is connected between the gate of the drive control element DR and the constant potential terminal ND1 '.

  The sealing substrate CS is an insulating substrate having optical transparency such as a glass substrate. The sealing substrate CS is typically a flat plate shape. In this example, the sealing substrate CS is in contact with the partition wall portion and the spacer portion of the insulating pattern layer PI via the second electrode CE. Note that the second substrate CE may not be disposed on the spacer portion of the insulating pattern layer PI, and the sealing substrate CS and the spacer portion may be in direct contact with each other.

  As shown in FIG. 2, the seal layer SS is interposed between the array substrate AS and the sealing substrate CS. As shown in FIG. 1, the seal layer SS has a frame shape and surrounds the insulating pattern layer PI. As a material of the seal layer SS, for example, an adhesive or frit glass can be used.

  The sealing layer SS plays a role of sealing the organic EL element OLED together with the sealing substrate CS in addition to the role of bonding the sealing substrate CS to the array substrate AS. The space surrounded by the array substrate AS, the sealing substrate CS, and the seal layer SS is evacuated or filled with an inert gas or the like.

  In this organic EL display device, for example, each of the scanning signal lines SL1 and SL2 is line-sequentially driven. In a writing period in which a video signal is written to a certain pixel PX, first, a scanning signal for opening the switch SW1 is output as a voltage signal from the scanning signal line driver YDR to the scanning signal line SL1 to which the previous pixel PX is connected. Subsequently, a scanning signal for closing the switches SW2 and SW3 is output as a voltage signal to the scanning signal line SL2 to which the previous pixel PX is connected. In this state, the video signal line driver XDR outputs the video signal as a current signal to the video signal line to which the previous pixel PX is connected, and the gate-source voltage of the drive control element DR corresponds to the previous video signal. Set the size to Thereafter, a scanning signal for opening the switches SW2 and SW3 is output as a voltage signal from the scanning signal line driver YDR to the scanning signal line SL2 to which the previous pixel PX is connected, and then the scanning signal to which the previous pixel PX is connected. A scanning signal for closing the switch SW1 is output as a voltage signal to the line SL1.

  In the effective display period in which the switch SW1 is closed, a drive current having a magnitude corresponding to the gate-source voltage of the drive control element DR flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current.

  By the way, in the manufacture of the organic EL display device, when the array substrate AS and the sealing substrate CS are bonded together, the sealing substrate CS is attached to the array substrate AS at the position of the seal layer SS in order to achieve high adhesion. Press with a strong force against. Therefore, in this organic EL display device, the distance between the insulating substrate SUB and the sealing substrate CS at the position of the seal layer SS is between the insulating substrate SUB and the sealing substrate CS at a position corresponding to the center of the display region. Shorter compared to the distance. That is, in this organic EL display device, the sealing substrate CS is slightly bent so that the outer surface thereof is a convex surface.

  The present inventors have found that when the curvature at the position corresponding to the convex display region is large, striped display unevenness may occur in the display image. Then, by arranging the spacer portion in a portion sandwiched between the sealing layer SS and the display region in the peripheral region, the adhesion of the array substrate AS and the sealing substrate CS is not impaired, and the sealing substrate CS is not damaged. It has been found that the greatly bent portion can be limited only to the position corresponding to the peripheral region.

  In other words, the spacer portion serves to sufficiently widen the distance between the insulating substrate SUB and the sealing substrate CS at a position corresponding to the peripheral region. Therefore, it is possible to prevent the deformation of the sealing substrate CS due to the seal layer SS from reaching the portion corresponding to the display area.

  Further, since the surface density of the spacer portion is smaller than the surface density of the partition wall portion, the spacer portion is more easily deformed than the partition wall portion. Therefore, the sealing substrate CS can be appropriately deformed at a position corresponding to a portion sandwiched between the seal layer SS and the display region. For this reason, for example, the tension acting between the sealing substrate CS and the seal layer SS does not become excessively large. That is, even if the above structure is adopted, the adhesion between the array substrate AS and the sealing substrate CS is not impaired.

  Therefore, according to this aspect, it is possible to prevent the occurrence of striped display unevenness in the display image.

When viewed from a direction perpendicular to the main surface of the substrate SUB, the width W _{1 of the} spacer portion with respect to the portion located between the seal layer SS and the display region in the peripheral region is, for example, in the range of 1 mm to 5 mm. Within. If the width W ₁ of the spacer portion is small, can range to a portion the deformation of the sealing substrate CS due to the sealing layer SS is corresponding to the display area. In addition, when the width W _{1 of the} spacer portion is large, the adhesion between the array substrate AS and the sealing substrate CS may be insufficient.

  The distance L from the display area to the seal layer SS is, for example, 0.75 mm or more. When the distance L is short, a large tension acts between the sealing substrate CS and the seal layer SS, and the adhesion between the array substrate AS and the sealing substrate CS may be insufficient. The distance L has no upper limit, but is usually 1.5 mm or less.

The distance D ₁ between the insulating substrate SUB and the sealing substrate CS at the inner peripheral position of the seal layer SS, and the distance D between the insulating substrate SUB and the sealing substrate CS at the boundary position between the display region and the peripheral region. the difference D ₂ -D ₁ and ₂ is typically a 0.5μm or in the range of 10 [mu] m. When the difference D ₂ −D ₁ is within this range, sufficient adhesion can be realized.

Next, the second aspect of the present invention will be described.
The second mode is the same as the first mode except that the following structure is adopted for the array substrate AS. In other words, in this aspect, in the state where the array substrate AS and the sealing substrate CS are separated from each other, the height H ₁ of the spacer portion with respect to the main surface of the insulating substrate SUB is set to the height of the partition wall portion with respect to the main surface of the insulating substrate SUB. Lower than the height H ₂ . The height H ₁ is set higher than the distance D ₁ .

  In this way, as in the first aspect, the greatly bent portion of the sealing substrate CS can be limited only to the position corresponding to the peripheral region without impairing the adhesion between the array substrate AS and the sealing substrate CS. . That is, even in this aspect, it is possible to prevent the display image from causing striped display unevenness.

In order to make the height H ₁ of the spacer portion lower than the height H ₂ of the partition wall portion, for example, the following structure may be adopted.

  FIG. 6 is a cross-sectional view schematically showing an example of a structure that can be employed in the organic EL display device according to the second aspect of the present invention. The portion depicted in FIG. 6 corresponds to the portion depicted in FIG. 4 in the organic EL display device.

In the structure of FIG. 6, the distance between the spacer portion of the insulating pattern layer PI and the insulating substrate SUB is shorter than that of the structure of FIG. Here, as an example, the planarization layer FL and the light extraction layer OC are disposed only at positions corresponding to the display area, and are omitted at positions corresponding to the peripheral area. By adopting such a structure, the height H ₁ of the spacer part can be made lower than the height H ₂ of the partition part even when the thickness of the spacer part is equal to the thickness of the partition part.

The ratio of the difference and the distance D ₁ of the the height between H ₂ height _{H 1 (H 2 -H 1)} / D 1 , for example, in the range of 250 to 1000. When the ratio (H ₂ −H ₁ ) / D ₁ is large, the deformation of the sealing substrate CS due to the seal layer SS may reach a portion corresponding to the display region. When the ratio (H ₂ −H ₁ ) / D ₁ is small, the adhesion between the array substrate AS and the sealing substrate CS may be insufficient.

The distance L is set in the same manner as in the first mode, for example. Further, the ratio D ₁ / D ₂ between the distance D ₁ and the distance D ₂ is set in the same manner as in the first mode, for example.

1 is a plan view schematically showing an organic EL display device according to a first embodiment of the present invention. Sectional drawing along the II-II line of the organic electroluminescent display apparatus shown in FIG. Sectional drawing which expands and shows a part of organic EL display apparatus shown in FIG. FIG. 3 is an enlarged cross-sectional view showing another part of the organic EL display device shown in FIG. 2. FIG. 2 is an equivalent circuit diagram of the organic EL display device shown in FIG. 1. Sectional drawing which shows roughly an example of the structure employable with the organic electroluminescence display which concerns on the 2nd aspect of this invention.

Explanation of symbols

AS ... array substrate, CE ... second electrode, CS ... sealing substrate, DE ... drain electrode, DL ... video signal line, DR ... drive control element, FL ... flattening layer, G ... gate electrode, GI ... gate insulating film II ... interlayer insulating film, L ... border between display region and peripheral region, ND1 ... first power supply terminal, ND1 '... constant potential terminal, ND2 ... second power supply terminal, OC ... light extraction layer, OLED ... organic EL element ,
ORG: Organic layer, PE: First electrode, PI: Insulating pattern layer, PS: Passivation film, PSL ... Power supply line, PX ... Pixel, RF ... Reflective layer, SC ... Semiconductor layer, SE ... Source electrode, SL1 ... Scanning signal Line, SL2 ... Scanning signal line, SS ... Sealing layer, SUB ... Insulating substrate, SW1 ... Output control switch, SW2 ... Video signal supply control switch, SW3 ... Diode connection switch, UC ... Undercoat layer, XDR ... Video signal line driver YDR: Scanning signal line driver.

Claims (4)

An insulating substrate; an insulating pattern layer disposed on one main surface of the insulating substrate and provided with a plurality of openings; and disposed on the main surface of the insulating substrate at a position corresponding to the opening. A plurality of organic EL elements each covering a first electrode and a second electrode facing the first electrode and an organic material layer interposed between the first and second electrodes and covering the insulating pattern layer; Array substrate,
A sealing substrate facing the array substrate across the insulating pattern layer;
A seal layer interposed between the array substrate and the sealing substrate and surrounding the insulating pattern layer;
The insulating pattern layer includes a partition wall portion located in a display area, which is an area where the plurality of organic EL elements are arranged, and a spacer portion located in a peripheral area surrounding the display area,
Each facing surface of the partition wall portion and the spacer portion with the sealing substrate is in contact with the sealing substrate through a layer including the second electrode, or is in direct contact with the sealing substrate. And
When viewed from a direction perpendicular to the main surface of the insulating substrate, an area ratio of the spacer portion to a portion of the peripheral region located between the seal layer and the display region is the display region. A top emission organic EL display device having a smaller area ratio than that of the partition wall with respect to the organic EL display. An insulating substrate; an insulating pattern layer disposed on one main surface of the insulating substrate and provided with a plurality of openings; and disposed on the main surface of the insulating substrate at a position corresponding to the opening. A plurality of organic EL elements each covering a first electrode and a second electrode facing the first electrode and an organic material layer interposed between the first and second electrodes and covering the insulating pattern layer; Array substrate,
A sealing substrate facing the array substrate across the insulating pattern layer;
A seal layer interposed between the array substrate and the sealing substrate and surrounding the insulating pattern layer;
The insulating pattern layer includes a partition wall portion located in a display area, which is an area where the plurality of organic EL elements are arranged, and a spacer portion located in a peripheral area surrounding the display area,
Each facing surface of the partition wall portion and the spacer portion with the sealing substrate is in contact with the sealing substrate through a layer including the second electrode, or is in direct contact with the sealing substrate. And
In the state in which the array substrate and the sealing substrate are separated from each other, the spacer portion has a lower height than the main surface of the insulating substrate compared to the partition wall portion. Light-emitting organic EL display device.   The organic EL display device according to claim 1, wherein the sealing substrate is bent so that a peripheral edge portion of the sealing substrate becomes a convex surface.   The organic EL display device according to claim 1, wherein the seal layer is made of frit glass.

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