JP2007122845A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a testing time of a nonvolatile memory in which a multi-valued storage is carried out. <P>SOLUTION: The semiconductor memory has a plurality of memory banks and data buffers for storing information of two or more bits as a storage unit. In a test mode, control data which classify values having one value and values having other values among the values for every storage unit of the information held by the data buffers, are transferred to sense latches of the memory banks in parallel, and in the memory banks to which the control data is transferred, a decision is made whether the state obtained in a bit line by a selection of specified word lines coincides with the state obtained in the bit line on the basis of the transferred control data. Excluding the memory banks which the noncoincident result is received, the decision is made by transferring the control data in parallel to the sense latch of the corresponding memory bank, for classifying the values having separate one value and the values having other values among the values for every storage unit of the information held by the corresponding data buffer, then the discrimination of the memory banks which are made to be noncoincident in the result of decision, is attained from outside. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a test facilitating technique for supporting a device test by writing / reading data in a semiconductor memory having a nonvolatile memory cell for storing information according to a difference in threshold voltage, for example, a technique effective when applied to a flash memory. About.

  A nonvolatile memory cell capable of storing information according to a difference in threshold voltage can obtain a high threshold voltage by injecting electrons into the charge storage region (writing operation), and can emit electrons or inject holes (erase). A low threshold voltage can be obtained by (operation). In the write operation and the erase operation, the verify operation is performed so that the threshold voltage falls within a specified distribution range. In the verify operation, the lower skirt verify voltage for defining the lower skirt of the threshold voltage distribution and the upper skirt verify voltage for determining the upper skirt are used as the word line selection level. In the read operation of stored information, the stored information can be determined by giving a word line selection level between the high threshold voltage and the low threshold voltage to the memory gate. The read selection level is set to a level between the lower skirt verify voltage for the upper threshold voltage distribution and the upper skirt verify voltage for the lower threshold voltage distribution. Thus, a predetermined voltage margin is secured. In the device test, whether or not such a voltage margin is secured is inspected by writing and reading data. Since the amount of data that is input / output during testing is much larger than the number of bits of the external data input / output terminal that performs write data input and read data output with an external tester, it is usually used for device tests. It takes a long time.

  Patent Document 1 describes a test technique in a DRAM-based memory such as an SDRAM (Dynamic Random Access Memory). According to this, the SDRAM holds the write data in the holding circuit, writes the data in the holding circuit into the nonvolatile memory cell, and compares the data read from the memory cell after writing with the write data held in the holding circuit And the comparison result is output to the outside.

JP 2004-310918 A

  However, in the case of a DRAM-based memory, it is necessary to determine whether or not a read error occurs while changing the pattern of write data due to the nature of reading stored information through charge distribution between the storage capacitor and the bit line. Don't be. On the other hand, in a flash memory or the like that performs multi-level storage, it may be determined whether a voltage margin is ensured between the read determination level of adjacent threshold voltage distributions and the verify voltage of these threshold voltage distributions. Therefore, in the case of a non-volatile memory that performs multi-value storage, all the memory cells may be written with the same value and read out. It is not necessary to repeat the operation of writing and reading pattern data in all memory cells while changing pattern data such as marching patterns as in a DRAM-based memory. In this sense, Patent Document 1 does not consider shortening the test time focusing on a nonvolatile memory that performs multi-level storage. According to the study of the present inventor, in the case of a non-volatile memory such as a flash memory, the write data does not have to be an arbitrary pattern and may be a single data. It was clarified that the device test could be further shortened. In addition, in the case of DRAM-based memory, it is necessary to consider the uneven distribution of stored information and the dependency on the operating state of the surrounding circuit, so even in the case of multi-banks, a defective memory bank is detected on the way. After that, there are concerns that the bank will be hindered from being removed from the test. On the other hand, in the case of a non-volatile memory that performs multi-value storage, the present inventor has found that there is no such concern because it is only necessary to focus on the voltage margin between the read selection level and the verify voltage. .

  An object of the present invention is to reduce the test time of a non-volatile memory that performs multi-level storage.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A nonvolatile memory according to the present invention includes a plurality of memory banks (MBNK0 to MBNKn) capable of storing, as a storage unit, information of 2 bits or more per nonvolatile memory cell (QM), A data buffer (5) and a control circuit (11) are provided corresponding to each. The memory bank includes a plurality of bit lines (GBL0 to GBLj) connected to the data terminals of the nonvolatile memory cells, a sense latch (29) connected to each of the bit lines, and a selection terminal of the nonvolatile memory cells. And a plurality of word lines (WL0 to WLm) to be connected. The control circuit distinguishes between one having one value and another having a value among the storage units of the information held by the data buffers according to the designation of the first test mode. The control data is transferred in parallel to the sense latch of the corresponding memory bank, and the state obtained in the bit line by selecting the designated word line in each memory bank that has received the control data transfer is the transferred control data. Based on the above, it is determined whether or not the state obtained for the bit line matches. Further, the control circuit, except for the memory bank from which the determination result of the inconsistency is obtained, has another one of the values for each storage unit of the information held by each data buffer and other values. The determination is performed by transferring in parallel the control data for distinguishing the control data from the sense latches of the corresponding memory bank. Further, the control circuit makes it possible to identify from the outside the memory bank in which the determination results do not match.

  Based on the above, the control circuit takes the expected value data for the data written to the nonvolatile memory cell into the data buffer and then internally determines whether the stored data read from the nonvolatile memory cell matches the expected value data. It is not necessary to transfer all data read from the nonvolatile memory cell from the external terminal to the tester. Therefore, the test time can be shortened in the sense that the determination operation is performed internally. In particular, since the determination operation is performed in parallel in a plurality of memory banks, the multi-bank configuration also contributes to shortening the test time. Further, the memory bank in which an error has occurred due to the discrepancy determination result is thereafter excluded from the test target. Therefore, it is not necessary to take in the expected value data from the outside to the data buffer of the memory bank excluded from the test target, and the test time can be further shortened even if the multibank itself can operate in parallel. become.

  Due to the nature of the test, it is preferable that the determination result can be referred to from the outside. If at least a memory bank in which an error due to mismatching can be identified, at least the error bank becomes inoperable and can be used as a nonvolatile memory with a small storage capacity.

  For the control data, for example, data having the one value is data of the first logical value, and data having other values is data of the second logical value.

  The control circuit, for example, performs a memory discharge by selecting a word line of the designated memory cell, and then performs a selective discharge of a bit line by data of a second logic value among control data transferred to the sense latch. . When all the bit lines are discharged, it is determined that the state obtained for the bit line by the selection of the designated word line matches the state obtained for the bit line based on the transferred control data. To do.

  [2] As one specific form of the present invention, the semiconductor memory has a second test mode and / or a third test mode. In a flash memory or the like that performs multi-level storage, it is only necessary to determine whether a voltage margin is secured between the read determination level of adjacent threshold voltage distributions and the verify voltage of the voltage distribution with these threshold values. Therefore, in the case of a non-volatile memory that performs multi-value storage, all the memory cells may be written with the same value and read out. It is not necessary to repeat the operation of writing and reading pattern data in all memory cells while changing pattern data such as marching patterns as in a DRAM-based memory.

  Focusing on this, according to the designation of the second test mode, the control circuit sets the selected word line of each of the memory banks to a predetermined read word line selection level, whereby all the states obtained for the bit lines match. It is determined whether or not to perform the determination, and the memory bank in which the determination result is inconsistent can be identified from the outside. This second operation mode is suitable for testing the highest distribution and the lowest distribution among the threshold voltage distributions of multilevel storage.

  In response to the designation of the third test mode, the control circuit uses one of the adjacent read word line selection levels as the read word line selection level for the selected word line of each memory bank, thereby obtaining a bit line. It is determined whether or not all the states match, and the determination result can be referred to from the outside. In addition, for the memory banks in which the determination results that all coincide in the determination are obtained, the other of the adjacent read word line selection levels is set as the read word line selection level, and all the states obtained by the bit lines are thereby obtained. It is determined whether or not they match. Furthermore, it is possible to identify the memory bank in which the determination result is inconsistent from the outside. This third operation mode is suitable for testing a distribution located between the highest distribution and the lowest distribution among the threshold voltage distributions of the multilevel storage.

  In the second test mode and the third test mode, the same value is applied to all the memory cells to be tested for each determination (only one state of binary 11/10/00/01). Therefore, it is not necessary to transfer the expected value from the data buffer to the sense latch. The first test mode performs reading from the memory cell to the sense latch six times, whereas the second test mode requires only one time and the third test mode requires two times. Therefore, the second and third test modes can shorten the test time compared to the first test mode. Further, when the same value is written in all the memory cells in the chip, all the word lines in the string may be selected in parallel, so that the test time can be further shortened compared to the first test mode. it can.

  It is preferable to have a status register that holds information that makes it possible to identify a memory bank in which the determination results do not match so that they can be referenced from the outside.

  [3] The semiconductor memory may be provided with the second test mode and / or the third test mode without providing the first test mode. Further, at that time, the semiconductor memory may be a single bank.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the test time of the nonvolatile memory that performs multi-value storage can be shortened.

<Flash memory>
FIG. 1 shows a configuration of a flash memory which is an example of a semiconductor memory according to the present invention. The flash memory 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate (chip) such as single crystal silicon by a known MOS integrated circuit manufacturing method.

  The flash memory 1 includes a plurality of memory banks MBNK0 to MBNKn. Each of the memory banks MBNK0 to MBNKn includes a sense latch circuit (LAT) 4 corresponding to each of the memory arrays ARY0 to ARYn. Each of the memory arrays ARY0 to ARYn includes a plurality of strings STRG0 to STRGi. Each of the memory arrays ARY0 to ARYn has global bit lines GBL0 to GBLj common to the plurality of strings STRG0 to STRGi. The configuration of the string is illustrated in FIG. The string STRG0 has a plurality of nonvolatile memory cells QM arranged in a matrix. Although not particularly shown, the nonvolatile memory cell QM has an n-channel MOS structure in which a floating gate and a memory gate are overlapped via a gate oxide film on a channel formation region between a source and a drain. The non-volatile memory cell QM can have a different threshold voltage depending on the amount of electrons held by the floating gate. Here, the operation of injecting electrons into the floating gate is called a write operation, and the operation of emitting electrons or injecting holes is called an erase operation. The memory cells QM are connected in parallel for each column, and the common drains of the memory cells QM connected in parallel are selectively connected to the global bit lines GBL0 to GBLj via the isolation switch QD. The common source of the memory cells QM connected in parallel is selectively connected to the data line CD via the separation switch QD. In the row direction, word lines WL0 to WLm connected to the memory gates of the nonvolatile memory cells QM are arranged in units of rows. The separation switches QD and QS are switch-controlled by string selection signal lines STD and STS. The other strings STRG1 to STRGi are similarly configured.

  The word lines WL0 to WLm and the string selection signal lines STD and STS in each of the strings STRG0 to STRGi are driven by the X decoder and driver (XDEC / DRV) 2 of FIG. Which memory bank X decoder and driver 2 is activated and which word line of which string of the activated memory bank is selected is determined based on address information output from the bank and X selector (BXSEL) 3. The

  The global bit lines GBL0 to GBLj are connected to a sense latch circuit (SLAT) 4 and the sense latch circuit 4 is connected to a corresponding data buffer (DBUF) 5. The data buffer 5 is arranged for each memory bank. The sense latch circuit 4 has, for example, the number of sense latches (SL: see FIG. 5) corresponding to each global bit line GBL0 to GBLj, and the storage node of the sense latch is the input / output of the corresponding global bit line and the data buffer 5. Connect to the node. The sense latch senses and holds data read from the nonvolatile memory cells QM to the global bit lines GBL0 to GBLj in parallel, and internally transmits the data to the data buffer 5. Further, the sense latch holds the write data transferred from the data buffer 5 and controls voltage drive, precharge and discharge for the global bit lines GBL0 to GBLj. The other interface of the data buffer 5 is connected to an internal data bus 7 via a Y decoder and a Y gate (YDEC • YG) 6. The Y decoder and Y gate 6 decode the column address signal output from the column address counter (CACUNT) 8 and determine the column position of the data buffer to be conducted to the internal data bus 7. The column address counter 8 is capable of outputting column address signals that are sequentially updated by incrementing the address based on the initial value of the preset column address. As a result, data can be input / output to / from the outside via the data bus 7 with any column position of the data buffer 5. The multi-bit external input / output terminal I / O is also used as an address input terminal, data input terminal, data output terminal, and command input terminal. The multiplexer (MPX) 9 connects the data bus to the external input / output terminal I / O for data input / output. The multiplexer (MPX) 9 connects the external input / output terminal I / O to the page address buffer (PABUF) 10 when inputting the page address signal, and connects the external input / output terminal I / O to the column address counter 8 when inputting the column address signal. When the command is input, the external input / output terminal I / O is connected to the control circuit (CONT) 11.

The control circuit 11 includes a microprocessor (MPU) 13, a read only memory (ROM) 14, a coder (CMDDEC) 15 and a status register (SREG) 16 using commands. The control circuit 11 inputs an access control signal from the outside via the control signal buffer 17. The access control signals are a chip enable signal / CE, a read enable signal / RE, a write enable signal / WE, a command latch enable signal CLE, an address latch enable signal ALE, and a reset signal / RES. The input / output path selection by the address multiplexer 9 is controlled by distinguishing the data input, data output, address input, command input, etc. according to the combination of the levels of these access control signals. The input command is decoded by the command decoder 15. The microprocessor 13 controls the internal memory operation by transitioning to the execution of the corresponding processing routine using the decoding result as a vector. The contents of the processing routine are defined by the description of the program held in the ROM 14. When performing a memory operation that requires a long time such as writing or erasing, the control circuit 11 asserts a ready / busy signal (R / B) to notify the outside that it is busy.
The bank address and X address necessary for controlling the memory operation are set in the bank and X selector 3 by the control circuit 11 based on the page address stored in the page address buffer 10. Various operating voltages necessary for the memory operation are generated by the power supply circuit (PSPLY) 19 based on the external power supply voltages VCC and VSS. The generated operating voltage is selected by the control circuit 11 according to the internal memory operation and supplied to a necessary circuit. The all determination circuit (AJDG) 20 takes a logic such as NAND, OR, or NOR with respect to all the logical values of the global bit lines GBL1 to GBLj in a write verify operation or the like and outputs it to the control circuit 11.

Information storage of the nonvolatile memory cell utilizes the fact that the threshold voltage (Vth) of the memory cell changes according to the amount of charge stored in the floating gate as a charge holding region.
At this time, the threshold voltage of the memory cell is limited to a desired range according to the value of the stored data, and the threshold voltage distribution is called a memory threshold voltage distribution. For example, when 2-bit information is stored in one nonvolatile memory cell, four types of memory threshold voltage distributions corresponding to data “01”, “00”, “10”, and “11” as storage information are obtained. It is decided. In order to obtain these memory threshold voltage distributions, an erase operation for obtaining the storage information “11” is performed, and a write verify voltage applied to the word line during the subsequent write operation is set to three different voltages. These three kinds of voltages may be switched sequentially to perform the write operation in three steps. In the writing process, for example, 0V may be applied to a bit line selected for writing, 1V to a non-selected bit line, and 17V to a word line. Whether 0V or 1V is applied to the bit line is determined by the logical value of the write control data latched by the corresponding sense latch. Whether the sense latch is set to “1” or “0” during the write process is controlled according to the write data in the data buffer. In the erase operation, for example, the bit line is set to 2V, the selected word line applied voltage is set to -16V, and the unselected word line is set to 0V, and the erase operation is performed in units of word lines.

  FIG. 3 illustrates storage information of a nonvolatile memory cell and a threshold voltage distribution corresponding to the storage information. VWV11, VW10, VWV00, and VWV01 are lower skirt verify voltages corresponding to storage information “11”, “10”, “00”, and “01” at the time of write verify. VWE11, VWE10, and VWE00 are upper base verify voltages corresponding to the stored information “11”, “10”, and “00” at the time of write verify. The threshold voltage distribution corresponding to the stored information “11”, “10”, “00”, “01” is defined by these upper and lower verify voltages. VRWL, VRWM, and VRWH are read word line voltages (read determination levels) for enabling determination of stored information “11”, “10”, “00”, and “01” during a read operation. FIG. 4 shows specific examples of the upper skirt verify voltage, the lower skirt verify voltage, and the read word line voltage in FIG.

  In the read process, although not particularly limited, the read word line voltage is switched in the order of VRWM, VRWH, and VRWL. The logical value (logical value 0 when Vth> VRWM and logical value 1 when Vth <VRWM) obtained in the sense latch by setting the read word line voltage to VRWM determines the upper bits of the 2-bit storage information. Next, when the logical value obtained by setting the read word line voltage to VRWH is 0 (Vth> VRWH), the lower bit of the stored information is determined to be the logical value 1. Finally, when the logical value obtained by setting the read word line voltage to VRWL is 0 (Vth> VRWL), the lower bits of the stored information are logical values 0, and when the logical value is 1 (Vth <VRWL) The lower bit of the stored information is determined to be a logical value 1. In this way, the read word line level is switched three times, and the 2-bit stored information can be reproduced based on the data read sequentially three times by the latch circuit. Conversely, in the write operation, write control data is generated according to the 2-bit unit value of the write data held in the data buffer and applied to the sense latch, thereby forming a threshold voltage distribution corresponding to the 2-bit write data. Write processing is enabled at the timing. The logic for reproducing the 2-bit stored information and the logic for generating the write control data based on the 2-bit write data are provided in an interface portion with the sense latch circuit 4 in the data buffer 5 circuit, although not particularly shown. ing.

《Sense latch》
FIG. 5 shows an example of a sense latch (SL) 29 included in the sense latch circuit 4. In the figure, the p-channel MOS transistor is distinguished from the n-channel MOS transistor by adding an arrow to the base gate. The sense latch 29 includes a static latch 30 having SLP (Vdd) and SLN (Vss) as operation power supply nodes. One input / output node is a sense node SNS and the other input / output node is a reference node REF. The sense node SNS and the reference node REF correspond to the corresponding input of the input / output terminals IOR0, IOS0 to IORj, IOSj of the data buffer 5 via transfer gate MOS transistors 31, 32 that are switch-controlled by the transfer gate selection signal YS. It can be connected to the output terminal. The sense node SNS and the reference node REF are connected to a precharge power supply node FRSA via sense latch set MOS transistors 33 and 34 that are switch-controlled by signals RSAS and RSAR. In the operation of initializing the sense node SNS and the reference node REF before the start of the read operation, the levels of the signals RSAS and RSAR are different, so that the reference node REF is precharged to approximately half the level of the sense node SNS. The The sense node SES is connected to the ground potential of the circuit through a sense MOS transistor 35 and a sense enable MOS transistor 36 that is switch-controlled by a signal SENSE. The gate of the sense MOS transistor 35 is coupled to the corresponding global bit line among the global bit lines GBL0 to GBLj. The sense MOS transistor 35 is switch-controlled according to the level of the global bit line, and the sense MOS transistor 35 is turned on. The level of the sense node SNS is selectively inverted to a low level. In the sensing operation, a potential difference is formed between the sense node SNS and the reference node REF, and the MOS transistor 36 is cut off in the initial state. At the sense timing at which the global bit line can be changed, the MOS transistor 36 is turned on, the operation power is supplied to the power supply terminals SLP and SLN of the sense latch, and the sense operation is started. At this time, if the corresponding global bit line maintains a high level, the sense node SNS is inverted to a low level. At that time, if the corresponding global bit line changes from the high level to the low level, the sense node SNS is set to the high level. Thereby, the static latch 30 can detect and latch the storage information of the nonvolatile memory cell QM. FIG. 6 illustrates a timing chart of an operation for reading stored information. The static latch 30 can latch write data from the corresponding input / output terminal among the input / output terminals IOR0, IOS0 to IORj, IOSj.

  Sense node SNS is coupled to a corresponding global bit line among global bit lines GBL0 to GBLj through isolation MOS transistor 38 that is switch-controlled by signal TR. Global bit lines GBL0 to GBLj are connected to a precharge MOS transistor 44 for precharging them all at once. The precharge MOS transistor 44 is connected to a precharge power supply FRPC and is switch-controlled by a signal RPC. Further, each of the global bit lines GBL0 to GBLj includes an enable MOS transistor 40 and a select MOS transistor 41 that enable the corresponding global bit line to be selectively precharged or discharged. The enable MOS transistor 40 is connected to the corresponding global bit line, is switch-controlled by a signal PC, and is used for enable control as to whether or not the output of the selection MOS transistor 41 in the subsequent stage is transmitted to the corresponding global bit line. The selection MOS transistor 41 is switch-controlled according to the level of the reference node REF, and is turned on to conduct to the precharge / discharge power supply FPC. Precharging of the global bit line in read operation or the like is performed by precharging all bits through the MOS transistor 44. The current path of all bit precharge is illustrated in FIG. When the write data is latched in the static latch 30 in the write operation, when the reference node REF is at the high level, the corresponding global bit line is precharged in advance by the power supply FPC, and then the transistor 38 is turned on to set the reference node REF to the high level. To reach. The high level of the reference node REF becomes a write blocking voltage in the write unselected bit line. If the reference node REF is low level when the static latch 30 latches the write data, the corresponding global bit line reaches the low level of the reference node REF, and becomes the write voltage in the write selection bit line. FIG. 8 illustrates a current path for selective precharging by the MOS transistors 40 and 41. Further, by connecting the power supply FPC to the ground potential of the circuit, the corresponding global bit line can be selectively discharged via the MOS transistors 40 and 41 according to the logical value of the data held by the static latch 30. FIG. 9 illustrates a current path for selective discharge by the MOS transistor 41. The power supply FPC is constituted by a push-pull circuit represented by a CMOS inverter that receives a precharge / discharge control signal PDCNT as an input.

In FIG. 5, a MOS transistor 46 whose gate is coupled to the sense node SNS of each static latch 30 and a MOS transistor 47 whose gate is coupled to the reference node REF are discharge MOS transistors for making an all determination.
The MOS transistor 46 changes the signal ECS to the low level when the sense node SNS detects that the threshold voltage of the nonvolatile memory cell is lower than the word line level in the sense operation. The MOS transistor 47 changes the signal ECR to low level when the static latch 30 holds data for setting the reference node REF to high level. The signals ECR and ECS are supplied to the all determination circuit 20 corresponding to each memory bank. For example, each all determination circuit 20 includes a first logic circuit (NAND) 20A and a second logic circuit (NAND) 20B as illustrated in FIG. The first logic circuit (NAND) 20A takes NAND logic for the j + 1 bit signal ECS from the corresponding memory bank and returns the result NGS to the MPU 13. The second logic circuit (NAND) 20B takes NAND logic for the j + 1 bit signal ECR from the corresponding memory bank and returns the result NGR to the MPU 13.

<< First test mode >>
The flash memory 1 has several test modes for device testing. The test mode is designated by both or a combination of the access control signals and a predetermined test command. When the test mode is designated in the control circuit 11, the MPU 13 transitions to execution of a processing routine corresponding to the designated test mode type and performs a test operation. Here, the first to third test modes will be described.

  The first test mode is an operation mode for verifying whether or not the data read from the nonvolatile memory cell matches the expected value data when arbitrary test pattern data is written in the memory banks MBNK0 to MBNKn. is there. FIG. 11 generally shows a flowchart of the test operation in the first test mode. FIG. 12 illustrates a part of the test operation in detail. Here, although not particularly limited, after the test data is written in parallel to one word line of one string STRG in each of the memory banks MBNK0 to MBNKn, the write data remains in the data buffer 5. In the state, the first test mode is designated for the write data of the word line. This write operation and verification in the first test mode are sequentially performed for all the strings STRG0 to STRGj in the respective memory banks MBNK0 to MBNKn.

  FIG. 11 illustrates a processing flow in the first test mode for one word line of one string STRGi for all the memory banks MBNK0 to MBNKn. Before the first test mode is designated, arbitrary test data is written into the nonvolatile memory cells corresponding to one word line in the string STRGi of all the memory banks MBNK0 to MBNKn. In this write operation, the write verify is naturally performed after the write process. The write data at this time remains in the data buffer 5 as expected value data. In the first process STP1, control data is set in the sense latch 29 according to the data “11” from the data buffer 5, and the threshold voltages of the nonvolatile memory cells corresponding to the set sense latch 29 are data “11” and data “10”. It is verified whether or not it is lower than the read word line selection level VRWL. Details of the first process STP1 are realized by steps S1 to S14 in FIG. First, all the memory banks MBNK0 to MBNKn are activated (S0). Next, the control data “0” (REF = L [: low level], SNS = H [: high level]) is set in the sense latch at the position corresponding to the data “11” held by the data buffer 5, and the others The control data “1” (REF = H, SNS = L) is set in the sense latch at the position corresponding to the data (S1). Next, the selected word line to be tested is set to VRWL (S2), the separation switch QS of the target string is turned on (STS = H) (S3), and all bit precharge operations for all the global bit lines GBL1 to GBLj are performed. Perform (S4). When the all bit precharge operation is completed (S5), the separation switch QD of the target string is turned on (STD = H) for a certain period, and memory discharge for the global bit line is started (S6). That is, the nonvolatile memory cell whose threshold voltage is lower than the read word line selection level VRWL is turned on, and the global bit line connected to the memory cell is discharged. In the nonvolatile memory cell in which data “11” has been written first, if the voltage margin of the read determination level VRWL with respect to the upper skirt determination level VWE11 is as specified, the erase verify process for storing the data “11” fails. The non-volatile memory cell which is normally terminated without being turned on is turned on. However, if such a voltage margin is insufficient for the regulation, the nonvolatile memory cell is in the on state even if the erase verify process for storing the data “11” is normally terminated without fail. It may not be done. Thereafter, the separation transistors QS and QD are turned off and the memory discharge is completed (S7, S8). Next, selective discharge (see FIG. 9) is performed (S9). The target of the selected discharge is a global bit line connected to the high level reference node REF. That is, the global bit line connected to the sense latch at the position corresponding to the data other than the data “11” held in the data buffer 5 is selected as the target of the selective discharge. Therefore, if the voltage margin of the read determination level VRWL with respect to the upper skirt determination level VWE11 is as specified, all the global bit lines are in a discharged state after all bit precharge, memory discharge, and selective discharge. It should be. However, at this time, if there is a global bit line that is still in the precharged state, it causes a malfunction due to the voltage margin of the read determination level VRWL with respect to the upper skirt determination level VWE11 being smaller than specified. It means to say. The state of the global bit line can be obtained at the reference node REF of each sense latch by the sensing operation (ON operation of the MOS transistor 36) (S10). If there is no malfunction, the reference nodes REF of all the sense latches are set to a low level. If a malfunction due to the voltage margin occurs in the nonvolatile memory cell, the reference node REF is set to the high level. The state in which at least one reference node REF is at a high level is recognized by the MPU 13 based on the high level of the signal NGR by activating the all determination circuit 20B on the reference node REF side (S11). When the MPU 13 recognizes the occurrence of a malfunction, it sets an error flag in the status register 16 corresponding to the memory bank (fail bank) (S12). Then, the MPU 13 deactivates the fail bank (S13).

  In the next second process STP2, as shown in FIG. 11, control data is set in the sense latch 29 according to the data “10” from the data buffer 5, and the threshold value of the nonvolatile memory cell corresponding to the set sense latch 29 is set. It is verified whether or not the voltage is above the read word line selection level VRWL between the data “10” and “11”. Specifically, the processing of S14 to S26 in FIG. 12 is performed. In this process, the target data is “10” (S14), the selective precharge is performed instead of the selective discharge (S22), and all the global bit lines GBL0 to GBLj are maintained in the charged state after the sensing operation. Is determined using an all determination circuit on the sense node SNS side (S24). That is, in step S14, the control data “0” (REF = L [: low level], SNS = H [: high level]) is set in the sense latch at the position corresponding to the data “10” held in the data buffer 5. The control data “1” (REF = H, SNS = L) is set in the sense latch at the position corresponding to the other data. In the selected precharge in step S22 (see FIG. 8), the target is a global bit line connected to the high-level reference node REF. That is, the global bit line connected to the sense latch at the position corresponding to the data “11” held in the data buffer 5 is selected as a target for selective precharge. The global bit lines connected to the sense latches at the positions corresponding to the data “00” and “01” held in the data buffer 5 are not discharged in the memory discharge (S19, S20) and maintain the precharged state. Therefore, if the voltage margin of the read determination level VRWL with respect to the lower end determination level VWV10 of the data “10” is as specified, all the global bit lines are pre-charged after all bit precharge, memory discharge, and selective precharge. Should be charged. However, if there is a discharged global bit line at this time, it means that a malfunction has occurred due to the voltage margin of the read determination level VRWL with respect to the lower skirt determination level VWV10 being smaller than the specified level. The state of the global bit line can be obtained in each sense latch by a sense operation (ON operation of the MOS transistor 36) (S23). If there is no malfunction, the sense nodes SNS of all the sense latches are set to the low level. If a malfunction due to the voltage margin occurs in the nonvolatile memory cell, the sense node SNS is set to the high level. The state where at least one sense node SNS is set to the high level is recognized by the MPU 13 based on the high level of the signal NGS by activating the all determination circuit 20A on the sense node side (S24). When the MPU 13 recognizes the occurrence of a malfunction, it sets an error flag in the status register 16 corresponding to the memory bank (fail bank) (S25). Then, the MPU 13 deactivates the fail bank (S26).

  In the next third process STP3, as shown in FIG. 11, the control data is set from the data buffer 5 to the sense latch 29 according to the data “10”, and the threshold value of the nonvolatile memory cell corresponding to the set sense latch 29 is set. It is verified whether or not the voltage is lower than the read word line selection level VRWM between data “10” and “00”. In the basic process, the selection discharge is performed in the same manner as the first process, and then the malfunction is detected using the all determination circuit on the reference node REF side.

  In the next fourth process STP4, as shown in FIG. 11, the control data is set from the data buffer 5 to the sense latch 29 according to the data “00”, and the threshold value of the nonvolatile memory cell corresponding to the set sense latch 29 is set. It is verified whether or not the voltage is higher than the read word line selection level VRWM between data “10” and “00”. As in the second process, the basic process is performed by performing selective precharge and then detecting the malfunction using the all determination circuit on the sense node SNS side.

  In the next fifth process STP5, as shown in FIG. 11, the control data is set from the data buffer 5 to the sense latch 29 according to the data “00”, and the threshold value of the nonvolatile memory cell corresponding to the set sense latch 29 is set. It is verified whether or not the voltage is lower than the read word line selection level VRWH between data “00” and “10”. In the basic process, the selection discharge is performed in the same manner as the first process, and then the malfunction is detected using the all determination circuit on the reference node REF side.

  Finally, in the sixth process STP6, as shown in FIG. 11, control data is set from the data buffer 5 to the sense latch 29 in accordance with the data “01”, and the threshold value of the nonvolatile memory cell corresponding to the set sense latch 29 is set. It is verified whether or not the voltage is higher than the read word line selection level VRWH between data “00” and “01”. As in the second process, the basic process is performed by performing selective precharge and then detecting the malfunction using the all determination circuit on the sense node SNS side.

  The process shown in FIG. 11 can be repeated for each multi-bank word line in which test patterns are sequentially written. When all the memory banks become fail banks on the way, it is determined that the flash memory is completely defective at that point, and the test may be terminated. If a failure is detected in some of the memory banks, the fail bank may be made inoperable and may be used as a nonvolatile memory with a small storage capacity.

  According to the first test mode, the control circuit 11 takes the expected value data for the data written in the nonvolatile memory cell QM into the data buffer 5, and then stores the stored data and the expected value data in the nonvolatile memory cell QM. Whether or not they match can be determined internally. It is not necessary to transfer all data read from the nonvolatile memory cell QM from the external terminal I / O to the tester. Therefore, the test time can be shortened in the sense that the determination operation is performed internally. In particular, since the determination operation is performed in parallel in the plurality of memory banks MBNK0 to MBNKn, this point also contributes to shortening the test time in the multi-bank configuration. Further, the fail bank that is clarified from the determination result of the mismatch is thereafter excluded from the test target. Therefore, it is not necessary to take in the expected value data from the outside to the data buffer of the memory bank excluded from the test target, and the test time can be further shortened even if the multibank itself can operate in parallel. become.

<< 2nd and 3rd test modes >>
The second and third test modes are test modes in which all the memory cells to be tested are written with a specific value determined according to the test mode, and the data buffer stores expected value data. This does not require any internal transfer to the sense latch. In the second and third test modes, it is only necessary to determine whether or not the voltage margin between the read determination level of the adjacent threshold voltage distribution and the verify voltage of the threshold voltage distribution is ensured in the flash memory that performs multi-level storage. It pays attention to. In short, in the case of a non-volatile memory that performs multi-value storage, all the memory cells to be tested may be written with the same value and read out. It is not necessary to repeat the operation of writing and reading pattern data in all memory cells while changing pattern data such as marching patterns as in a DRAM-based memory.

  As illustrated in FIGS. 13 and 14, the second test mode includes a test mode (VRWL lower test mode) for checking whether all bits in the selected word are below the read determination level VRWL. 15 and 16, the test mode is roughly divided into a test mode (VRWH upper test mode) for checking whether or not all bits in the selected word are above the read determination level VRWH. As illustrated in FIGS. 17 and 18, the third test mode is a test mode (VRWL-VRWM test) for checking whether all bits in the selected word are between the read determination levels VRWL and VRWM. Mode) and a test mode (VRWM-VRWH test mode) for checking whether all the bits in the selected word are between the read determination levels VRWM and VRWH, as illustrated in FIGS. It is divided roughly into.

  In the VRWL lower test mode, the same data “11” write process and write verify process are completed in advance in all the nonvolatile memory cells to be tested in the memory blocks MBLK0 to MBLKn. When the VRWL lower test mode is designated, first, all memory banks MBNK0 to MBNKn are activated as illustrated in FIG. 14 (S30). Next, the selected word line to be tested in each memory bank is set to VRWL (S31), the target string separation switch QS is turned on (STS = H) (S32), and all the global bit lines GBL1 to GBLj are all set. A bit precharge operation is performed (S33). When the all-bit precharge operation is completed (S24), the separation switch QD of the target string is turned on (STD = H) for a certain period to start memory discharge for the global bit line (S35). That is, the nonvolatile memory cell whose threshold voltage is lower than the read word line selection level VRWL is turned on, and the global bit line connected to the memory cell is discharged. In the nonvolatile memory cell in which data “11” has been written first, if the voltage margin of the read determination level VRWL with respect to the upper skirt determination level VWE11 is as specified, the erase verify process for storing the data “11” fails. The non-volatile memory cell which is normally terminated without being turned on is turned on. However, if such a voltage margin is insufficient for the regulation, the nonvolatile memory cell is in the on state even if the erase verify process for storing the data “11” is normally terminated without fail. It may not be done. Thereafter, the separation transistors QS and QD are turned off and the memory discharge is finished (S36, S37). Next, the state of the global bit line can be obtained at the reference node REF of each sense latch by a sensing operation (ON operation of the MOS transistor 36) (S38). If there is no malfunction due to the voltage margin, the reference nodes REF of all the sense latches are set to a low level. If a malfunction due to the voltage margin occurs in the nonvolatile memory cell, the reference node REF is set to the high level. The state in which at least one reference node REF is at a high level is recognized by the MPU 13 based on the high level of the signal NGR by activating the all determination circuit 20B on the reference node REF side (S39). When the MPU 13 recognizes the occurrence of malfunction, it sets an error flag in the status register 16 corresponding to the memory bank (fail bank) (S40).

  In the VRWH upper test mode, the same data “01” write processing and write verify processing are completed in advance in all the nonvolatile memory cells to be tested in the memory blocks MBLK0 to MBLKn, and all the normally written flash memories are set as test targets. To do. When the VRWH upper test mode is designated, the processing of S50 to S60 is performed as illustrated in FIG. This process is different from the process of FIG. 14 in that the target data is “01”, VRWH is used for the word line selection level, and all the global bit lines GBL0 to GBLj are kept charged after the sensing operation. It is different from using the all determination circuit on the reference node REF side to determine whether or not there is. If the voltage margin of the read determination level VRWH with respect to the lower end determination level VWV01 of the data “01” is as specified, all the global bit lines should be in a precharged state. However, if there is a global bit line in a discharged state at this time, it means that a malfunction has occurred due to the voltage margin of the read determination level VRWH with respect to the lower skirt determination level VWV01 being smaller than the standard. The state of the global bit line can be obtained in each sense latch by a sense operation (ON operation of the MOS transistor 36) (S58). If there is no malfunction, the sense nodes SNS of all the sense latches are set to the low level. If a malfunction due to the voltage margin occurs in the nonvolatile memory cell, the sense node SNS is set to the high level. The state in which at least one sense node SNS is set to the high level is recognized by the MPU 13 based on the high level of the signal NGS by activating the all determination circuit 20A on the sense node SNS side (S59). When the MPU 13 recognizes the occurrence of malfunction, it sets an error flag in the status register 16 corresponding to the memory bank (fail bank) (S60).

  In the test mode between VRWL and VRWM, the same data “10” write process and the write verify process are completed in advance in all the nonvolatile memory cells of all the memory blocks MBLK0 to MBLKn, and all the normally written flash memories are subjected to the test. . When the VRWL-VRWM test mode is designated, the processing of S70 to S92 is performed as illustrated in FIG. The processing in steps S70 to S80 in FIG. 18 is the same as the processing in steps SS50 to S60 in FIG. 16 except that the word line selection level is set to VRWL. After step S80 in FIG. 18, processing for deactivating the fail bank is performed (S81), and the processing of S82 to S92 is continued thereafter. The processes of S82 to S92 are the same as steps S31 to S40 of FIG. 14 except that the word line selection level is set to VRWM.

  In the test mode between VRWM and VRWH, the same data “00” write process and the write verify process are completed in advance in all the nonvolatile memory cells of all the memory blocks MBLK0 to MBLKn, and all the normally written flash memories are tested. . When the VRWM-VRWH test mode is designated, the processing of S100 to S122 is performed as illustrated in FIG. The processing in steps S100 to S111 in FIG. 20 is the same as the processing in steps S70 to S81 in FIG. 18 except that the word line selection level is set to VRWM (S102). The processing in steps S112 to S122 in FIG. 20 is the same as that in steps S82 to S92 in FIG. 18 except that the word line selection level is set to VRWH (S112).

  The second test mode is suitable for testing the highest distribution and the lowest distribution among the threshold voltage distributions of multilevel storage. The third test mode is suitable for testing a distribution located between the highest distribution and the lowest distribution among the threshold voltage distributions of the multilevel storage. In the second test mode and the third test mode, since the same value is written in all the memory cells to be tested for each determination, the expected value from the data buffer to the sense latch is set. There is no need to transfer the corresponding data. Also, the number of readings is six in the first test mode, whereas it is one in the second test mode and two in the third test mode. Accordingly, the second and third test modes can shorten the test time compared to the first test mode. Further, when the same value is written in all the memory cells in the chip, all the word lines need only be selected in parallel, so that the test time can be further shortened compared to the first test mode.

  The fourth test mode will be described with reference to FIGS. 21A to 21E. In the first test mode to the third test mode, the order of data reading is different from that of the normal reading operation. Therefore, there is a difference in the remaining charge amount of the bit line in the reading operation, and data reading is performed by the current sense method. It is also conceivable that a read malfunction occurs. In the first to third test modes, verify reading is performed using the verify voltage. However, since it is necessary to generate a plurality of verify voltages in addition to the normal read voltage, the voltage generation circuit is large. It is possible to increase the scale. In the fourth test mode, verification is performed by a normal read operation.

  FIG. 21A shows a normal read operation. In a normal read operation, a read voltage VRWM is applied to the word line WL, and memory discharge is performed by extracting precharged charges from a bit line connected to a memory cell whose threshold voltage is lower than VRWM. As a result, the upper bits of the multi-value distribution are read out differently. The read data from each sense amplifier is latched in the sense latch and transferred to the upper bit buffer.

  Subsequently, the read voltage VRWH is applied to the word line WL, and memory discharge is performed to extract charges from the bit line connected to the memory cell whose memory cell threshold voltage is lower than VRWH, and the read data from each sense amplifier is sense latched. Latch on.

  Finally, a read voltage VRWL is applied to the word line WL, and memory discharge is performed to extract charges from the bit line connected to the memory cell whose memory cell threshold voltage is lower than VRWL. Simultaneously with the memory discharge or following the memory discharge, the bit line corresponding to the cell whose threshold voltage is higher than VRWH when read by VRWH is selectively discharged. As a result, the lower bits of the multi-value distribution are read out differently. Thereafter, the read data from each sense amplifier is latched in the sense latch and transferred to the lower bit buffer.

  Multi-value data is determined by the above processing.

  FIG. 21B shows a verify operation when it is expected that “11” data is written in all the memory cells, that is, an erased state.

  First, a read voltage VRWM is applied to the word line WL, and memory discharge is performed to extract precharged charges from bit lines connected to memory cells whose memory cell threshold voltage is lower than VRWM. Since the value stored in the memory cell is a threshold voltage state lower than the read voltage VRWM, all the bit lines are discharged, and all the bit lines are in the discharged state by performing all determination on the reference side. Can be discriminated.

  Subsequently, a read voltage VRWH is applied to the word line WL to perform a read operation. At this time, as in FIG.

  Finally, the read voltage VRWL is applied to the word line WL, and the memory discharge is performed by extracting the precharged charge from the bit line connected to the memory cell whose memory cell threshold voltage is lower than VRWL. Simultaneously with the memory discharge or subsequent to the memory discharge, the bit line corresponding to the cell whose threshold voltage of the memory cell is higher than VRWH when read by VRWH is selectively discharged. However, since the value stored in the memory cell is a threshold voltage state lower than VRWL, there is no bit line discharged by the selective discharge, but all the bit lines are discharged by the memory discharge, and the reference side By performing the all determination, it is possible to determine that all the bit lines are in the discharge state.

  Since all the bit lines are in the discharged state by all determination when the read voltage VRWM is applied, and all the bit lines are in the discharged state by all determination when the read voltage VRWL is applied, they are stored in the memory cell. It can be determined that the existing value is “11”.

  FIG. 21C shows a verify operation when it is expected that “10” data is written in all the memory cells.

  First, a read voltage VRWM is applied to the word line WL, and memory discharge is performed to extract precharged charges from bit lines connected to memory cells whose memory cell threshold voltage is lower than VRWM. Since the value stored in the memory cell is in the threshold voltage state lower than the read voltage VRWM, all the bit lines are discharged, and all bit lines are in the discharged state by performing all determination on the reference side. Can be distinguished.

  Subsequently, the read voltage VRWH is applied to the word line WL to perform a read operation, and the read result is held in the sense amplifier.

  Then, the memory cell is discharged by applying the read voltage VRWL to the word line WL and extracting the precharged charge from the bit line connected to the memory cell whose memory cell threshold voltage is lower than VRWL. Simultaneously with the memory discharge or subsequent to the memory discharge, the bit line corresponding to the cell whose threshold voltage of the memory cell is higher than VRWH when read by VRWH is selectively discharged. Since the value stored in the memory cell is in a threshold voltage state higher than the read voltage VRWL, all the bit lines are not discharged by the memory discharge. Further, since the threshold voltage of the memory cell is lower than VRWH, it is not discharged even by selective discharge. Therefore, it is possible to determine that all the bit lines are in the charged state by performing the all determination on the sense side.

  Since all the bit lines are in the discharged state by all determination when the read voltage VRWM is applied, and all the bit lines are in the charged state by all determination when the read voltage VRWL is applied, they are stored in the memory cell. It can be determined that the existing value is “10”.

  FIG. 21D shows a verify operation when it is expected that “00” data is written in all the memory cells.

  First, a read voltage VRWM is applied to the word line WL, and memory discharge is performed to extract precharged charges from bit lines connected to memory cells whose memory cell threshold voltage is lower than VRWM. Since the value stored in the memory cell is a threshold voltage state higher than the read voltage VRWM, all the bit lines are not discharged, and all the bit lines are in a charged state by performing an all determination on the sense side. Can be discriminated.

  Subsequently, the read voltage VRWH is applied to the word line WL to perform a read operation, and the read result is held in the sense amplifier.

  Then, the memory cell is discharged by applying the read voltage VRWL to the word line WL and extracting the precharged charge from the bit line connected to the memory cell whose memory cell threshold voltage is lower than VRWL. Simultaneously with the memory discharge or subsequent to the memory discharge, the bit line corresponding to the cell whose threshold voltage of the memory cell is higher than VRWH when read by VRWH is selectively discharged. Since the value stored in the memory cell is in the threshold voltage state lower than the read voltage VRWH, all the bit lines are not discharged by the selective discharge, and all the bit lines are in the threshold voltage state higher than the read voltage VRWL. Since the bit lines are not discharged by the memory discharge, it is possible to determine that all the bit lines are in the charged state by performing the all determination on the sense side.

  It is determined that all bit lines are in a charged state by all determination when the read voltage VRWM is applied, and it is determined that all bit lines are in a charged state by all determination when the read voltage VRWL is applied. Thus, it can be determined that the value stored in the memory cell is “00”.

  FIG. 21E shows a verify operation when it is expected that “01” data is written in all the memory cells.

  First, a read voltage VRWM is applied to the word line WL, and memory discharge is performed to extract precharged charges from bit lines connected to memory cells whose memory cell threshold voltage is lower than VRWM. Since the value stored in the memory cell is a threshold voltage state higher than the read voltage VRWM, all the bit lines are not discharged, and all the bit lines are in a charged state by performing an all determination on the sense side. Can be discriminated.

  Subsequently, the read voltage VRWH is applied to the word line WL to perform a read operation, and the read result is held in the sense amplifier.

  Then, the memory cell is discharged by applying the read voltage VRWL to the word line WL and extracting the precharged charge from the bit line connected to the memory cell whose memory cell threshold voltage is lower than VRWL. Simultaneously with the memory discharge or subsequent to the memory discharge, the bit line corresponding to the cell whose threshold voltage of the memory cell is higher than VRWH when read by VRWH is selectively discharged. Since the value stored in the memory cell is in the threshold voltage state higher than the read voltage VRWH, it is not discharged by the memory discharge, but is discharged by the selective discharge. Therefore, it is possible to determine that all the bit lines are in the discharge state by performing the all determination on the reference side.

  It is determined that all the bit lines are in the charged state by all determination when the read voltage VRWM is applied, and it is determined that all the bit lines are in the discharged state by all determination when the read voltage VRWL is applied. Thus, it can be determined that the value stored in the memory cell is “01”.

  This fourth test mode eliminates the need to generate a verify voltage different from the read voltage by using a normal read sequence and an all determination circuit, thereby reducing the number of voltage levels to be adjusted. In addition, the influence of the remaining charge amount of the bit line depending on the reading order can be eliminated. In addition, since the normal reading sequence is used, the reading in the fourth test mode is the same as the time required for the normal reading, or a test in a shorter time than that by determining by all determination. It becomes possible.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the information storage of the nonvolatile memory cell is not limited to four values, and may be multi-value storage such as eight values or binary storage. The nonvolatile memory cell is not limited to a stack structure having a floating gate. A structure having a charge trapping insulating film such as a silicon nitride film in the charge storage region may also be used. Further, the present invention is not limited to the stack structure, and may be a non-volatile memory cell having a split gate structure having a select transistor portion and a memory transistor portion in series. The configuration of the memory array may be a NAND type in which memory cells are connected in series to form a string. Further, the string configuration, the bank configuration, and the like are not limited to the above, and can be changed as appropriate. The present invention is not limited to a single flash memory. The present invention can be widely applied to semiconductor integrated circuits such as microcomputers equipped with nonvolatile memories. Alternatively, the first test mode may be performed after test data is written in advance in all the nonvolatile memory cells in all the memory banks. The second and third test modes are not limited to performing the same data in advance in the memory cells of all memory banks. For example, the same data is written in some strings of all memory banks. You may go in the state.

1 is a block diagram of a flash memory which is an example of a semiconductor memory according to the present invention. It is a circuit diagram which shows an example of the string which comprises a memory array. It is a characteristic view which shows the memory | storage information of a non-volatile memory cell, and threshold voltage component distribution corresponding to it. FIG. 4 is an explanatory diagram illustrating specific examples of an upper skirt verify voltage, a lower skirt verify voltage, and a read word line voltage in FIG. 3. It is a circuit diagram showing an example of a sense latch included in the sense latch circuit. It is a timing diagram of read-out operation. It is a circuit diagram which shows the electric current path | route of all the bit precharges. It is a circuit diagram which shows the electric current path | route of selective precharge. It is a circuit diagram which shows the electric current path of selective discharge. It is a block diagram which shows an example of an all determination circuit. It is a flowchart which shows the test operation by 1st test mode generally. It is a flowchart which illustrates in detail a part of test operation by 1st test mode. It is a schematic explanatory drawing of VRWL lower side test mode which is an example of 2nd test mode. It is an operation | movement flowchart by the VRWL lower side test mode. It is a schematic explanatory drawing of the VRWH upper side test mode which is another example of a 2nd test mode. It is an operation | movement flowchart by VRWH upper side test mode. It is a schematic explanatory drawing of the test mode between VRWL-VRWM which is an example of 3rd test mode. It is an operation | movement flowchart by the test mode between VRWL-VRWM. It is a schematic explanatory drawing of the test mode between VRWM-VRWH which is another example of 3rd test mode. It is an operation | movement flowchart by the test mode between VRWM-VRWH. It is a schematic explanatory drawing of a 4th test mode. It is a schematic explanatory drawing of a 4th test mode. It is a schematic explanatory drawing of a 4th test mode. It is a schematic explanatory drawing of a 4th test mode. It is a schematic explanatory drawing of a 4th test mode.

Explanation of symbols

1 Flash memory
MBNK0-MBNKn Memory bank ARY0-ARYn Memory array STRG0-STRGi String GBL0-GBLj Global bit line QM Non-volatile memory cell WL0-WLm Word line 2 X decoder and driver (XDEC / DRV)
3 Bank and X selector (BXSEL)
4 Sense latch circuit (SLAT)
5 Data buffer (DBUF)
6 Y decoder and Y gate (YDEC / YG)
7 Internal data bus 8 Column address counter (CACUNT)
9 Multiplexer (MPX)
10 page address buffer (PABUF)
11 Control circuit (CONT)
13 Microprocessor (MPU)
14 Read-only memory (ROM)
15 Commander (CMDDEC) with command
16 Status register (SREG)
19 Power supply circuit (PSPLY) 19
20 All judgment circuit (AJDG)
29 sense latch (SL)
SNS Sense node REF Reference node 30 Static latch 40, 41 Select precharge / select discharge MOS transistor 44 All bit line precharge MOS transistors

Claims (11)

A plurality of memory banks capable of storing information of 2 bits or more per nonvolatile memory cell as a storage unit, a data buffer provided corresponding to each of the memory banks, and a control circuit;
The memory bank includes a plurality of bit lines connected to data terminals of the nonvolatile memory cells, a sense latch connected to the respective bit lines, and a plurality of word lines connected to selection terminals of the nonvolatile memory cells. Have
The control circuit distinguishes between one having one value and another having a value among the storage units of the information held by the data buffers according to the designation of the first test mode. The control data is transferred in parallel to the sense latch of the corresponding memory bank, and the state obtained in the bit line by selecting the designated word line in each memory bank that has received the control data transfer is the transferred control data. Of the information stored in each data buffer, except for the memory bank in which the determination result is inconsistent. Control data for distinguishing between one having another value and another having another value is transferred in parallel to the sense latch of the corresponding memory bank, and the determination is performed. But the non-volatile memory that allows identify the memory bank that was a mismatch from the outside.   2. The nonvolatile memory according to claim 1, wherein the control data having the one value is data of the first logical value, and the control data having the other value is data of the second logical value.   The control circuit performs a memory discharge by selecting a word line of the designated memory cell, and then performs a selective discharge of bit lines according to the second logic value data among the control data transferred to the sense latch. And determining that the state obtained in the bit line by selection of the designated word line coincides with the state obtained in the bit line based on the transferred control data. The nonvolatile memory according to 2.   The control circuit sets all memory cells connected to the selected word line of each memory bank to the first state according to the designation of the second test mode, and the voltage applied to the selected word line 2 is a predetermined read word line selection level, whereby it is determined whether or not the states obtained in the bit lines all match, and the memory bank in which the determination results do not match can be identified from the outside. Non-volatile memory.   In response to the designation of the third test mode, the control circuit sets one of the adjacent read word line selection levels as the read word line selection level as the voltage applied to the selected word line of each memory bank, To determine whether or not all the states obtained in the bit lines match, and to make it possible to refer to the determination result from the outside, and further to the adjacent memory bank for which the determination result that all match in the determination is obtained. The other read word line selection level is set as the read word line selection level, and it is determined whether or not all the states obtained in the bit lines match, and the memory bank in which the determination result does not match can be identified from the outside. The nonvolatile memory according to claim 4.   The non-volatile memory according to claim 5, further comprising a status register that holds information enabling identification of the memory bank in which the determination results are inconsistent so that the information can be referred to from outside. A memory bank capable of storing, as a storage unit, information of 2 bits or more per nonvolatile memory cell, and a control circuit;
The control circuit sets the voltage applied to all the selected word lines of the memory bank to a predetermined read word line selection level according to the designation of the second test mode, and all the states obtained for the bit lines are thereby obtained. A non-volatile memory that determines whether or not they match and makes the determination result referable from the outside. A memory bank capable of storing, as a storage unit, information of 2 bits or more per nonvolatile memory cell, and a control circuit;
In response to the designation of the third test mode, the control circuit sets one of the adjacent read word line selection levels as a read word line selection level as a voltage applied to all the selected word lines of the memory bank, thereby It is determined whether or not all the states obtained in the bit lines match, and the determination result can be referred to from the outside. When a determination result that matches all in the determination is obtained, the adjacent read word line selection is further performed. A non-volatile memory in which the other of the levels is set as a read word line selection level, thereby determining whether or not all the states obtained in the bit lines match, and allowing the determination result to be referred to from the outside. A plurality of memory banks capable of storing information of 2 bits or more per nonvolatile memory cell as a storage unit, and a control circuit;
In response to the designation of the third test mode, the control circuit sets one of the adjacent read word line selection levels as the read word line selection level for all the word lines of each memory bank, thereby obtaining the bit lines. It is determined whether or not all the states match, the determination result can be referred to from the outside, and the adjacent read word line selection level is further applied to the memory bank in which the determination result that matches all in the determination is obtained. A non-volatile memory in which the other word line is set to a read word line selection level, thereby determining whether or not all the states obtained in the bit lines match, and the memory bank in which the determination result does not match can be identified from the outside. A plurality of memory banks capable of storing information of 2 bits or more per nonvolatile memory cell as a storage unit, a data buffer provided corresponding to each of the memory banks, and a control circuit;
The memory bank includes a plurality of bit lines connected to data terminals of the nonvolatile memory cells, a sense latch connected to the respective bit lines, and a plurality of word lines connected to selection terminals of the nonvolatile memory cells. Have
The control circuit distinguishes between one having one value and another having a value among the storage units of the information held by the data buffers according to the designation of the first test mode. The control data is transferred in parallel to the sense latch of the corresponding memory bank, and the state obtained in the bit line by selecting the designated word line in each memory bank that has received the control data transfer is the transferred control data. A first determination operation is performed to determine whether or not the state obtained for the bit line matches with
The control circuit further provides another one of the values for each storage unit of the information held by each data buffer for a memory bank that has obtained a determination result that matches the state obtained for the bit line. Control data for distinguishing between those having other values and those having other values is transferred in parallel to the sense latches of the corresponding memory banks, and the designated memory is transferred to each memory bank that has received the control data. Performing a second determination operation for determining whether or not a state obtained in the bit line by selecting the word line of the cell matches a state obtained in the bit line based on the transferred control data;
A non-volatile memory that makes it possible to identify from the outside a memory bank in which the determination results do not match in the first determination operation and the second determination operation.   The non-volatile memory according to claim 10, further comprising a status register that holds information for identifying a memory bank in which the determination result does not match between the first determination operation and the second determination operation so that the information can be referred to from the outside.

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