JP2007122335A - Electronic circuit with time constant circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To utilize a component comprising a time constant circuit which has finished a role as the time constant circuit for a new role different from the time constant circuit. <P>SOLUTION: In an electronic circuit with the time constant circuit 11 which is constituted of a combination of a resistor R1 and a capacitor C1 and outputs a delay signal after elapse of a period equivalent to a time constant from an optional reference time period, a switch 14 connected with the time constant circuit 11 forms a noise removal passage through the capacitor C1 constituting the time constant circuit 11 by being switched from a disconnected state to a connected state on the basis of the delay signals. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic circuit provided with a time constant circuit, and is particularly suitable for use in other applications when a resistor or a capacitor constituting the time constant circuit does not serve as a time constant circuit.

  2. Description of the Related Art Conventionally, a time constant circuit configured using a resistor and a capacitor has been proposed that can set a time constant (see, for example, Patent Document 1). FIG. 6 shows a circuit diagram of a conventional time constant circuit. As shown in this figure, the time constant circuit 60 includes a resistance circuit 61, a capacitor circuit 62, and a detection circuit 63.

  The resistor circuit 61 is configured by connecting five resistors R3 to R7 in series, and switches SW1 to SW4 are connected in parallel to the four resistors R4 to R7 constituting the resistor circuit 61, respectively. Yes. The capacitor circuit 62 includes three capacitors C4 to C6 connected in parallel, and switches SW5 and SW6 are connected in series to the two capacitors C5 and C6 constituting the capacitor circuit 62. .

  The resistor circuit 61 and the capacitor circuit 62 are connected in series between the operating potential Vcc and the ground GND, so that the operating voltage Vcc is input to the resistor circuit 61 and the capacitor circuit 62.

  The detection circuit 63 detects that the potential at the connection point 64 between the resistor circuit 61 and the capacitor circuit 62 has reached 0.632 times the operating voltage, and outputs the detected voltage to the outside. The converter 63a and the reference voltage source 63b And. In the detection circuit 63, when the potential at the connection point 64 between the resistance circuit 61 and the capacitor circuit 62 reaches the voltage of the reference voltage source 63b, the output signal S1 is switched to the H level and output. That is, the detection circuit 63 constantly monitors the actual voltage across the capacitor circuit 62. The above is the configuration of the conventional time constant circuit 60.

In the time constant circuit 60 having the above-described configuration, the resistance values of the individual resistors R1 to R5 constituting the resistor circuit 61 are known in advance. Therefore, when the time constant of the time constant circuit 60 is adjusted to a desired time, the switch of the resistor circuit 61 is set so that the voltage at the connection point 64 of the capacitor circuit 62 is 0.632 times the operating voltage Vcc at the desired time. SW1 to SW4 are set as appropriate. In this way, the time constant can be easily set.
JP 2000-156623 A

  For example, when power is supplied to a microcomputer (hereinafter referred to as a microcomputer) or a semiconductor chip having a reset signal output function, a CR time constant circuit such as the time constant circuit 60 is used to reliably set these to a reset state. A power-on reset signal generating circuit configured by the following is used. The power-on reset signal generation circuit is a circuit that is provided in the microcomputer or semiconductor chip and generates a reset signal according to the output of the time constant circuit 60, for example.

  However, the conventional time constant circuit 60 only exhibits a delay function of a reset signal when power is supplied to a microcomputer or a semiconductor chip. That is, after the reset of the microcomputer or the semiconductor chip is released, the time constant circuit 60 plays a role if a potential is applied by pull-up or power supply direct connection by the resistors R3 to R7, and the resistors constituting the time constant circuit 60 R3 to R7 and capacitors C4 to C6 were never used for different functions.

  In view of the above points, the present invention provides an electronic device including a time constant circuit that can use components constituting the time constant circuit that has finished its role as a time constant circuit in a role different from the role as a time constant circuit. An object is to provide a circuit.

  In order to achieve the above object, the present invention includes switches (14, 26, 32, 34) connected to the time constant circuit (11, 31), which switches from a disconnected state to a connected state based on a delay signal. By switching to, a noise removal path via the capacitors (C1 to C3) constituting the time constant circuit is formed.

  In this way, the switch is connected to the time constant circuit, and the open / close state of the switch is switched based on the delay signal to form a noise removal path. As a result, the capacitor constituting the time constant circuit that has finished its role by outputting the delay signal can be used for noise removal.

  For example, noise included in the operating potential (Vcc) input to the electronic circuit can be removed to the ground, and noise included in the operating potential can be prevented from being input to other circuits formed in the electronic circuit. Further, noise input from the outside to an arbitrary terminal (23) provided in the electronic circuit can be removed to the ground, and noise can be prevented from being input to a circuit connected to the specific terminal.

  As described above, a capacitor configured as a time constant circuit can be caused to function in a function other than the time constant circuit.

  In the present invention, the switch is switched by the control circuit (13, 25, 33) that switches the disconnection state of the switch to the connection state based on the delay signal, thereby forming a noise removal path.

  In this way, the connection state of the switch is switched by the control circuit. Thereby, software control (control according to a program) of a switch can be performed.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings. An electronic circuit including a time constant circuit shown below is used in an electronic circuit such as a microcomputer, and is configured as an IC chip formed on a semiconductor substrate, for example.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a microcomputer as an electronic circuit according to the first embodiment of the present invention. As shown in this figure, the microcomputer 10 includes a power-on reset signal generating CR time constant circuit (hereinafter referred to as a time constant circuit) 11. The time constant circuit 11 outputs a POR_Bar signal indicating that a time Ts corresponding to the time constant has elapsed after the operating potential Vcc is input to the microcomputer 10 shown in FIG.

  Specifically, as shown in FIG. 1, the time constant circuit 11 is configured by connecting a resistor R1 and a capacitor C1 in series between the operating potential Vcc and the ground GND. The connection point between the resistor R1 and the capacitor C1 is A, and the POR_Bar signal (delay signal) is output from the connection point A according to the time Ts corresponding to the time constant. That is, the time constant circuit 11 outputs the L level POR_Bar signal until the time Ts elapses after the operating potential Vcc is input to the time constant circuit 11, and outputs the H level POR_Bar signal after the time Ts elapses. .

  The time Ts corresponding to the time constant is appropriately set to a desired time according to the design of the resistor R1 and the capacitor C1. The H level corresponds to a value at which the potential at the connection point A reaches about 63% of the final value output from the connection point A, and a value not reaching this corresponds to the L level.

  The connection point A is connected to the input terminal of the inverter 12. The inverter 12 inverts an input signal and outputs it. That is, the inverter 12 outputs an H-level Reset signal until the potential at the connection point A of the time constant circuit 11 reaches the H level, and when the potential at the connection point A of the time constant circuit 11 reaches the H level, the inverter 12 outputs the L level. The Reset signal is output.

  The inverter 12 includes a PMOS transistor and an NMOS transistor (not shown), for example, and when the POR_Bar signal is input to the inverter 12, it is output from the output terminal as a Reset signal. The inverter 12 is operated when the operating potential Vcc is input.

  The output terminal of the inverter 12 is connected to the CPU 13, and the Reset signal output from the output terminal of the inverter 12 is input to the CPU 13. The CPU 13 executes control of each device, calculation of data, processing, etc. according to a program stored in a memory (not shown). The operating potential Vcc is input and a reset signal is input from the inverter 12. Normal operation (execution of a program for controlling the apparatus and the like) is started in response to the fall of the Reset signal. The CPU 13 corresponds to the control circuit of the present invention. Further, the Reset signal output from the inverter 12 is output to other circuits provided in the microcomputer 10 in addition to the CPU 13.

  Further, as shown in FIG. 1, a connection switching switch (hereinafter referred to as a switch) 14 is connected between the operating potential Vcc and the connection point A. That is, a switching program for switching the switch 14 is stored in a memory (not shown), and the connection of the switch 14 is switched by the CPU 13 executing the switching program. As such a switch 14, for example, a MOS transistor is employed.

  In the present embodiment, when the CPU 13 executes the switching program, the switch 14 is in a disconnected state (hereinafter referred to as “open”) while the Reset signal input from the inverter 12 to the CPU 13 is at the H level and at the initial stage after the H level is released. A signal indicating a state is output to the switch 14. Thus, the capacitor C1 of the time constant circuit 11 functions as a CR time constant circuit capacitor. When the Reset signal is at L level, the switch 14 outputs a signal to the switch 14 that is in a connected state (hereinafter referred to as a closed state). Thus, the capacitor C1 of the time constant circuit 11 forms a noise removal path via the switch 14 between the operating potential Vcc and the ground GND, and a noise removal capacitor between the power supply (Vcc) and the ground GND (that is, power supply noise). Functions as a bypass capacitor).

  The above is the configuration of the microcomputer 10 as an electronic circuit including the time constant circuit 11.

  Next, an operation of using the capacitor C1 of the time constant circuit 11 as a function other than the function as the time constant circuit 11 in the microcomputer 10 including the time constant circuit 11 will be described. First, the operating potential Vcc is input to the microcomputer 10. That is, the operating potential Vcc is input to the time constant circuit 11, the switch 14, the inverter 12, and the CPU 13, respectively.

  At this time, the L level POR_Bar signal is output from the connection point A of the time constant circuit 11. Therefore, an H level Reset signal is output from the inverter 12, and this signal is input to the CPU 13.

  The CPU 13 executes the switching program when the operating potential Vcc is input. Thus, when an H level Reset signal is input to the CPU 13, a signal for opening the switch 14 is output from the CPU 13 to the switch 14, and the switch 14 is opened to disconnect the noise removal path.

  In this state, when the capacitor C1 of the time constant circuit 11 is charged, the potential at the connection point A reaches the H level after the time constant Ts has elapsed, and the H level POR_Bar signal is output from the connection point A. Thus, when the HOR level POR_Bar signal is output from the connection point A of the time constant circuit 11, the time constant circuit 11 ends its role.

  When the H level POR_Bar signal is input to the inverter 12, the L level Reset signal is output from the inverter 12, and the L level Reset signal is input to the CPU 13.

  When an L level Reset signal is input to the CPU 13, a signal that causes the switch 14 to be closed is output from the CPU 13 to the switch 14 by the switching program, and the switch 14 is closed to form a noise removal path. Thereby, the capacitor C1 that has finished its role as the time constant circuit 11 can be caused to function as a noise removing capacitor between the power supply (Vcc) and the ground GND.

  The CPU 13 starts executing a program for controlling each device in response to the input of the L level Reset signal. The Reset signal is input to an electric circuit (not shown) of the microcomputer 10. When the microcomputer 10 is turned off and the operating potential Vcc is no longer input to the microcomputer 10, the operation of the microcomputer 10 ends.

  As described above, in the present embodiment, the switch 14 is connected to the time constant circuit 11, and the open / close state of the switch 14 is switched by the CPU 13 to which the Reset signal based on the POR_Bar signal that is a delay signal is input, and the noise removal path. Form. As a result, the capacitor C1 constituting the time constant circuit 11 which has finished its role by outputting the POR_Bar signal can be used for noise removal.

  In the present embodiment, in particular, noise included in the operating potential Vcc input to the microcomputer 10 is removed to the ground GND, so that noise included in the operating potential is not input to other circuits formed in the microcomputer 10. Can do.

  As described above, the capacitor C <b> 1 configured as the time constant circuit 11 can function other than the time constant circuit 11.

  Further, when the microcomputer 10 is configured in a chip of a limited size, the capacitor C1 configured as the time constant circuit 11 can be used as another function, so that the addition of the switch 14 is necessary. A circuit (path) having an arbitrary function can be added without increasing the chip size of the microcomputer 10.

(Second Embodiment)
In the present embodiment, only parts different from the first embodiment will be described. The present embodiment is characterized in that the capacitor C1 of the time constant circuit 11 is used for noise removal from a reset terminal provided in the microcomputer 10.

  FIG. 2 is a circuit diagram of a microcomputer as an electronic circuit according to the second embodiment of the present invention. As shown in this figure, the connection point A of the time constant circuit 11 provided in the microcomputer 20 is connected to the input terminal of the inverter 21. The output terminal of the inverter 21 is connected to one input terminal of an OR circuit 22 having two input terminals. The POR_Bar signal input from the time constant circuit 11 is input and inverted, and the OR circuit is used as the POR signal. 22 is input.

  The OR circuit 22 has two input terminals as described above. When an H level signal is input to one of the two input terminals, the OR circuit 22 outputs an H level signal and outputs two inputs. When an H level signal is not input to both terminals, an L level is output. Such an OR circuit 22 is constituted by, for example, a MOS transistor.

  The reset terminal 23 provided in the microcomputer 20 is connected to the input terminal of the inverter 24. A signal for resetting the microcomputer 20 is input to the reset terminal 23 from the outside of the microcomputer 20.

  In the present embodiment, when the microcomputer 20 is reset, an L level RST_Bar signal is input from the reset terminal 23 to the inverter 24, and when the microcomputer 20 is not reset, an H level RST_Bar signal is input from the reset terminal 23 to the inverter 24. (In this embodiment, an H-level RST_Bar signal is realized by connecting a PullUp resistor between the reset terminal 23 and the operating potential Vcc). The inverter 24 inverts the RST_Bar signal input from the reset terminal 23 and outputs the inverted signal as the RST signal.

  The output terminal of the inverter 24 is connected to the input terminal of the OR circuit 22. That is, the OR circuit 22 outputs an H-level Reset signal when either one of the input POR signal or RST signal is at the H level.

  The output terminal of the OR circuit 22 is connected to the CPU 25, and the Reset signal output from the OR circuit 22 is input to the CPU 25. As shown in FIG. 2, a switch 26 is connected between the connection point A and the reset terminal 23. That is, the CPU 25 switches the switch 26 according to the Reset signal input from the OR circuit 22. When the switch 26 is closed by the CPU 25, a noise removal path is formed, which is the reset terminal 23, the switch 26, the capacitor C1 of the time constant circuit 11, and the ground GND, and noise input to the reset terminal 23 is removed from the noise. It is removed by the route.

  The above is the configuration of the microcomputer 20 when the time constant circuit 11 is applied to the present embodiment.

  Next, an operation of using the capacitor C1 of the time constant circuit 11 as a function other than the function as the time constant circuit 11 in the microcomputer 20 including the time constant circuit 11 will be described. First, the operating potential Vcc is input to the microcomputer 20.

  Thus, immediately after the operating potential Vcc is input to the microcomputer 20, the L level POR_Bar signal is output from the connection point A of the time constant circuit 11 as described above. Therefore, the inverter 21 outputs an H level POR signal, and the OR circuit 22 outputs an H level Reset signal. When this H-level Reset signal is input to the CPU 25, a signal for opening the switch 14 is output from the CPU 25 to the switch 26, the switch 26 is opened, and the noise removal path is disconnected.

  Thereafter, the potential at the connection point A of the time constant circuit 11 reaches the H level after the elapse of the time constant Ts, the H level POR_Bar signal is output from the connection point A, and the role of the time constant circuit 11 ends. Then, when the H level POR_Bar signal is input to the inverter 21, the L level POR signal is output from the inverter 21 and input to the OR circuit 22.

  On the other hand, if a signal for resetting the microcomputer 20 from the outside is not input to the reset terminal 23, an H level RST_Bar signal is input from the reset terminal 23 to the inverter 24, and an L level RST signal is output from the inverter 24. The

  As a result, an L level Reset signal is input from the OR circuit 22 to the CPU 25, so that the switch 25 is closed by the CPU 25. Thereby, after the time constant Ts elapses, the above-described noise removal path is formed, and the capacitor C1 of the time constant circuit 11 functions as a capacitor for removing noise (ie, a capacitor for removing terminal noise).

  Further, when the operating potential Vcc is input to the microcomputer 20 as described above and a signal for resetting the microcomputer 20 is input after the time constant Ts has elapsed, the L level RST_Bar signal is output from the reset terminal 23 to the inverter 24. And an H level RST signal is output. The H level RST signal is input to the OR circuit 22, whereby the H level Reset signal is input to the CPU 25 from the OR circuit 22, and the switch 25 is opened by the CPU 25. Thus, the capacitor C1 of the time constant circuit 11 functions as the time constant circuit 11 while a signal for resetting the microcomputer 20 is input to the reset terminal 23.

  When a signal for resetting the microcomputer 20 is not input to the reset terminal 23, an L level RST signal is output from the inverter 24, and an L level Reset signal is input from the OR circuit 22 to the CPU 25. The switch 26 is closed.

  As described above, after the capacitor C1 finishes the function as the time constant circuit 11, the noise input from the outside to the reset terminal 23 provided in the microcomputer 20 is grounded through the noise removal path formed by the capacitor C1. The noise input to the system connected to the reset terminal 23 can be removed.

(Third embodiment)
In the present embodiment, only portions different from the first and second embodiments will be described. The present embodiment is characterized in that the first and second embodiments can be realized simultaneously by preparing a plurality of capacitors of a time constant circuit and connecting them in parallel.

  FIG. 3 is a circuit diagram of a microcomputer as an electronic circuit according to the third embodiment of the present invention. As shown in this figure, the time constant circuit 31 provided in the microcomputer 30 is configured by connecting a resistor R2 and a parallel connection of capacitors C2 and C3 in series.

  The parallel connection of the capacitors C2 and C3 is realized by the switch 32. That is, the capacitor C2 is connected between the contact 32a of the switch 32 and the ground GND, the capacitor C3 is connected between the contact 32b of the switch 32 and the ground GND, and the contact 32a and the contact 32b of the switch 32 are connected. As a result, the capacitors C2 and C3 are connected in parallel.

  Further, the contact 32 c of the switch 32 is connected to the reset terminal 23 of the microcomputer 30. The switch 32 is connected to either the contact 32b or the contact 32c with respect to the contact 32a. The switch 33 is switched by the CPU 33.

  If the connection point between the resistor R2 and the capacitor C3 is B (the connection point B corresponds to the connection point A shown in the first and second embodiments), the connection between the operating potential Vcc and the connection point B. Is connected to the switch 34. Further, the connection point B is connected to the input terminal of the inverter 35. When a POR_Bar signal is input to the inverter 35 from the connection point B, this signal is inverted and output as a POR signal and input to the input terminal of the OR circuit 36.

  On the other hand, the reset terminal 23 is connected to the input terminal of the inverter 37, and is input to the input terminal of the OR circuit 36 as the RST signal output from the output terminal of the inverter 37.

  The OR circuit 36 inputs a Reset signal to the CPU 33 in response to the POR signal and the RST signal. When the reset signal of L level is input, the CPU 33 connects the contact 32a and the contact 32c of the switch 32 and outputs a signal for closing the switch 34 to the switches 32 and 34, respectively. That is, the CPU 33 executes a program for controlling the switches 32 and 34 in this way.

  In such a configuration, when the operating potential Vcc is input to the microcomputer 30, the H level RST_Bar signal is input from the reset terminal 23 to the inverter 37 as shown in the second embodiment. An L level RST signal is input from 37 to the OR circuit 36. Further, the L level POR_Bar signal is output from the connection point B while the time corresponding to the time constant does not elapse after the operation potential Vcc is input in the time constant circuit 31. As a result, an H level Reset signal is output from the OR circuit 36, and the CPU 33 connects the contact 32a and the contact 32b of the switch 32 in accordance with the H level Reset signal, and the switch 34 is opened. . As a result, the capacitors C2 and C3 function as part of the time constant circuit 31, respectively.

  Thereafter, when a time corresponding to the time constant elapses in the time constant circuit 31, an H level POR_Bar signal is output from the connection point B, and therefore an L level Reset signal is input from the OR circuit 36 to the CPU 33 and the switch 32. Are connected to each other and the switch 34 is closed.

  Thus, the capacitor C2 functions to form a noise removal path between the reset terminal 23 and the ground GND and remove noise. The capacitor C3 forms a noise removal path between the operating potential Vcc and the ground GND, and functions to remove noise. When a reset signal is input from the outside to the reset terminal 23, the capacitors C2 and C3 function as part of the time constant circuit 31 by the same operation as in the second embodiment.

  As described above, the capacitors C2 and C3 constituting the time constant circuit 31 are connected in parallel, and after the function as the time constant circuit 31 is completed, the noise removal path is formed by the switches 32 and 34, respectively. It can be used as a function.

(Fourth embodiment)
In the present embodiment, only parts different from the first embodiment will be described. The present embodiment is characterized in that the open / close state of the switch 14 is not controlled by the CPU 13, but the open / close state of the switch 14 is controlled by hardware using the Reset signal output from the inverter 12.

  FIG. 4 is a circuit diagram of a microcomputer as an electronic circuit according to the fourth embodiment of the present invention. As shown in this figure, in the microcomputer 40 of this embodiment, the output terminal of the inverter 12 is connected to the input terminal of the inverter 41, and the signal output from the output terminal of the inverter 41 is input to the switch 14. It has become. In other words, the switch 14 is closed when an H level signal is input from the inverter 41, and is opened when an L level signal is input.

  Therefore, while the operating potential Vcc is input to the microcomputer 40 and the potential at the connection point A of the time constant circuit 11 is L level, the H level reset signal is output from the inverter 12. Is output and the switch 14 is open.

  Thereafter, when the potential at the connection point A of the time constant circuit 11 reaches the H level, an L level Reset signal is output from the inverter 12, an H level signal is output from the inverter 41, and the switch 14 is closed. . As a result, a noise removal path is formed between the operating potential Vcc and the ground GND via the switch 14 and the capacitor C1 of the time constant circuit 11, and the capacitor C1 functions for noise removal.

  As described above, the reset signal output from the inverter 12 can be used to control the open / close state of the switch 14 so that the capacitor C1 can be used as a function other than the time constant circuit 11.

  Note that the Reset signal output from the inverter 12 is output to a CPU (not shown in FIG. 4) and used to start up the operation of the CPU.

(Fifth embodiment)
In the present embodiment, only different parts from the second embodiment will be described. As in the fourth embodiment, this embodiment is characterized in that the switch 26 is controlled by a hard enemy using a Reset signal.

  FIG. 5 is a circuit diagram of a microcomputer as an electronic circuit according to the fifth embodiment of the present invention. As shown in this figure, in the microcomputer 50, the input terminal of the inverter 51 is connected to the output terminal of the OR circuit 22, and the signal output from the output terminal of the inverter 51 is input to the switch 26. Yes.

  That is, as in the fourth embodiment, the open / close state of the switch 26 is controlled according to the Reset signal output from the OR circuit 22. Accordingly, the capacitor C1 that has finished its role as the time constant circuit 11 can be used for removing noise from the reset terminal 23.

(Other embodiments)
The circuit configurations of the microcomputers 10 to 50 shown in the above embodiments are merely examples, and are not limited to the above circuits. That is, by incorporating the time constant circuits 11 and 31 into an electronic circuit such as the microcomputer 10 to 50, the capacitors C1 to C3 constituting the time constant circuits 11 and 31 can be used as other functions.

  In each of the above embodiments, the capacitors C1 to C3 are used for applications other than the time constant circuits 11 and 31, but the resistors R1 and R2 are similarly made to function as applications other than the time constant circuits 11 and 31. It is also possible. For example, when the resistors R1 and R2 are connected to an arbitrary circuit and used as the resistance of the circuit, the resistance value of an arbitrary path is changed, or used as a resistor for the voltage PullUp.

  The configurations of the time constant circuits 11 and 31 shown in the above embodiments are merely examples, and are not limited to the above. That is, it is possible to freely configure each electronic circuit such as a configuration in which resistors are paralleled, a configuration in which three or more capacitors are paralleled, and a configuration using coils.

  The switches 14, 26, 32, and 34 shown in the above embodiments are composed of MOS transistors, but may be composed of elements such as analog switches and bipolar transistors. .

It is a circuit diagram of the microcomputer as an electronic circuit concerning a 1st embodiment of the present invention. It is a circuit diagram of the microcomputer as an electronic circuit concerning a 2nd embodiment of the present invention. It is a circuit diagram of the microcomputer as an electronic circuit concerning a 3rd embodiment of the present invention. It is a circuit diagram of the microcomputer as an electronic circuit concerning a 4th embodiment of the present invention. It is a circuit diagram of the microcomputer as an electronic circuit concerning a 5th embodiment of the present invention. It is a circuit diagram of the conventional time constant circuit.

Explanation of symbols

10-50 ... microcomputer, 11, 31 ... time constant circuit,
12, 21, 24, 35, 37, 41, 51 ... inverter,
13, 25, 33 ... CPU, 14, 26, 32, 34 ... switch,
22, 36... OR circuit, R1, R2... Resistor, C1 to C3.

Claims (2)

A resistor (R1, R2) and a capacitor (C1 to C3) are combined to provide a time constant circuit (11, 31) that outputs a delay signal after a time corresponding to the time constant has elapsed from an arbitrary reference time. Electronic circuit,
Comprising switches (14, 26, 32, 34) connected to the time constant circuit;
The switch is configured to form a noise removal path via the capacitor constituting the time constant circuit by switching from a disconnected state to a connected state based on the delay signal. circuit. The switch is configured to form the noise removal path by being switched by a control circuit (13, 25, 33) that switches the disconnection state of the switch to a connection state based on the delay signal. The electronic circuit according to claim 1.

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