JP2007121699A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To drastically reduce the electric power consumption of an LCD controller by changing over an operation mode according to the operation mode of an image display. <P>SOLUTION: In displaying a static image on an LCD panel, a CPU 3 sets a register 9 of the LCD controller 5 at a low-speed mode. A clock switching section 8 supplies a clock signal CLK1 to a data processing section 6 and a frame buffer 4 based on the setting. A bus switching section 7 switches buses in such a manner that the frame buffer 4 and the LCD controller 5 are directly connected via the bus B1 dedicated for low speed. Image data are captured into the LCD controller 5 from the frame buffer 4 via the bus B1 dedicated for low speed. Since the LCD controller 5 and the frame buffer 4 are disconnected from the high-speed bus Bh, the electric power consumption during LCD refresh can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technology for reducing power consumption of a semiconductor integrated circuit device, and more particularly to a technology effective for reducing power consumption of a semiconductor integrated circuit device having an LCD controller for driving a liquid crystal display (LCD) panel. .

  2. Description of the Related Art In recent years, LCD panels used for mobile phones and the like have become standard with QVGA (Quarter Video Graphics Array) size panels.

  Along with this, the data capacity of VRAM (Video Random Access Memory) that holds the contents to be displayed on the LCD tends to increase. Therefore, it is known that a VRAM is not mounted on an LCD driver but a frame buffer is provided in a semiconductor integrated circuit device used as an application processor.

  In the case where a frame buffer is provided in a semiconductor integrated circuit device, for example, when a semiconductor memory such as SDRAM (Synchronous Dynamic RAM) is externally connected as a frame buffer, external connection is performed when displaying the same frame (hereinafter referred to as LCD refresh). Therefore, it is possible to reduce the power consumption for accessing the frame buffer.

  However, the present inventors have found that the semiconductor integrated circuit device as described above has the following problems.

  Writing of image data to the frame buffer is performed by a bus master such as a CPU (Central Processing Unit) or a DMAC (Direct Memory Access Controller).

  Generally, the frame buffer is connected to a high-speed bus to which the above-described bus master is connected, and reading from the LCD controller is also performed via the high-speed bus.

  In this case, even in a state where only LCD refresh is required, it is necessary to always turn on the power of the high-speed bus, the LCD controller, and the clock pulse generator that supplies the clock signal to the frame buffer, which hinders low power consumption. There is a problem of becoming.

  In addition, since the high-speed bus is operated with a high-speed clock signal, the operating frequency of the LCD controller and the frame buffer cannot be lowered, and this also consumes unnecessary power.

  An object of the present invention is to provide a technique capable of significantly reducing the power consumption of an LCD controller by switching an operation mode according to an image display operation.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor integrated circuit device according to the present invention includes a display data semiconductor memory for storing image data, a display control unit for controlling driving in a display display panel stored in the display data semiconductor memory, and control of the display control unit. A display data semiconductor memory, a display control unit, and a CPU are interconnected to an internal bus, and the display control unit is connected to the display data semiconductor memory via the internal bus, Alternatively, the first mode for reading display data stored in an externally connected semiconductor memory, the display data semiconductor memory, and the display control unit are connected by a dedicated bus, and the display data semiconductor memory is connected to the first mode via the dedicated bus. A mode switching control unit for switching between the second mode for reading stored display data is provided.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the semiconductor integrated circuit device of the present invention, the mode switching control unit supplies the first clock signal to the display data semiconductor memory and the display control unit in the first mode, and the display data in the second mode. The second clock signal having a frequency lower than that of the first clock signal is supplied to the semiconductor memory and the display control unit for operation.

  In the semiconductor integrated circuit device of the present invention, the mode switching control unit is accessed by the CPU, and the switching setting unit in which the switching setting between the first mode and the second mode is performed by the CPU, and the switching setting unit. Based on the set data that has been set, it is determined whether the first mode or the second mode has been set, and a bus switching unit that switches between an internal bus and a dedicated bus, and a switching setting unit are set. Based on the set data, it is determined which one of the first mode and the second mode is set, and a clock switching unit that switches and outputs the first clock signal and the second clock signal. Is.

  Furthermore, in the semiconductor integrated circuit device of the present invention, the switching setting unit is composed of a register.

  In the semiconductor integrated circuit device of the present invention, the mode switching control unit performs switching between the first mode and the second mode during a blanking period when the display control unit is not accessing.

  Furthermore, the semiconductor integrated circuit device of the present invention is capable of shutting off the power to the CPU when the mode switching control unit sets the second mode.

  In the semiconductor integrated circuit device of the present invention, the display control unit performs display control using display data stored in the display data semiconductor memory while the second mode is set. .

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The power consumption in the semiconductor integrated circuit device can be greatly reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

  In the present embodiment, the semiconductor integrated circuit device 1 is used as an application processor of a mobile communication device such as a mobile phone. As shown in FIG. 1, the semiconductor integrated circuit device 1 includes a memory controller 2, a CPU 3, a frame buffer (semiconductor memory for display data) 4, an LCD controller (display control unit) 5, and the like.

  The memory controller 2, CPU 3, frame buffer 4, and LCD controller 5 are connected to each other via a high-speed bus (internal bus) Bh. The frame buffer 4 is directly connected to the LCD controller 5 via a low-speed dedicated bus (dedicated bus) Bl.

  The memory controller 2 controls the external memory M externally connected to the semiconductor integrated circuit device 1. The external memory M is composed of a volatile semiconductor memory such as SDRAM, for example, and temporarily stores image data to be displayed on an externally connected LCD.

  The CPU 3 manages all the controls in the semiconductor integrated circuit device 1. The frame buffer 4 is composed of, for example, a volatile semiconductor memory such as a RAM, and temporarily stores the image data of the external memory M read through the memory controller 2.

  The LCD controller 5 controls an LCD driver Dr that drives an LCD panel externally connected to the semiconductor integrated circuit device 1. The LCD controller 5 includes a high-speed clock signal (first clock signal) CLKh (for example, about 66 MHz) generated by the clock pulse generator provided in the semiconductor integrated circuit device 1 and the clock signal CLKh. A low-frequency externally input clock signal (second clock signal) CLK1 (for example, about 13 MHz) is connected to be input. The clock signal CLKl may be generated by a clock pulse generator.

  Hereinafter, a mode in which the semiconductor integrated circuit device 1 operates with the clock signal CLKh is a high speed mode (first mode), and a mode in which the semiconductor integrated circuit device 1 operates with the clock signal CLKl is a low speed mode (second mode).

  The LCD controller 5 includes a data processing unit 6, a bus switching unit (mode switching control unit) 7, a clock switching unit (mode switching control unit) 8, a register (mode switching control unit, switching setting unit) 9, and the like. Yes.

  The data processing unit 6 performs an arithmetic process on the image data fetched from the external memory M or the frame buffer 4 and outputs the processing result to the LCD driver Dr. Based on the register value stored in the register 9, the bus switching unit 7 performs switching so that the frame buffer 4 is connected to either the high speed bus Bh or the low speed dedicated bus Bl.

  Based on the register value stored in the register 9, the clock switching unit 8 switches to either the clock signal CLKh or the clock signal CLKl and supplies it to the data processing unit 6 and the frame buffer 4.

  The register 9 is a register accessed by the CPU 3, and an arbitrary register value is set under the control of the CPU 3.

  Next, the operation of the LCD controller 5 according to this embodiment will be described.

  First, when displaying a still image on the LCD panel, the image data in the external memory M is taken into the frame buffer 4 from the memory controller 2 via the high-speed bus Bh in the high-speed mode.

  Then, the image data taken into the frame buffer 4 is read out to the LCD controller 5 via the high-speed bus Bh (path shown by a dotted arrow line in FIG. 1). In this high-speed mode, since the frame buffer 4 is connected via the high-speed bus Bh, for example, peripheral frames other than the LCD controller 5 such as an image processing engine can access the frame buffer 4 at high speed. .

  Subsequently, when transitioning to the low speed mode, the CPU 3 accesses the register 9 of the LCD controller 5 and sets the register value of the register 9 to operate in the low speed mode.

  The clock switching unit 8 performs switching so as to supply the clock signal CLKl to the data processing unit 6 and the frame buffer 4 based on the setting of the register 9 by the CPU 3.

  Similarly, the bus switching unit 7 performs switching so that the frame buffer 4 and the LCD controller 5 are directly connected via the low-speed dedicated bus B1 (path indicated by a solid line arrow in FIG. 1).

  These switching operations by the clock switching unit 8 and the bus switching unit 7 are automatically performed during a period in which the LCD controller 5 between frames does not access the frame buffer 4 or the LCD driver Dr (hereinafter referred to as a blanking period). Is called.

  As a result, the image data is taken into the LCD controller 5 from the frame buffer 4 via the low-speed dedicated bus Bl and displayed on the LCD panel. Therefore, when displaying a still image, the LCD controller 5 and the frame buffer 4 are disconnected from the high-speed bus Bh, so that power consumption during LCD refresh can be greatly reduced.

  In this low-speed mode, the power consumption can be further reduced by controlling the power supply to the memory controller 2, the CPU 3, the clock pulse generator, and the external memory M.

  In the case of this power shutdown, for example, to return to the high speed mode, the CPU 3 is activated when an external interrupt signal is input, and the register value is set so that the CPU 3 operates in the high speed mode in the register 9 of the LCD controller 5. To do.

  Accordingly, the clock switching unit 8 switches the clock signal supplied to the data processing unit 6 and the frame buffer 4 from the clock signal CLKl to the clock signal CLKh, and the bus switching unit 7 connects the frame buffer 4 and the LCD controller 5 to each other. It switches so that it may connect via the high-speed bus Bh.

  The switching operation by the clock switching unit 8 and the bus switching unit 7 is automatically performed during the return period.

  Next, a case where an image display (for example, a low-speed moving image) in which the refresh rate of the LCD panel is about 60 fps and the frame buffer 4 is updated about 10 fps will be described.

  In this case, for example, the image data needs to be updated every 6 frames. At this time, control is performed so that image data is read from the external memory M for one frame and image data is read from the frame buffer 4 for the remaining five frames.

  First, image data is read from the external memory M in the high-speed mode. This data is input to the LCD controller 5 and the frame buffer 4 via the high-speed bus Bh.

  The image data input to the LCD controller 5 is processed by the data processing unit 6 and output to the LCD driver Dr. At this time, the frame buffer 4 stores the image data read from the external memory M.

  Further, the CPU 3 accesses the register 9 and sets the register value of the register 9 so as to operate in the low speed mode.

  The clock switching unit 8 performs switching so as to supply the clock signal CLKl to the data processing unit 6 and the frame buffer 4 based on the set value of the register 9, and the bus switching unit 7 includes the frame buffer 4 and the LCD controller 5. Are switched directly to each other via the low-speed dedicated bus Bl.

  As described above, the switching operation by the clock switching unit 8 and the bus switching unit 7 is automatically performed during the retrace period.

  The remaining five frames are controlled so that the LCD controller 5 reads out the image data stored in the frame buffer 4 via the low-speed dedicated bus Bl and draws the frames.

  Thereafter, the same operation is repeated every 6 frames to draw a frame. As a result, 5 frames out of 6 frames can be drawn in the low-speed mode in a low-speed moving image or the like.

  Thereby, according to the present embodiment, the power consumption in the semiconductor integrated circuit device 1 can be significantly reduced.

  Further, in low-speed moving image display or the like, the occupation rate of the high-speed bus Bh can be reduced, and the bus load during execution of complicated processing such as videophone can be reduced. The processing speed of the semiconductor integrated circuit device 1 Can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for a technique for reducing power consumption in a semiconductor integrated circuit device including an LCD controller.

1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 Memory controller 3 CPU
4 Frame buffer (semiconductor memory for display data)
5 LCD controller (display controller)
6 Data processing unit 7 Bus switching unit (mode switching control unit)
8 Clock switching unit (mode switching control unit)
9 registers (mode switching control unit, switching setting unit)
Bh express bus (internal bus)
Bl Low-speed exclusive bus (dedicated bus)
M External memory Dr LCD driver CLKh Clock signal (first clock signal)
CLKl clock signal (second clock signal)

Claims (7)

Display data semiconductor memory for storing display data;
A display control unit that reads display data stored in the display data semiconductor memory and performs drive control in the display display panel;
A CPU for controlling the display control unit;
The display control unit
The display data semiconductor memory, the display control unit, and the CPU are connected to an internal bus, and the display control unit is connected to the display data semiconductor memory or an externally connected semiconductor memory via the internal bus. A first mode for reading stored display data, the display data semiconductor memory and the display control unit are connected by a dedicated bus, and the display data stored in the display data semiconductor memory via the dedicated bus A semiconductor integrated circuit device, comprising: a mode switching control unit that switches between a second mode for reading out data. The semiconductor integrated circuit device according to claim 1.
The mode switching control unit
In the first mode, a first clock signal is supplied to the display data semiconductor memory and the display control unit. In the second mode, the display data semiconductor memory and the display control unit are supplied with the first clock signal. A semiconductor integrated circuit device which operates by supplying a second clock signal having a frequency lower than that of the first clock signal. The semiconductor integrated circuit device according to claim 1 or 2,
The mode switching control unit
A switching setting unit that is accessed by the CPU and configured to switch between the first mode and the second mode by the CPU;
Based on the setting data set in the switching setting unit, it is determined which of the first mode and the second mode is set, and bus switching is performed to switch between the internal bus and the dedicated bus And
Based on the setting data set in the switching setting unit, it is determined which of the first mode and the second mode is set, and the first clock signal and the second clock signal are And a clock switching unit for switching and outputting the semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 3.
The semiconductor integrated circuit device, wherein the switching setting unit is a register. The semiconductor integrated circuit device according to any one of claims 1 to 4,
The mode switching control unit
The semiconductor integrated circuit device, wherein the switching between the first mode and the second mode is performed during a blanking period when the display control unit is not accessing. In the semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein when the mode switching control unit sets the second mode, the power to the CPU can be shut off. The semiconductor integrated circuit device according to any one of claims 1 to 6,
The display control unit
A semiconductor integrated circuit device that performs display control using display data stored in the display data semiconductor memory while the second mode is set.

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