JP2007115743A - Patterning method, thin film transistor, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a patterning method in which metal elements composing an anti-diffusion layer are prevented from diffusing into other layer by forming a more compact anti-diffusion layer exhibiting good adhesiveness, and to provide an electronic device and an electronic apparatus. <P>SOLUTION: The patterning method comprises a step for forming a barrier 30 on a substrate P, a step for arranging a conductive material 80a containing plating nuclei 26 in a patterning region 30a surrounded by the barrier 30, a step for forming a conductive layer 80 by calcinating the conductive material 80a arranged in the patterning region 30a, and a step for forming an anti-diffusion layer 82 on the conductive material 80a by electroless plating method using the plating nuclei 26 as a catalyst. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a pattern forming method, a thin film transistor, and an electronic device.

  When manufacturing a thin film transistor (TFT) which is a switching element used in an electro-optical device such as a liquid crystal device, a photolithography method is used in a process of forming an electrode or a wiring. This photolithography method includes a step of previously forming a solid thin film by a film forming method such as sputtering, plating, or CVD, a step of applying a photosensitive material called a resist on the thin film, and exposing the resist. The thin film electrode or the wiring pattern is formed by the developing step and the step of etching the conductive film according to the obtained resist pattern. The formation and patterning of functional thin films using this series of photolithography methods require large-scale equipment such as a vacuum apparatus and complicated processes during film formation and etching, and the material use efficiency is about several percent. Most of them have to be discarded, and not only the production cost is high, but also the productivity is low.

Therefore, a method of forming an electrode pattern or a wiring pattern (film pattern) on a substrate using a droplet discharge method (so-called ink jet method) in which a liquid material is discharged from a liquid discharge head in a droplet shape is widely used. (For example, refer to Patent Document 1 and Patent Document 2). In this method, a bank corresponding to a thin film pattern to be formed is formed, and after discharging ink in which metal fine particles and the like are dispersed in a region surrounded by the bank, the thin film pattern is formed by drying or baking. According to this method, the conventional complicated film forming process, photolithography, and etching process are not required, and the process is greatly simplified. In addition, the amount of raw materials used is small, and productivity can be improved. There is.
Japanese Patent Laid-Open No. 11-274671 JP 2000-216330 A

  In recent years, a method of forming an electrode of a bottom gate type thin film transistor by using the above-described droplet discharge method has been proposed. Here, the thin film transistor has a structure in which a gate electrode made of a metal material and a semiconductor layer are stacked on the gate electrode through a gate insulating film. At this time, part of the metal element of the material forming the gate electrode may be diffused into the gate insulating film by heat treatment performed when forming the stacked structure. As a result, the insulating property of the gate insulating film is lowered, current leakage occurs, and the thin film transistor becomes defective. Therefore, a method for preventing the diffusion of the metal element by covering the gate electrode with a diffusion preventing layer has been proposed. This diffusion prevention layer can also be formed by the above-described droplet discharge method.

  However, materials constituting the diffusion prevention layer, such as Ni, Ti, Co, Ta, etc. have a high melting point. On the other hand, the melting point of the bank surrounding the pattern region is lower than the material constituting the diffusion prevention layer. For example, the melting point of the material constituting the diffusion prevention layer is 700 ° C., and the melting point of the partition walls is 300 ° C. Therefore, when forming the diffusion prevention layer, it is necessary to perform heat treatment at a temperature not higher than the melting point of the bank. Therefore, a method for lowering the melting point by making the material such as Ni finer has been proposed, but it has been difficult to fuse the diffusion preventing layer on the gate electrode only by this method. Therefore, minute holes are generated in the diffusion prevention layer formed by firing the metal fine particles (conductive fine particles), and it becomes difficult to obtain a dense diffusion prevention layer due to the minute holes. Such a diffusion preventing layer lacking in density cannot sufficiently prevent the diffusion of the metal element into the gate insulating film, and causes a leakage current due to a decrease in insulation.

  The present invention has been made in view of the above problems, and its purpose is to form a denser and more adherent anti-diffusion layer and prevent the metal elements constituting the anti-diffusion layer from diffusing into other layers. Another object of the present invention is to provide a pattern forming method, an electronic device, and an electronic apparatus.

  In order to solve the above problems, the present invention provides a partition forming step of forming a partition on a substrate, a conductive material disposing step of disposing a conductive material containing a plating nucleus in a pattern formation region surrounded by the partition, A conductive layer forming step of forming a conductive layer by firing the conductive material disposed in the pattern formation region, and a diffusion prevention layer on the conductive layer by using the plating nucleus as a catalyst by an electroless plating method And a layer forming step.

  According to this method, since the conductive material disposed in the partition contains plating nuclei, when such a substrate is subjected to electroless plating, the plating nuclei contained in the conductive material function as a catalyst (seed layer), and the conductive material is placed on the conductive material. Only selectively deposits the plating. Further, since the diffusion preventing layer is formed by the electroless plating method, it is possible to form a diffusion preventing layer that is dense and has good adhesion at a temperature lower than the melting point of the partition wall. Thereby, it can prevent that the elemental material which comprises a conductive layer diffuses to another layer. Furthermore, since the plating nucleus is contained in the conductive material, there is no need to provide a separate catalyst treatment step for depositing the diffusion preventing material on the conductive layer, so that the total number of steps can be reduced and the cost can be reduced. Can be planned.

  In the pattern forming method of the present invention, it is also preferable to use Pd for the plating nucleus in the conductive material arranging step.

  According to this method, it is possible to selectively deposit a metal such as Ni on the conductive layer by using Pd (palladium) for the plating nucleus.

  In the pattern forming method of the present invention, it is also preferable that the conductive material is arranged by a droplet discharge method or a dispenser method in the conductive material arrangement step.

  According to this method, the photolithography process and the etching process can be reduced, and the process is greatly simplified. Moreover, by selectively disposing the plating nucleus on the conductive layer, the amount of material used can be reduced, and productivity can be improved.

  The thin film transistor of the present invention includes a gate electrode provided on a substrate and a semiconductor layer disposed on the gate electrode with an insulating film interposed therebetween, and the gate electrode and the semiconductor layer include the above-mentioned A diffusion prevention layer formed by a pattern forming method is provided.

The thin film transistor of the present invention has a bottom gate type thin film transistor structure in which a gate electrode is formed below the semiconductor layer.
According to this configuration, the dense and anti-diffusion layer formed by the above-described method is formed on the gate electrode. Accordingly, the metal material of the gate electrode can be prevented from diffusing into the insulating film formed over the gate electrode due to the heat treatment. Therefore, it is possible to avoid the occurrence of a leakage current due to the lowering of the insulating property of the insulating film, and to obtain a thin film transistor with excellent operation reliability.

  The thin film transistor of the present invention further comprises a source electrode and a drain electrode connected on the semiconductor layer, and at least one of the upper layer of the source electrode and the upper layer of the drain electrode has the pattern according to the present invention described above. It is preferable that a diffusion preventing layer formed by the forming method is provided.

  According to this configuration, since the diffusion prevention layer is formed in the upper layer and / or the lower layer of the source electrode and / or the drain electrode, the metal material such as the source electrode diffuses into the insulating film formed in the upper layer or the like. Can be prevented. Therefore, it is possible to avoid the occurrence of a leakage current due to the lowering of the insulating property of the insulating film, and to obtain a thin film transistor with excellent operation reliability.

An electronic apparatus according to the present invention includes the thin film transistor.
ADVANTAGE OF THE INVENTION According to this invention, the electronic device which has the outstanding reliability and can be provided cheaply is obtained.

Embodiments of the present invention will be described below with reference to the drawings.
In the following description, a method for manufacturing a TFT array substrate including a bottom gate type thin film transistor will be described. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.

[Droplet discharge device]
First, a droplet discharge device used for forming the gate electrode 80, the diffusion prevention layer 82, and the like will be described. FIG. 1A is a perspective view showing a schematic configuration of a droplet discharge device IJ used in the present embodiment.
The droplet discharge device IJ includes a droplet discharge head 301, an X-axis direction drive shaft 304, a Y-axis direction guide shaft 305, a control device CONT, a stage 307, a cleaning mechanism 308, a base 309, and a heater. 315.
The stage 307 supports the substrate P on which ink (liquid material) is provided by the droplet discharge device IJ, and includes a fixing mechanism (not shown) that fixes the substrate P at a reference position.

  The droplet discharge head 301 is a multi-nozzle type droplet discharge head provided with a plurality of discharge nozzles, and the longitudinal direction and the Y-axis direction are made to coincide. The plurality of ejection nozzles are provided on the lower surface of the droplet ejection head 301 in the Y axis direction at regular intervals. From the discharge nozzle of the droplet discharge head 301, the ink containing the conductive fine particles described above is discharged onto the substrate P supported by the stage 307.

An X-axis direction drive motor 302 is connected to the X-axis direction drive shaft 304. The X-axis direction drive motor 302 is a stepping motor or the like, and rotates the X-axis direction drive shaft 304 when a drive signal in the X-axis direction is supplied from the control device CONT. When the X-axis direction drive shaft 304 rotates, the droplet discharge head 301 moves in the X-axis direction.
The Y-axis direction guide shaft 305 is fixed so as not to move with respect to the base 309. The stage 307 includes a Y-axis direction drive motor 303. The Y-axis direction drive motor 303 is a stepping motor or the like, and moves the stage 307 in the Y-axis direction when a drive signal in the Y-axis direction is supplied from the control device CONT.

The control device CONT supplies a droplet discharge control voltage to the droplet discharge head 301. Further, the X-axis direction drive motor 302 has a drive pulse signal for controlling the movement of the droplet discharge head 301 in the X-axis direction, and the Y-axis direction drive motor 303 has a drive pulse signal for controlling the movement of the stage 307 in the Y-axis direction. Supply.
The cleaning mechanism 308 is for cleaning the droplet discharge head 301. The cleaning mechanism 308 includes a Y-axis direction drive motor (not shown). The cleaning mechanism moves along the Y-axis direction guide shaft 305 by driving the Y-axis direction drive motor. The movement of the cleaning mechanism 308 is also controlled by the control device CONT.
Here, the heater 315 is means for heat-treating the substrate P by lamp annealing, and performs evaporation and drying of the solvent contained in the liquid material applied on the substrate P. The heater 315 is also turned on and off by the control device CONT.

  The droplet discharge device IJ discharges droplets onto the substrate P while relatively scanning the droplet discharge head 301 and the stage 307 that supports the substrate P. Here, in the following description, the X-axis direction is a scanning direction, and the Y-axis direction orthogonal to the X-axis direction is a non-scanning direction. Accordingly, the discharge nozzles of the droplet discharge head 301 are provided at regular intervals in the Y-axis direction, which is the non-scanning direction. In FIG. 1A, the droplet discharge head 301 is arranged at a right angle to the traveling direction of the substrate P. However, the angle of the droplet discharging head 301 is adjusted to the traveling direction of the substrate P. You may make it cross. In this way, the pitch between the nozzles can be adjusted by adjusting the angle of the droplet discharge head 301. Further, the distance between the substrate P and the nozzle surface may be arbitrarily adjusted.

FIG. 1B is a schematic configuration diagram of a droplet discharge head for explaining the principle of discharging a liquid material by a piezo method.
In FIG. 1B, a piezo element 322 is installed adjacent to a liquid chamber 321 that stores a liquid material (ink; functional liquid). The liquid material is supplied to the liquid chamber 321 via a liquid material supply system 323 including a material tank that stores the liquid material. The piezo element 322 is connected to a drive circuit 324, and a voltage is applied to the piezo element 322 via the drive circuit 324 to deform the piezo element 322 and elastically deform the liquid chamber 321. And the liquid material is discharged from the nozzle 325 by the change of the internal volume at the time of this elastic deformation.
In this case, the amount of distortion of the piezo element 322 can be controlled by changing the value of the applied voltage. In addition, the strain rate of the piezo element 322 can be controlled by changing the frequency of the applied voltage. Since the droplet discharge by the piezo method does not apply heat to the material, it has an advantage of hardly affecting the composition of the material.

[Method for manufacturing TFT array substrate]
Hereinafter, each manufacturing process of the TFT array substrate will be described with reference to FIGS.
2 to 5 are cross-sectional process diagrams showing a series of processes in the manufacturing method of the present embodiment. 3 to 5, the Pd nucleus 26 contained in the gate electrode is omitted from the illustration.
In the manufacturing method of this embodiment, a thin film transistor is formed by forming a bank on a glass substrate and forming an electrode pattern and a wiring pattern in a region surrounded by the bank by a droplet discharge method using a droplet discharge device IJ. This is a method for manufacturing a TFT array substrate.

<Gate electrode formation process>
First, as shown in each drawing of FIG. 2, a glass substrate P serving as a base is prepared, a bank 30 is formed on one side thereof, and then predetermined ink is dropped onto an opening 30 a provided in the bank 30. Thus, the gate electrode 80 (conductive layer) is formed in the opening 30a. This gate electrode formation step includes a bank formation step, a liquid repellency treatment step, a gate electrode formation step, and a firing step.

(Bank formation process)
First, in order to form the gate electrode 80 (and the scanning line 18a) in a predetermined pattern on the glass substrate, an opening having a predetermined pattern corresponding to the gate electrode 80 on the glass substrate P as shown in FIG. A bank 30 having 30a is formed. The bank 30 is a partition member that partitions the substrate surface in a plane, and any method such as a photolithography method or a printing method can be used to form the bank. For example, when using the photolithography method, an organic system such as an acrylic resin according to the height of the bank formed on the glass substrate P by a predetermined method such as spin coating, spray coating, roll coating, die coating, dip coating, etc. A photosensitive material is applied to form a photosensitive material layer. And the bank 30 provided with the opening part 30a for gate electrodes is formed by irradiating an ultraviolet-ray with respect to the photosensitive material layer according to the bank shape to form. The bank 30 may be an inorganic film formed from a photosensitive material having a polysilazane, polysiloxane, or polysilane skeleton.

(Liquid repellency treatment process)
Next, the bank 30 is subjected to a liquid repellency treatment to impart liquid repellency to the surface thereof. As the lyophobic treatment, for example, a plasma treatment method (CF ₄ plasma treatment method) using tetrafluoromethane as a treatment gas in an air atmosphere can be employed. The conditions of the CF ₄ plasma treatment are, for example, a plasma power of 50 kW to 1000 kW, a tetrafluoromethane gas flow rate of 50 ml / min to 100 ml / min, a substrate transfer speed to the plasma discharge electrode of 0.5 mm / sec to 1020 mm / sec, and a substrate temperature. Is 70 ° C to 90 ° C. The processing gas is not limited to tetrafluoromethane (carbon tetrafluoride), and other fluorocarbon gases can also be used.
By performing such a liquid repellency treatment, the bank 30 is introduced with a fluorine group in the resin constituting the bank 30 and imparted with high liquid repellency.

Prior to the liquid repellency treatment, an ashing treatment using O ₂ plasma or a UV (ultraviolet) irradiation treatment is performed for the purpose of cleaning the surface of the glass substrate P exposed on the bottom surface of the opening 30a. It is preferable. By performing this treatment, the residue of the bank on the surface of the glass substrate P can be removed, and the difference between the contact angle of the bank 30 after the lyophobic treatment and the contact angle of the substrate surface can be increased. In this step, the droplets arranged in the opening 30a can be accurately confined inside the opening 30a. Further, when the bank 30 is made of an acrylic resin or a polyimide resin, if the bank 30 is exposed to O ₂ plasma prior to the CF ₄ plasma treatment, it is more likely to be fluorinated (liquid repellent). Therefore, when the bank 30 is formed of these resin materials, it is preferable to perform the O ₂ ashing process prior to the CF ₄ plasma process.

Specifically, the O ₂ ashing process is performed by irradiating the glass substrate P with oxygen in a plasma state from a plasma discharge electrode. As the processing conditions, for example, the plasma power is 50 W to 1000 W, the oxygen gas flow rate is 50 ml / min to 100 ml / min, the plate conveyance speed of the substrate P with respect to the plasma discharge electrode is 0.510 mm / sec to 10 mm / sec, and the substrate temperature is 70. ° C to 90 ° C.

Note that the lyophobic treatment (CF ₄ plasma treatment) on the bank 30 has some influence on the surface of the substrate P made lyophilic by the residue treatment previously performed, but particularly when the substrate P is made of glass or the like. Since the introduction of fluorine groups due to the lyophobic treatment hardly occurs, the lyophilicity, that is, the wettability of the substrate P is not substantially impaired. Further, the bank 30 may be formed of a material having liquid repellency (for example, a resin material having a fluorine group), so that the liquid repellency treatment may be omitted.

(Gate electrode formation process)
Next, as shown in FIG. 2B, the gate electrode forming ink 80a is dropped from the droplet discharge head 301 of the droplet discharge device IJ into the opening 30a (gate electrode formation region) surrounded by the bank 30. To do. At this time, the liquid repellent property is imparted to the surface of the bank 30 and the lyophilic property is imparted to the substrate surface at the bottom of the opening 30a. Even if it is mounted on the surface, it is slid into the opening 30a by being repelled on the bank surface.

Here, the gate electrode forming ink 80a (liquid material) suitable for ejection from the droplet ejection head 301 used in the manufacturing method according to the present embodiment will be described.
As the gate electrode forming ink 80a of the present embodiment, a dispersion in which conductive fine particles are dispersed in a dispersion medium or a precursor thereof is further mixed with Pd particles (plating nuclei).

  Here, as conductive fine particles, in addition to metal fine particles containing, for example, Au, Ag, Cu, Pd, Nb and Ni, these precursors, alloys, oxides, conductive polymers, indium tin oxides, and the like Fine particles are used. These conductive fine particles can be used by coating the surface with an organic substance or the like in order to improve dispersibility. The particle diameter of the conductive fine particles is preferably about 1 nm to 0.1 μm. If it is larger than 0.1 μm, there is a possibility that clogging may occur in the nozzles of the liquid discharge head 301 described later, and the denseness of the resulting film may be deteriorated. On the other hand, if it is smaller than 1 nm, the volume ratio of the coating agent to the conductive fine particles becomes large, and the ratio of the organic matter in the obtained film becomes excessive.

The dispersion medium is not particularly limited as long as it can disperse the conductive fine particles and does not cause aggregation. For example, in addition to water, alcohols such as methanol, ethanol, propanol, butanol, n-heptane, n-octane, decane, dodecane, tetradecane, toluene, xylene, cymene, durene, indene, dipentene, tetrahydronaphthalene, decahydro Hydrocarbon compounds such as naphthalene and cyclohexylbenzene, ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol methyl ethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether, 1,2-dimethoxyethane, bis (2- Methoxyethyl) ether, ether compounds such as p-dioxane, propylene carbonate, γ- Butyrolactone, N- methyl-2-pyrrolidone, dimethylformamide, dimethyl sulfoxide, can be exemplified polar compounds such as cyclohexanone. Of these, water, alcohols, hydrocarbon compounds, and ether compounds are preferred from the viewpoints of fine particle dispersibility and dispersion stability, and ease of application to the droplet discharge method (inkjet method). More preferred dispersion media include water and hydrocarbon compounds.
In the present embodiment, the gate electrode forming ink 80a in which conductive fine particles of Ag (silver) are dissolved in a solvent (dispersion medium) of diethylene glycol diethyl ether is used.

  The surface tension of the conductive fine particle dispersion is preferably in the range of 0.02 N / m to 0.07 N / m. When the liquid is ejected by the ink jet method, if the surface tension is less than 0.02 N / m, the wettability of the ink composition to the nozzle surface increases, and thus flight bending tends to occur, exceeding 0.07 N / m. Since the meniscus shape at the nozzle tip is not stable, it becomes difficult to control the discharge amount and the discharge timing. In order to adjust the surface tension, a small amount of a surface tension regulator such as a fluorine-based, silicone-based, or nonionic-based material may be added to the dispersion within a range that does not significantly reduce the contact angle with the substrate. The nonionic surface tension modifier improves the wettability of the liquid to the substrate, improves the leveling property of the film, and helps prevent the occurrence of fine irregularities in the film. The surface tension modifier may contain an organic compound such as alcohol, ether, ester, or ketone, if necessary.

  The viscosity of the dispersion is preferably 1 mPa · s to 50 mPa · s. When a liquid material is ejected as droplets using the inkjet method, if the viscosity is less than 1 mPa · s, the nozzle periphery is easily contaminated by the outflow of the ink, and if the viscosity is greater than 50 mPa · s, the nozzle hole The clogging frequency in the case becomes high, and not only is it difficult to smoothly discharge droplets, but also the amount of droplets discharged is reduced.

The Pd particles contained in the gate electrode forming ink 80a function as a substance that selectively adsorbs a catalyst metal or a precursor for forming a catalyst metal for depositing a diffusion prevention layer by an electroless plating process described later. is there. In addition to the Pd particles described above, SnCl ₂ or PdCl ₂ (Pd ions), Pd salts such as PdCl ₂ , palladium nitrate and palladium acetate, SnPd colloidal dispersion, polyvinyl alcohol (PVA) or polyvinyl pyrrolidone ( Pd sol held by a water-soluble polymer such as PVP) can be suitably used.

  Next, after discharging droplets made of electrode forming ink, a drying process is performed as necessary to remove the dispersion medium. The drying process can be performed, for example, by a heating process using a normal hot plate or an electric furnace that heats the substrate P. In this embodiment, for example, heating is performed at 180 ° C. for about 60 minutes. This heating is not necessarily performed in the air, such as in a nitrogen gas atmosphere.

  This drying process can also be performed by lamp annealing. The light source used for lamp annealing is not particularly limited, but excimer lasers such as infrared lamps, xenon lamps, YAG lasers, argon lasers, carbon dioxide lasers, XeF, XeCl, XeBr, KrF, KrCl, ArF, ArCl, etc. It can be used as a light source. In general, these light sources have an output in the range of 10 W to 5000 W, but in the present embodiment, a range of 100 W to 1000 W is sufficient. By performing this intermediate drying step, a solid gate electrode 80 is formed as shown in FIG.

(Baking process)
The dried film after the discharging step needs to completely remove the dispersion medium in order to improve the electrical contact between the fine particles. In addition, when a coating agent such as an organic substance is coated on the surface of the conductive fine particles in order to improve the dispersibility in the liquid, it is also necessary to remove this coating agent. Therefore, the glass substrate P after the discharge process is subjected to heat treatment and / or light treatment.

  This heat treatment and / or light treatment is usually carried out in the atmosphere, but can also be carried out in an inert gas atmosphere such as nitrogen, argon or helium, if necessary. The treatment temperature of the heat treatment and / or the light treatment depends on the boiling point (vapor pressure) of the dispersion medium, the type and pressure of the atmospheric gas, the thermal behavior such as the dispersibility and oxidation of the fine particles, the presence and amount of the coating agent, Although it is determined as appropriate in consideration of the heat-resistant temperature and the like, even in such a configuration, since the gate electrode 80 is formed using the above-described materials, the baking temperature can be set to 250 ° C. or less. However, in this step, since the semiconductor layer is not provided on the glass substrate P, the firing temperature can be increased within the range of the heat resistance temperature of the bank 30, for example, a firing temperature of about 250 ° C. or higher, or about 300 ° C. Thus, a metal wiring having even better conductivity can be formed. In addition, it is preferable that the film thickness of the gate electrode 80 after a baking process shall be about 500 nm-1500 nm.

<Diffusion prevention layer forming step>
Next, a diffusion prevention layer 82 (barrier metal) is formed on the gate electrode 80 by electroless plating.
First, organic substances or the like attached to the surface of the gate electrode 80 are removed by ozone treatment or plasma ashing treatment. Next, lyophilicity is imparted to the surface of the gate electrode 80 from which organic substances have been removed by ozone water treatment or the like.

  Next, as shown in FIG. 2D, a diffusion prevention layer 82 is formed on the gate electrode 80 by electroless plating. Specifically, the glass substrate P on which Pd nuclei are formed on the gate electrode 80 is immersed in a plating bath in which conductive fine particles of Ni are dispersed and a reducing agent is dissolved for a predetermined time. Here, the gate electrode 80 contains Pd metal as a plating nucleus, and the metal Pd is uniformly dispersed in the gate electrode. Therefore, the Pd nucleus exposed on the surface of the gate electrode and buried in the upper layer of the gate electrode functions as a catalyst during the electroless plating process described later. Therefore, with the Pd nucleus 26 on the gate electrode 80 as a nucleus, Ni metal ions dissolved in the solution by the reducing agent of sodium hypophosphite are reduced to Ni metal, and Ni metal is deposited on the gate electrode 80. At this time, Ni metal is deposited and grown to the height of the bank 30. As a result, as shown in FIG. 2D, a diffusion prevention layer 82 made of Ni is selectively formed on the gate electrode 80 partitioned in the bank 30. As the reducing agent, in addition to the above, a commercially available product prepared by blending a reducing agent such as sodium borohydride and a complexing agent such as sodium potassium tartrate can be used.

  The film thickness of the diffusion preventing layer 82 is preferably about 20 nm to 400 nm. If the thickness of the diffusion prevention layer 82 is less than 20 nm, the diffusion of the metal element from the gate electrode 80 to the gate insulating film 83 described later cannot be sufficiently prevented, and if the thickness exceeds 400 nm, the gate electrode 80 (and This is not preferable because the resistance of the scanning line 18a) increases.

  In each of the above steps, a gate electrode 80 made of Ag and a diffusion prevention layer 82 made of Ni are formed, but the gate electrode 80 is made of a metal other than Ag, such as Cu or Al, or these metals. An alloy having a main component may be used. The diffusion preventing layer 82 may be Ti, W, Mn other than Ni, or an alloy containing these metals as a main component.

  In this embodiment, as a method for forming the diffusion prevention layer 82 for preventing diffusion on the gate electrode 80, the plating nucleus adsorption film 20 is selectively formed on the gate electrode 80 by the droplet discharge method as described above. Then, after the Pd nuclei 26 are adsorbed on the plating nucleus adsorption film 20, a diffusion preventing material is selectively deposited on the gate electrode 80 by the electroless plating process using the Pd nuclei 26 as a catalyst to form the diffusion preventing layer 82. Forming. This method of forming the diffusion prevention layer 82 is also applied to the diffusion prevention layer 82 formed below and above the source and drain electrodes described below.

<Gate insulation film formation process>
Next, as shown in FIG. 3A, a gate insulating film 83 made of silicon nitride is formed on the gate electrode 80. The gate insulating film 83 can be formed, for example, by depositing the entire surface by a plasma CVD method and then appropriately patterning by a photolithography method. As the source gas used in the CVD process, a mixed gas of monosilane and dinitrogen monoxide, TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ) and oxygen, disilane and ammonia, etc. are suitable, and the gate to be formed The film thickness of the insulating film 83 is about 150 nm to 400 nm.

<Semiconductor layer formation process>
Next, as shown in FIG. 3A, the semiconductor layer 33 is formed on the gate insulating film 83. This semiconductor layer 33 is formed by applying an amorphous silicon film having a thickness of about 150 nm to 250 nm and an N ⁺ silicon film having a thickness of about 50 nm to 100 nm on the entire surface of the glass substrate P on which the gate insulating film 83 is formed. Is obtained by patterning into a predetermined shape by photolithography. Disilane or monosilane is suitable as the source gas used in the amorphous silicon film forming step. In the subsequent N ⁺ silicon film forming step, film formation can be performed by introducing a source gas for forming the N ⁺ silicon layer into the film forming apparatus used for forming the amorphous silicon film.

After that, the amorphous silicon film and the N ⁺ silicon film are patterned into the shape shown in FIG. 3A by photolithography, so that the amorphous silicon layer 84 and the N ⁺ silicon layer having a predetermined planar shape are formed on the gate insulating film 83. Thus, the semiconductor layer 33 in which 85 is stacked is obtained. At the time of patterning, a substantially concave resist similar to the side sectional shape of the semiconductor layer 33 shown in the figure is selectively placed on the surface of the N ⁺ silicon film, and etching is performed using the resist as a mask. By such a patterning method, the N ⁺ silicon layer 85 is selectively removed in a region overlapping the gate electrode 80 in a plan view and divided into two regions. These N ⁺ silicon layers 85 and 85 are respectively connected to source contacts. Regions and drain contact regions are formed.

<Electrode formation process>
Next, the source electrode 34 and the drain electrode 35 are formed on the glass substrate P on which the semiconductor layer 33 is formed. This electrode forming step includes a bank forming step, a liquid repellency step, a first diffusion preventing layer forming step, an electrode film forming step, a second diffusion preventing layer forming step, and a firing step.

(Bank formation process)
After the amorphous silicon layer 84 and the N ⁺ silicon layer 85 are formed, a bank having openings corresponding to the pattern of the source electrode and the drain electrode is formed on the glass substrate P as shown in FIG. As described above, the bank can be formed by an arbitrary method such as a photolithography method or a printing method.

Here, two types of banks, that is, the first bank portion 31b and the second bank portion 31a are formed. First, as shown in FIG. 3B, the first bank portion 31b has an amorphous silicon layer. 84 and N ⁺ silicon layer, and exposure by ultraviolet irradiation is performed so as to be positioned at the substantially central portion of the amorphous silicon layer 84. That is, the first bank portion 31b is formed as a partition member that partitions the source electrode and the drain electrode formed in a subsequent process in a plane. On the other hand, as shown in FIG. 3B, the second bank portion 31 a is formed in a region outside the amorphous silicon layer 84 so as to surround the amorphous silicon layer 84. In the present embodiment, the left region in FIG. 3B divided into the first bank portion 31b and the second bank portion 31a is referred to as a source electrode formation region 34a, and the right region in FIG. 3B. Is referred to as a drain electrode formation region 35a.

Further, in order to remove a resist (organic matter) residue at the time of bank formation between the bank portions 31a and 31b, it is preferable to perform a residue treatment. As this residue treatment, a UV irradiation treatment for performing a residue treatment by irradiating ultraviolet rays, an O ₂ ashing treatment using oxygen as a processing gas in an air atmosphere, or the like can be selected. Here, an O ₂ ashing treatment is performed. The condition of the ashing process may be the same as the condition used when patterning the bank 30 previously.

(Liquid repellency treatment process)
Next, by a method similar to the above-described method, a liquid repellency treatment is performed on the bank portions 31a and 31b by a plasma treatment method or the like to impart liquid repellency to the surfaces of the bank portions 31a and 31b.

(First diffusion prevention material arrangement process)
Next, as shown in FIG. 3C, the first diffusion prevention layer 61 is formed in a region surrounded by the first bank portion 31b and the second bank portion 31a. In the above-described method of forming the diffusion prevention layer 82 by electroless plating, Pd metal serving as a catalyst is added to the conductive layer, so that it is formed below the conductive layer (source electrode, drain electrode). It is difficult to apply. Therefore, in this embodiment, the diffusion prevention layer 82 formed under the source electrode and the drain electrode is formed by a droplet discharge method instead of the electroless plating method.

  First, organic substances and the like attached to the source electrode formation region 34a and the drain electrode formation region 35a surrounded by the first bank portion 31b and the second bank portion 31a are removed by plasma ashing or the like. Next, the source electrode formation region 34a and the drain electrode formation region 35a from which organic substances have been removed are hydrophilized by ozone water treatment or the like.

  Next, the first diffusion preventing layer forming ink is disposed in the opening 30 a of the bank 30 by the droplet discharge device IJ. As the first diffusion preventing layer forming ink, an ink in which conductive fine particles such as Ni (nickel) are dispersed in water and a solvent (dispersion medium) such as diethanolamine is used. At this time, the liquid repellent property is imparted to the surface of the bank 30 and the lyophilic property is imparted to the substrate surface at the bottom of the opening 30a. Even if it is mounted on the surface, it is slid into the opening 30a by being repelled on the bank surface.

(Drying process)
Next, in order to remove the solvent in the ink 82a, the applied ink is dried using a hot plate or the like as necessary. In this embodiment, for example, 180 ° C. heating is performed for about 60 minutes. This heating is not necessarily performed in the air, such as in an N ₂ atmosphere.

(Baking process)
Next, it is necessary to completely remove the dispersion medium in order to improve electrical contact between the fine particles. Further, when a coating agent such as an organic substance is coated on the surface of the conductive fine particles in order to improve dispersibility, it is also necessary to remove this coating agent. Therefore, the substrate after the drying step is subjected to heat treatment and / or light treatment.
In this way, as shown in FIG. 3C, the first diffusion prevention layer 61 is straddled across the gate insulating film 83 and the N ⁺ silicon layer 85 in each of the source electrode formation region 34a and the drain electrode formation region 35a. Form.

(Electrode film forming process)
Next, as shown in FIG. 4A, ink for forming electrodes (source electrode and drain electrode) is applied onto the first diffusion preventing layer 61 by the droplet discharge device IJ. As the source electrode and drain electrode forming ink, a dispersion liquid in which conductive fine particles are dispersed in a dispersion medium, or a precursor thereof, in which Pd particles (plating nuclei) are further mixed, is used. The plating nucleus is not limited to Pd particles, and as described above, an aqueous colloid solution in which SnCl ₂ or PdCl ₂ is dispersed in a dispersion medium may be added to the ink.

  In this electrode film process, ink for forming an electrode film is discharged as a droplet from a droplet discharge head, and the droplet is a source electrode surrounded by the first bank portion 31b and the second bank portion 31a on the substrate P. It arrange | positions in the formation area 34a and the drain electrode formation area 35a. At this time, since the liquid repellent properties are imparted to the surfaces of the bank portions 31a and 31b, even if some of the ejected droplets are placed on the bank portions 31a and 31b, the bank surfaces become liquid repellent. As a result, the ink that is repelled and dripped on the surfaces of the bank portions 31a and 31b flows down to the regions 34a and 35a.

  Prior to this electrode film forming step, an intermediate layer for improving the wettability of the ink may be formed on the surface of the first diffusion prevention layer 61 previously formed. As this intermediate layer, for example, Mn or the like can be used, and a droplet discharge method can be used for the film formation.

(Drying process)
After discharging the droplets, a drying process is performed as necessary by the same method as described above to remove the dispersion medium. By performing this intermediate drying step, as shown in FIG. 4A, the source electrode 34 and the drain electrode 35 are formed on the diffusion preventing layers 61 and 61, respectively.

(Baking process)
Next, in order to improve electrical contact between the fine particles of the source electrode 34 and the drain electrode 35 after the discharging process, the dispersion medium is completely removed by heat treatment and / or light treatment.

(Second diffusion prevention layer forming step)
Next, as shown in FIG. 4B, second diffusion preventing layers 68 and 68 are formed on the source electrode 34 and the drain electrode 35 surrounded by the first bank portion 31b and the second bank portion 31a. Since the second diffusion preventing layer is formed on the conductive layer (source electrode and drain electrode), it can be formed by the same method as the diffusion preventing layer 61 formed on the gate electrode 80.

  First, organic substances and the like attached on the source electrode 34 and the drain electrode 35 surrounded by the first bank portion 31b and the second bank portion 31a are removed by plasma ashing or the like. Next, the surface of the gate electrode 80 from which organic substances have been removed is hydrophilized by ozone water treatment or the like.

  Next, a diffusion prevention layer 68 is formed on the source electrode 34 and the drain electrode 35 by electroless plating. Specifically, the glass substrate P having Pd nuclei formed on the source electrode 34 and the drain electrode 35 is immersed in a plating bath in which conductive fine particles of Ni are dispersed and a reducing agent is dissolved for a predetermined time. Then, with the Pd nucleus 26 on the source electrode 34 and the drain electrode 35 as nuclei, Ni metal ions dissolved in the solution by the reducing agent of sodium hypophosphite are reduced to Ni metal, and the source electrode 34 and the drain electrode 35. Ni metal is deposited on top. At this time, Ni metal is deposited and grown to the height of the bank 30. As a result, second diffusion prevention layers 68 and 68 made of Ni are selectively formed on the source electrode 34 and the drain electrode 35 partitioned by the first bank portion 31b and the second bank portion 31a.

  In the present embodiment, the first diffusion prevention layer 61 and the second diffusion prevention layer 68 are preferably about 20 nm to 400 nm in thickness. The film thickness of the source electrode 34 and the drain electrode 35 is preferably about 500 nm to 1500 nm. If the film thickness of the first diffusion preventing layer 61 is less than 20 nm, the diffusion of the metal element from the source electrode 34 and the drain electrode 35 to the semiconductor layer 33 cannot be sufficiently prevented, and if the film thickness exceeds 400 nm, the source electrode 34 (and the data line 16) and the drain electrode 35 are undesirably increased in resistance. Further, when the thickness of the second diffusion preventing layer 68 is less than 20 nm, the diffusion of the metal element from the source electrode 34 and the drain electrode 35 to the later-described bank 31c (see FIG. 4B) and the liquid crystal layer is sufficiently prevented. If the film thickness exceeds 400 nm, the resistance of the source electrode 34 and the drain electrode 35 increases, which is not preferable.

  In each of the above steps, the source electrode 34 and the drain electrode 35 are made of Ag. However, for example, Cu, Al, or an alloy containing these metals as a main component may be used. Further, the first diffusion preventing layer 61 and the second diffusion preventing layer 68 are made of Ni, but Ti, W, Mn, or an alloy mainly containing these metals may be used.

<Bank removal process>
Next, as shown in FIG. 4C, the first bank portion 31b and the second bank portion 31a formed on the glass substrate P are selectively removed. In this removal step, the bank portions 31a and 31b are removed by an ashing process such as plasma ashing or ozone ashing. Plasma ashing is a method in which a gas such as oxygen gas converted into plasma reacts with a bank, and the bank is vaporized and removed. Ozone ashing is a method in which ozone (O ₃ ) is decomposed into active oxygen, and the active oxygen and the bank are reacted to vaporize and remove the bank. By this bank removal step, a thin film transistor (TFT) 60 formed on the glass substrate P can be obtained as shown in FIG.

<Pixel electrode formation process>
Next, the pixel electrode 19 is formed on the glass substrate P on which the TFT 60 is formed. This pixel electrode forming process includes a bank forming process, a liquid repellent treatment process, a liquid material arranging process, and a baking process.

(Bank formation process)
Next, as shown in FIG. 5A, a bank 31 c for forming the pixel electrode 19 is formed at a predetermined position on the substrate P. The bank 31c is formed so as to partially cover the TFT 60, and is formed in a substantially lattice shape surrounding each pixel electrode 19 in plan view. The bank 31c can be formed by an arbitrary method such as a photolithography method or a printing method. For example, when using the photolithography method, an organic photosensitive material mainly composed of an acrylic resin or the like according to the height of the bank 31c to be formed by a predetermined method such as spin coating, spray coating, roll coating, die coating, or dip coating. A photosensitive material is applied to form a photosensitive material layer, and then the photosensitive material layer is irradiated with ultraviolet rays in accordance with the bank shape.
Here, among the constituent members of the TFT 60, the bank 31c is patterned so that the drain electrode 35 protrudes into a region surrounded by the bank 31c. In the patterning of the bank 31c, since the second diffusion prevention layer 68 is formed on the surface portion of the existing drain electrode 35 on the substrate P, the etching solution enters the source electrode 34 and the drain electrode 35 and enters them. Can be prevented from eroding. Further, as described above, the bank 31c may be an inorganic film formed from a photosensitive material having a polysilazane, polysiloxane, or polysilane skeleton.

In addition, in order to remove a resist (organic matter) residue at the time of bank formation in a region surrounded by the bank 31c, it is preferable to perform residue processing such as UV irradiation processing and O ₂ ashing processing by the same method as described above. .

(Liquid repellency treatment process)
Subsequently, a liquid repellency treatment is performed on the bank 31c to impart liquid repellency to the surface. As the lyophobic treatment, the same treatment method as that described above can be used.
Although the surface of the gate insulating film 83 made lyophilic by the residue treatment performed previously is somewhat affected by the lyophobic treatment for the bank 31c, introduction of fluorine groups into the gate insulating film 83 by the lyophobic treatment is performed. Is unlikely to occur, so its lyophilicity (wetting) is not impaired. Further, when the bank 31c is formed of a liquid repellent material (for example, a resin material having a fluorine group), the liquid repellent treatment can be omitted.

(Liquid material arrangement forming process)
Next, ink (liquid material) for forming a pixel electrode is applied to a region surrounded by the bank 31c by using a droplet discharge method by the droplet discharge device IJ. Here, ink in which fine particles of a light-transmitting conductive material such as ITO, IZO, or FTO are dispersed in a solvent (dispersion medium) is ejected. An ink containing a precursor of the light-transmitting conductive material or a metal organic compound may be used.

(Drying process)
Next, after discharging droplets made of electrode forming ink, a drying process is performed as necessary by the same method as described above in order to remove the dispersion medium. By performing this intermediate drying step, a desired pixel electrode 19 is formed as shown in FIG.

(Baking process)
The dried film after the discharging process needs to completely remove the dispersion medium in order to improve the electrical contact between the fine particles. Further, when a coating agent such as an organic substance is coated on the surface of the conductive fine particles in order to improve dispersibility, it is also necessary to remove this coating agent. For this reason, the substrate after the discharge process is subjected to heat treatment and / or light treatment.

  As a result of the above process, the dry film after the discharge process ensures electrical contact between the fine particles and is converted into a conductive film. As a result, the pixel electrode 19 is formed on the substrate P, and the TFT array substrate provided with the thin film transistor 60 Can be manufactured.

  Note that the method for manufacturing the thin film transistor described in each embodiment can be applied to a method for manufacturing various electro-optical devices including the thin film transistor. For example, it is preferably employed when forming a thin film transistor such as a liquid crystal device, an organic electroluminescence display device, or a plasma display device.

  According to the present embodiment, since the gate electrode forming ink 80a disposed in the bank 30 contains the Pd nuclei 26, when the substrate P is subjected to electroless plating, the Pd nuclei 26 contained in the gate electrode forming ink 80a are changed. It functions as a catalyst (seed layer) and selectively deposits only on the gate electrode 80. Further, since the diffusion prevention layer 82 is formed by the electroless plating method, the diffusion prevention layer 82 having a high density and good adhesion can be formed at a temperature equal to or lower than the melting point of the bank 30. Thereby, it is possible to prevent the elemental material constituting the gate electrode 80 from diffusing to other layers. Further, since the plating nucleus is contained in the gate electrode forming ink 80a, it is not necessary to provide a separate catalyst treatment step for depositing a diffusion preventing material on the gate electrode 80, and the total number of steps can be reduced. Cost reduction can be achieved.

  According to this method, it is possible to selectively deposit a metal such as Ni on the gate electrode 80 by using Pd as a plating nucleus serving as a catalyst.

  According to this method, the photolithography process and the etching process can be reduced, and the process is greatly simplified. In addition, by selectively disposing the plating nucleus on the gate electrode 80, the amount of material used can be reduced, and productivity can be improved.

<Liquid crystal display device>
FIG. 6 is an equivalent circuit diagram showing the liquid crystal display device 100 including the TFT array substrate having the thin film transistor 60 formed by the method described above.
In the liquid crystal display device according to the present embodiment, a pixel electrode 19 and a TFT 60 that is a switching element for controlling the pixel electrode 19 are respectively formed on a plurality of dots arranged in a matrix that forms an image display region. The data line (electrode wiring) 16 to which the image signal is supplied is electrically connected to the source of the TFT 30. Image signals S1, S2,..., Sn to be written to the data lines 16 are supplied line-sequentially in this order, or are supplied for each group to a plurality of adjacent data lines 16. Further, the scanning line (electrode wiring) 18a is electrically connected to the gate of the TFT 60, and the scanning signals G1, G2,..., Gm are pulse-sequentially line-sequentially at a predetermined timing with respect to the plurality of scanning lines 18a. Applied. Further, the pixel electrode 19 is electrically connected to the drain of the TFT 60. By turning on the TFT 60, which is a switching element, for a predetermined period, the image signals S1, S2,. Write at the timing.

  Image signals S1, S2,..., Sn written at a predetermined level on the liquid crystal via the pixel electrode 19 are held for a certain period with a common electrode described later. Then, the light is modulated by utilizing the change in the orientation and order of the molecular assembly of the liquid crystal according to the applied voltage level, thereby enabling arbitrary gradation display. Each dot is provided with a storage capacitor 70 in parallel with the liquid crystal capacitor formed between the pixel electrode 19 and the common electrode in order to prevent the image signal written in the liquid crystal from leaking. Reference numeral 18b denotes a capacitor line connected to an electrode on one side of the storage capacitor 70.

Next, FIG. 7 is an overall configuration diagram of the liquid crystal display device 100.
The liquid crystal display device 100 has a configuration in which the TFT array substrate 10 and the counter substrate 25 are bonded together via a sealing material 52 having a substantially rectangular frame shape in plan view, and is sandwiched between the substrates 10 and 25. The liquid crystal thus formed is sealed between the substrates by a sealing material 52. In FIG. 7, the outer peripheral end of the counter substrate 25 is displayed so as to coincide with the outer peripheral end of the sealing material 52 in plan view.

  In a region inside the sealing material 52, a light shielding film (peripheral parting) 53 made of a light shielding material is formed in a rectangular frame shape. In the peripheral circuit area outside the sealing material 52, the data line driving circuit 201 and the mounting terminal 202 are disposed along one side of the TFT array substrate 10, and scanning is performed along two sides adjacent to the one side. Line drive circuits 104 and 104 are provided. On the remaining one side of the TFT array substrate 10, a plurality of wirings 105 are formed for connecting the scanning line driving circuits 104, 104. In addition, a plurality of inter-substrate conductive members 106 for providing electrical continuity between the TFT array substrate 10 and the counter substrate 25 are disposed at corner portions of the counter substrate 25.

Next, FIG. 8 is a plan configuration diagram showing a pixel configuration of the liquid crystal display device 100.
As shown in FIG. 8, in the display area of the liquid crystal display device 100, a plurality of scanning lines 18a extend in the horizontal direction in the figure, and a plurality of data lines 16 extend in a direction intersecting these scanning lines. is doing. In FIG. 8, a rectangular region in plan view surrounded by the scanning line 18a and the data line 16 is a dot region. A color filter of one of the three primary colors is formed corresponding to one dot region, and one pixel region having three colored portions 22R, 22G, and 22B is formed by the three dot regions shown. These colored portions 22R, 22G, and 22B are periodically arranged in the display area of the liquid crystal display device 100.

  In each dot region shown in FIG. 8, a pixel electrode 19 having a substantially rectangular shape in a plan view made of a light-transmitting conductive film such as ITO (indium tin oxide) is provided. A TFT 60 is interposed between the data line 16 and 18a. The TFT 60 includes a semiconductor layer 33, a gate electrode 80 provided on the lower layer side (substrate side) of the semiconductor layer 33, a source electrode 34 provided on the upper layer side of the semiconductor layer 33, and a drain electrode 35. Has been. A channel region of the TFT 30 is formed in a region where the semiconductor layer 33 and the gate electrode 80 face each other, and a source region and a drain region are formed in the semiconductor layers on both sides thereof.

The gate electrode 80 is formed by branching a part of the scanning line 18 a in the extending direction of the data line 16, and the semiconductor layer 33 and a not-shown insulating film (gate insulating film) are interposed at the tip portion thereof. It faces the vertical direction of the page. The source electrode 34 is formed by branching a part of the data line 16 in the extending direction of the scanning line 18a, and is electrically connected to the semiconductor layer 33 (source region). One end (left end in the drawing) side of the drain electrode 35 is electrically connected to the semiconductor layer 33 (drain region), and the other end (right end in the drawing) side of the drain electrode 35 is electrically connected to the pixel electrode 19. ing.
In the above configuration, the TFT 60 is turned on for a predetermined period by a gate signal input via the scanning line 18a, whereby an image signal supplied via the data line 16 is supplied to the liquid crystal at a predetermined timing. On the other hand, it functions as a switching element for writing.

FIG. 9 is a cross-sectional configuration diagram of the TFT array substrate 10 constituting the liquid crystal display device 100 along the line BB ′ in FIG.
Looking at the cross-sectional structure shown in the figure, a bank 30 with a part opened is formed on the glass substrate P, and a gate electrode 80 made of a metal material such as Ag, Cu, Al or the like is formed in the opening of the bank 30. Is buried. A diffusion prevention layer and an inorganic resist layer are stacked on the gate electrode 80. The diffusion prevention layer is made of one or more metal materials selected from Ni, Ti, W, Mn, etc., and is formed so as to cover the entire surface of the gate electrode 80. Thereby, the diffusion of the metal material of the gate electrode 80 to the other layer can be prevented.

A gate insulating film 83 made of silicon oxide, silicon nitride, or the like is formed on the bank 30, and the semiconductor layer 33 is formed on the gate insulating film 83 at a position overlapping the gate electrode 80 in a plan view. Yes. The semiconductor layer 33 includes an amorphous silicon layer 84 and an N ⁺ silicon layer 85 stacked on the amorphous silicon layer 84. N ⁺ silicon layer 85, on the amorphous silicon layer 84 is divided into two portions which are planarly spaced, whereas N ⁺ silicon layer 85 (left side), the gate insulating film 83 above and the N ⁺ The source electrode 34 formed over the silicon layer 85 is electrically connected, and the other N ⁺ silicon layer 85 is a drain formed over the gate insulating film 83 and the N ⁺ silicon layer 85. The electrode 35 is electrically connected.

  A diffusion prevention layer is formed in the lower layer and the upper layer of the source electrode 34 and the drain electrode 35, respectively. These diffusion prevention layers are formed so as to cover the source electrode 34 and the drain electrode 35 so as to prevent diffusion of the metal material of the source electrode 34 and the drain electrode 35 into the upper and lower layers (insulating layers). It has become. About the material of a diffusion prevention layer, it is the same as that of the diffusion prevention layer mentioned above.

  A bank 31 c is formed so as to cover a part of the surface of the drain electrode 35 and the source electrode 34. The banks 31c are actually formed on the glass substrate P in a substantially lattice shape in plan view having openings corresponding to the respective pixel electrodes 19 shown in FIG. Sometimes, it is used as a partition member for patterning the pixel electrode 19 using a liquid phase method. As shown in FIG. 9, the pixel electrode 19 is formed so as to be in contact with the upper surface and the side surface of the drain electrode 35 protruding from the insulating film 31 c to the right side in the drawing, and is electrically connected to the drain electrode 35.

According to the present embodiment, the dense and good diffusion preventing layer 82 formed by the above-described method is formed on the gate electrode 80. Thereby, the metal material of the gate electrode 80 can be prevented from diffusing into the gate insulating film 83 formed on the gate electrode 80 by the heat treatment.
Similarly, since the first diffusion prevention layer 61 below the source electrode 34 and the drain electrode 35 and the second diffusion prevention layer 68 above the upper layer are formed, a metal material such as the source electrode 34 is formed on the gate insulation. Diffusion to the film 83 and the bank 31c formed in the upper layer can be prevented. Therefore, it is possible to avoid the occurrence of a leakage current due to the deterioration of the insulating property of the gate insulating film 83, and it is possible to obtain the TFT 60 excellent in operation reliability.

(Electronics)
FIG. 10 is a perspective view showing an example of an electronic apparatus according to the invention.
A cellular phone 1300 shown in this figure includes the liquid crystal display device of the present invention as a small-sized display portion 1301 and includes a plurality of operation buttons 1302, an earpiece 1303, and a mouthpiece 1304.
The electro-optical device according to each of the embodiments is not limited to the mobile phone, but is an electronic book, a personal computer, a digital still camera, a video monitor, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic It can be suitably used as an image display means for devices such as notebooks, calculators, word processors, workstations, videophones, POS terminals, and touch panels.
According to this embodiment, since the liquid crystal display device having the above-described TFT having excellent operational reliability is provided, an electronic device that has excellent reliability and can be provided at low cost can be obtained.

It should be noted that the technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention.
In the above embodiment, the diffusion preventing layer is formed of Ni metal, but the present invention is not limited to this, and other metals can also be used. For _example, to form Ti, TiN, TiSi 2, Ta , TaN, W, WN, and WSi 2, Co, CoSi2, and any single Mn, or diffusion barrier layer by using conductive particles composed of these alloys It is also preferable.

  Further, in the above embodiment, a droplet discharge method using the droplet discharge device IJ is adopted to dispose the conductive material or the like. As another method, for example, a Cap coating method as shown in FIG. 11 is used. It can also be adopted. The Cap coating method is a film forming method using a capillary phenomenon, and when a slit 71 is inserted into the coating liquid 70 and the coating liquid level is raised in this state, a liquid deposit 72 is generated at the upper end of the slit 71. The coating liquid 70 can be applied to the surface of the substrate P by bringing the substrate P into contact with the liquid deposit 72 and translating the substrate P in a predetermined direction.

(A) is a figure which shows an example of a droplet discharge apparatus, (b) is the schematic of an ejection head. Sectional process drawing for demonstrating the manufacturing method of a thin-film transistor. Sectional process drawing for demonstrating the manufacturing method of a thin-film transistor. Sectional process drawing for demonstrating the manufacturing method of a thin-film transistor. Sectional process drawing for demonstrating the manufacturing method of a thin-film transistor. 1 is an equivalent circuit diagram of a liquid crystal display device according to an embodiment. The top view which shows the whole structure same as the above. FIG. 2 is a plan configuration diagram showing one pixel region. The partial cross section block diagram of a TFT array board | substrate same as the above. FIG. 11 is a perspective configuration diagram illustrating an example of an electronic device. The schematic sectional drawing for demonstrating Cap coat method.

Explanation of symbols

26 ... Pd nucleus (plating nucleus), 30 ... bank, 80 ... gate electrode (conductive layer), 80a ... ink for gate electrode formation (conductive material), 82 ... diffusion prevention layer (barrier metal), P ... substrate

Claims (6)

A partition formation step of forming a partition on the substrate;
A conductive material arranging step of arranging a conductive material containing a plating nucleus in a pattern forming region surrounded by the partition;
A conductive layer forming step of baking the conductive material disposed in the pattern formation region to form a conductive layer;
On the conductive layer, a diffusion prevention layer forming step of forming a diffusion prevention layer using the plating nucleus as a catalyst by an electroless plating method;
The pattern formation method characterized by having. In the conductive material arranging step,
The pattern forming method according to claim 1, wherein Pd is used for the plating nucleus. In the conductive material arranging step,
The pattern forming method according to claim 1, wherein the conductive material is disposed by a droplet discharge method or a dispenser method. A gate electrode provided on the substrate, and a semiconductor layer disposed on the gate electrode so as to face each other with an insulating film interposed therebetween,
4. A thin film transistor, wherein a diffusion prevention layer formed by the pattern forming method according to claim 1 is provided between the gate electrode and the semiconductor layer. A source electrode and a drain electrode connected on the semiconductor layer;
The diffusion prevention layer formed by the pattern formation method of any one of Claims 1 thru | or 3 was provided in at least any one of the upper layer of the said source electrode, and the said drain electrode, It is characterized by the above-mentioned. Thin film transistor.   An electronic apparatus comprising the thin film transistor according to claim 4.

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