JP2007115402A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multivalued nonvolatile semiconductor storage device that reduces data read time and data write time. <P>SOLUTION: A nonvolatile semiconductor storage device 1000 transmits/receives data by j bits (for example, 8 bits) to/from a data input/output terminal 10. Each of memory cells in a memory cell array 100 holds n bit data correspondingly to 2<SP>n</SP>threshold levels. A write data conversion circuit 230 generates write data from bit data input from the same data input/output terminal in a plurality of j bit data sets input at different timing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of storing information of four values or more (information of two bits or more) in one memory cell. More specifically, the present invention relates to an electrically rewritable nonvolatile semiconductor memory device such as a flash memory.

  In order to cope with an increase in the storage capacity of a nonvolatile semiconductor memory device such as a flash memory, a configuration capable of storing multilevel data exceeding binary data in one memory cell has been developed.

  FIG. 118 is a schematic block diagram showing an overall configuration of a conventional AND type flash memory 8000.

  The memory cell array 100 has a large number of memory cells including a floating gate and a control gate. In FIG. 118, memory cell array 100 is divided into two memory cell blocks 100R and 100L.

  The control gate of the memory cell is connected to the word line WL, the drain of the memory cell is connected to the bit line BL, and the source of the memory cell is connected to a source line SCL (not shown).

  Typically, one word line WL and one bit line BL are shown. The row decoder 110 selectively drives the word line based on an address signal given from the outside. A sense latch circuit 120 is provided on one end side of the bit line BL. Bit line BL is selected based on a selection signal output from column decoder 130, and read data and write data are exchanged with the selected bit line.

  In FIG. 118, although not shown, the sense latch circuit 120 includes a column switch circuit for selecting a bit line based on a selection signal from the column decoder 130.

  An address signal is supplied from the address buffer 140 to the column decoder 130 and the row decoder 110.

  The chip control unit 200 receives an access control signal and a clock signal (not shown) from the outside, and controls the internal circuit of the flash memory as a whole for the write control and read control of the memory cell in accordance with this. The chip control unit 200 controls the power supply generation unit 150 to switch the operation voltage of a word driver (not shown) that drives the potential of the word line according to the operation mode such as erasing, writing, and reading. Done.

  Data latch circuits DL-L and DL-R are data buffers that temporarily hold data exchanged in data write and read operations.

  The operation mode of the flash memory is not particularly limited, but is instructed by an access control signal supplied to the chip control unit 200 from the outside or command data supplied via a data bus or the like, and data rewriting (erasing and writing) ) And data read mode.

  In the conventional AND type quaternary flash memory shown in FIG. 118, the information storage state of one memory cell is an erase state, a first write state, a second write state, or a third write state. One state selected from the inside. The four information storage states in total correspond to states determined by 2-bit data. That is, 2-bit data can be stored in one memory cell.

  Therefore, flash memory 8000 sets three different write verify voltages to be applied to the word line during the write operation, and sequentially switches these to perform the write operation in three steps.

  In each of these write operations, the chip control unit 200 writes a binary (1 bit) held in a sense latch SL (sense latch SL included in the sense latch circuit 120) connected to a memory cell to be written. The corresponding write verify voltage is set for each write operation in which the write operation of embedded data “0” or “1” (“L” or “H”) is divided into the above three times. Control. With such a configuration, as will be described in detail later, it is possible to write 4-level (2-bit) information in one memory cell.

  Flash memory 8000 also sets three types of voltages as word line selection levels to be applied to the word lines during a read operation, and sense latches binary (1 bit) data read from the memory cell in three read operations. After taking in through the circuit 120 and completing the read operation three times, the chip control unit 200 converts the information into quaternary (2-bit) information.

The outline of the write operation and the read operation will be described below.
In the write operation, a binary (1 bit) data string to be written is fetched from the data input / output terminal group 10 and an address signal is fetched from the address signal input terminal 12 to the address buffer / data input / output buffer 140, respectively.

  The chip control circuit 200 separates the data string to be written into binary (1 bit) into an upper bit data string and a lower bit data string (or an odd bit data string and an even bit data string). The data latches DL-L and DL-R (hereinafter referred to as non-selection selection latches) connected to the non-selection memory cells in the memory cell array 100 are respectively transferred through the signal line 20 and temporarily latched.

  Then, the chip control unit 200 includes “write 1 (write operation for obtaining the first write state)”, “write 2 (write operation for obtaining the second write state)”, For each operation of “write 3 (write operation for obtaining the third write state)”, the data held in the data latches DL-L and DL-R is taken in through the signal line 20 and , “Write 1”, “Write 2”, “Write 3”, binary (1 bit) data “corresponding to 4-value (2 bits) data to be written to the selected memory cell” Convert to 0 ”or“ 1 ”. Further, the chip control unit 200 transfers the converted data to the sense latch SL in the sense latch circuit 120 connected to the selected memory cell through the signal line 18 and is latched by the selected sense latch SL. According to the binary data, each of the above-described “write 1”, “write 2”, and “write 3” write operations is performed.

  In this way, the binary data divided into the upper bit string and the lower bit string is temporarily held in the data latches DL-L and DL-R, and the three write operations “write” with different verify voltages are performed. 1 "to" write 3 "), the chip control unit 200 forms write data to binary (1 bit), and performs write operations with different verify voltages, so that one memory cell is written. 4-value (2-bit) information can be written.

  In the read operation, three different voltages are sequentially applied to the same selected word line WL, and binary values read from the memory cells in the memory cell array 100 to the selected sense latch by each of the three read operations. (1 bit) of information “0” or “1” is transferred to the data latches DL-L and DL-R, respectively, and temporarily held. Three kinds of binary (1 bit) data “0” in the data string read by the three read operations and held in the data latches DL-L and DL-R and the data string latched in the selection sense latch Alternatively, “1” is transferred to the chip control circuit 200 through the signal lines 18 and 20.

  The chip control circuit 200 synthesizes the upper bit and the lower bit of the quaternary (2-bit) data based on the transferred data. The chip control circuit 200 outputs the synthesized upper and lower bits from the data input / output terminal group 10 via the data input / output buffer 140.

Hereinafter, the write operation and the read operation described above will be described in more detail.
[Conventional four-value data writing operation]
FIG. 119 is a diagram showing the relationship between the write data of the conventional binary AND type flash memory and the threshold value of the memory cell transistor. In the write operation and the read operation, data is written and read with reference to determination level Vj01.

  FIG. 120 is a diagram showing the relationship between the write data of the conventional 4-valued AND flash memory 8000 and the threshold value of the memory cell transistor. In the write operation and the read operation, data is written and read based on the three determination levels Vj1, Vj2, and Vj3.

  As described above, in the conventional 4-level AND flash memory 8000, as shown in FIG. 119, in the 2-level AND flash memory, the threshold value (Vth) of the memory cell transistor after writing is set to “0” and “1”. However, the threshold value after writing is divided into four types as shown in FIG.

  Therefore, three types of determination values Vj1, Vj2, and Vj3 are required to determine each level.

  121 to 126 show data latched in data latches DL-L and DL-R and sense latch SL in the first to third processing steps of the write operation and the threshold value of the memory cell after the write. It is a conceptual diagram.

  121 shows data held in the respective latches in the first processing step of the write operation, and FIG. 122 shows memory cell threshold values in the first processing step of the write operation.

  123 shows data held in the respective latches in the second processing step of the write operation, and FIG. 124 shows threshold values of the memory cells in the second processing step of the write operation.

  125 shows data held in the respective latches in the third processing step of the write operation, and FIG. 126 shows threshold values of the memory cells in the third processing step of the write operation.

  First, before the start of the write operation, processing for setting the threshold value of the memory cell to the determination level Vj1 or less is performed.

  Referring to FIGS. 121 and 122, in the first step of the write operation, out of 1-byte data DQ0-7 input from terminals I / O0-7 of data input / output terminal group 10, Data DQ0-3 are stored in data latch DL-R, and data DQ4-7 are stored in data latch DL-L. In the example of FIG. 121, it is assumed that the input 1-byte data is C9h in hexadecimal notation.

  For all the sectors (data corresponding to one word line), the input data DQ0-3 from the terminals I / O0-3 are input to the data latch DL-R, and the input data DQ4-from the terminals I / O4-7 are input. 7 are respectively latched in the data latches DL-L.

  Hereinafter, one of the data DQ4 to 7 held in the data latch DL-L is an upper bit, and one of the data DQ0 to 3 held in the data latch DL-R is a lower bit. Data, (DQ4, DQ0), (DQ5, DQ1) (DQ6, DQ2) (DQ7, DQ3) are considered as a set of data.

  First, the chip control unit 200 calculates the above-described data set included in the data latches DL-R and DL-L, so that the upper bit held in the data latch DL-L is “0”. Only the bit data of the sense latch SL corresponding to the data whose lower bit held in the data latch DL-R is “1” is set to the “0” level.

  As shown in FIG. 121, after such calculation, the sense latch SL holds data “0111” from the top. Based on the data held in the sense latch SL in this way, data is written into the memory cells MC1 to MC4 corresponding to the respective bits of the sense latch SL. Here, the memory cells MC1 to MC4 are connected to the same word line WL. Further, the third determination value Vj3 is used as the determination value for the verify operation.

  At this time, data is written to the memory cell corresponding to data “0” in the sense latch. Therefore, level 4 data (corresponding to data “01”) is written into memory cell MC4 corresponding to the most significant bit of the sense latch.

  The actual data writing is performed by applying a high voltage to the word line WL and utilizing an FN (Fowler-Nordheim) tunnel current.

  A voltage equal to or lower than the word line voltage is applied to the bit line BL corresponding to the bit whose bit data of the sense latch SL is “1” in order to relax the voltage applied from the word line WL. As a result, data is written only to the memory cells connected to the bit line BL corresponding to the bit data held in the sense latch of “0”.

  Next, referring to FIGS. 123 and 124, in the second step of the write operation, the data held in the data latches DL-R and DL-L is calculated, and the higher order held in the data latch DL-L. “0” is written in the bit of the sense latch SL corresponding to the data set in which the bit is “0” and the lower bit held in the data latch DL-R is “0”. In the data write after changing the determination value in the verify operation to Vj2, data is written only to the memory cells connected to the bit lines corresponding to the data DQ5 and DQ1.

  Next, referring to FIGS. 125 and 126, in the third step of the write operation, the data held in data latches DL-R and DL-L is operated, and the higher order held in data latch DL-L. “0” is written in the bit of the sense latch SL corresponding to the data set in which the bit is “1” and the lower bit held in the data latch DL-R is “0”. In the data write after changing the determination value in the verify operation to Vj1, data is written only to the memory cells connected to the bit lines corresponding to the data DQ6 and DQ2.

  As described above, after all the data to be written is input, the writing operation is completed through three operations and the writing process.

[Conventional four-value data read operation]
Next, the reading operation will be described.

  127 to 132 show the data latches DL-L and DL-R and the data held in the sense latch SL and the threshold value of the memory cell at the time of reading in the first to third processing steps of the reading operation. It is a conceptual diagram which shows a level.

  127 shows data held in the respective latches in the first processing step of the read operation, and FIG. 128 shows threshold values and determination levels of the memory cells in the first processing step of the read operation.

  FIG. 129 shows data held in the respective latches in the second processing step of the read operation, and FIG. 130 shows threshold values and determination levels of the memory cells in the second processing step of the read operation.

  131 shows data held in the respective latches in the third processing step of the read operation, and FIG. 132 shows thresholds and determination levels of the memory cells in the third processing step of the read operation.

  First, referring to FIGS. 127 and 128, in the first processing step of the reading operation, reading is performed at first determination level Vj1, and the result is stored in sense latch SL. The data is transferred to the data latch DL-R, and the sense latch SL is cleared.

  Next, referring to FIGS. 129 and 130, in the second processing step of the reading operation, reading is performed at second determination level Vj2, and the result is stored in sense latch SL. The data is transferred to the data latch DL-L, and the sense latch SL is cleared again.

  Finally, referring to FIGS. 131 and 132, in the third processing step of the read operation, data is read at third determination level Vj3, and the read result is stored in sense latch SL. The chip control circuit 200 sets the data in the data latch DL-R to “1” only at the bit position where the data stored in the sense latch SL and the data in the data latch DL-R are both “0”.

  The data latches DL-L to DQ4 to 7 and the data latches DL-R to DQ0 to 3 are sequentially output.

  As described above, also in the read operation, data output is performed after all of the three read operations are confirmed.

An example of a more detailed configuration of the multilevel memory is disclosed in, for example, Patent Document 1 and the like. However, in the read and write operations, it is necessary to perform a plurality of processing step operations in the same manner as the configuration of the multilevel memory described above.
JP-A-9-297996

  As described above, in the conventional AND type quaternary flash memory 8000, the delay due to the operation of a plurality of processing steps in both writing and reading is larger than that in the normal binary flash memory. The speed of the pull-in operation is degraded. Moreover, the deterioration of the speed becomes more serious as the number of values increases.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a nonvolatile semiconductor memory capable of suppressing deterioration in speed even when multi-value data is held in one memory cell. Is to provide a device.

A nonvolatile semiconductor memory device according to the present invention includes a memory cell array in which a plurality of memory cells are arranged, and each memory cell has a threshold voltage of first to second ⁿ (where n is an integer of 3 or more). ) Is selectively set to any one of the threshold levels, and any one of the 2 ⁿ different data codes is stored, and each data code is stored in the first To nth data. Here, the first threshold level is lower than the first determination level, and the Nth threshold level (where N is an integer greater than or equal to 2 and less than or equal to 2 ⁿ −1) is the (N− It is higher than the determination level of 1) and lower than the Nth determination level, and the ^2nth threshold level is higher than the ( ^2n- 1) ^th determination level. The first to second ⁿ threshold levels are 2 ⁿ data codes, i) in the first step, the first data of each data code is any of the first and second logics Ii) In the j-th step (where j is an integer greater than or equal to 2 and less than or equal to n), 2 ^{j-1 -th} ( j-1) Each of the groups is further divided into two j-th groups and rearranged according to whether the j-th data of each data code is the first or second logic. Correspond to those sorted by the procedure corresponding to the procedure. The ^first data of each data code corresponding to the ^first to second ^n-1 threshold levels is the first logic, and the (2 ^n-1 +1) to second ⁿ threshold levels. The first data of each corresponding data code is the second logic. In the (j−1) th group in which the (j−1) th data in the data code is the first logic, the jth data is the first in the data code in which the jth data is the first logic. It corresponds to a threshold level lower than that of the data code which is a logic of 2. In the (j−1) th group in which the (j−1) th data in the data code is the second logic, the data code in which the jth data is the first logic is more in the jth data. Corresponds to a higher threshold level than a data code of 2 logic. This non-volatile semiconductor memory device is a cell that collectively selects any one of a plurality of memory cells of a memory cell array (where m is an integer of 2 or more) in response to an address signal. Data for performing read / write operations of m data codes for m memory cells selected by the cell selection circuit based on the selection circuit and the first to (2 ⁿ -1) determination levels The first to nth data of m data codes are k bits (where k is a natural number) between the read / write circuit and the outside of the nonvolatile semiconductor device and the data read / write circuit. And a data input / output circuit for transferring data via k input / output nodes. The first to nth data of each data code is exchanged via the same input / output node at different timings.

Also, other non-volatile semiconductor memory device according to the invention includes a memory cell array having a plurality of memory cells are arranged, each memory cell, the threshold voltage is first to 2 ^{n (where,} n is 3 or more Each of the data codes is stored in a data code of ²ⁿ data codes that are different from each other. The code includes first to nth data. Here, the first threshold level is lower than the first determination level, and the Nth threshold level (where N is an integer greater than or equal to 2 and less than or equal to 2 ⁿ −1) is the (N− It is higher than the determination level of 1) and lower than the Nth determination level, and the ^2nth threshold level is higher than the ( ^2n- 1) ^th determination level. The first to second ⁿ threshold levels are 2 ⁿ data codes, i) in the first step, the first data of each data code is any of the first and second logics Ii) In the j-th step (where j is an integer greater than or equal to 2 and less than or equal to n), 2 ^{j-1 -th} ( j-1) Each of the groups is further divided into two j-th groups and rearranged according to whether the j-th data of each data code is the first or second logic. Correspond to those sorted by the procedure corresponding to the procedure. The ^first data of each data code corresponding to the ^first to second ^n-1 threshold levels is the first logic, and the (2 ^n-1 +1) to second ⁿ threshold levels. The first data of each corresponding data code is the second logic. In the (j−1) th group in which the (j−1) th data in the data code is the first logic, the jth data is the first in the data code in which the jth data is the first logic. It corresponds to a threshold level lower than that of the data code which is a logic of 2. In the (j−1) th group in which the (j−1) th data in the data code is the second logic, the data code in which the jth data is the first logic is more in the jth data. Corresponds to a higher threshold level than a data code of 2 logic. This non-volatile semiconductor memory device is a cell that collectively selects any one of a plurality of memory cells of a memory cell array (where m is an integer of 2 or more) in response to an address signal. A selection circuit, a data read circuit for reading out m data codes from m memory cells selected by the cell selection circuit based on the first to (2 ⁿ -1) determination levels, and a data read circuit Data to be output to the outside of the non-volatile semiconductor memory device through k output nodes for every k bits (where k is a natural number) of the first to nth data of the read m data codes And an output circuit. The first to nth data of each data code is output via the same output node at different timings.

  As described above, according to the present invention, multi-value data stored in one memory cell is generated from data exchanged at different timings. Therefore, in read operation, data is determined every time each bit data is determined. Output can be performed, and data output time can be shortened.

  In addition, since multi-value data stored in one memory cell is generated from data exchanged at different timings, data can be written every time each bit data is determined in the write operation. Input time can be shortened.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing a configuration of a flash memory 1000 which is a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention.

  The memory cell array 100 has a large number of memory cells including a floating gate and a control gate. Also in FIG. 1, the memory cell array 100 is divided into two memory cell blocks 100R and 100L.

  The control gate of the memory cell is connected to the word line WL, the drain of the memory cell is connected to the bit line BL, and the source of the memory cell is connected to a source line SCL (not shown).

Two word lines WL and two bit lines BL are typically shown.
Row decoder 110 selectively drives word lines based on address signals A0-Ak supplied from outside via address signal input terminal group 12 and address buffer 146. A sense latch circuit 120 is provided on one end side of the bit line BL. Bit line BL is selected based on a selection signal output from column decoder 130 according to address signals A0-Ak, and read data and write data are exchanged with the selected bit line.

  Although not shown in FIG. 1, the sense latch circuit 120 includes a column switch circuit for selecting a bit line based on a selection signal from the column decoder 130.

  The chip control unit 200 receives an access control signal and a clock signal supplied from the control signal input terminal group 14 via the command buffer circuit 144 from the outside, and according to this, a flash memory is used for writing control and reading control of the memory cell. Includes a control circuit 210 for overall control of the internal circuit. Switching of the operating voltage of a word driver (not shown) for driving the potential of the word line according to the operation mode such as erasing, writing, and reading is performed by the control circuit 210 controlling the power supply generation unit 150. It is.

  Data latch circuits DL-L and DL-R are data buffers that temporarily hold data exchanged in data write and read operations.

  Further, as will be described later, the chip control unit 200 is controlled by the control circuit 210 to calculate data held in the data latch circuits DL-L and DL-R and the sense latch circuit 120 in the read operation, The read data conversion circuit 220 that generates read data and the control circuit 210 control the data held in the data latch circuits DL-L and DL-R and the sense latch circuit 120 in the write operation, and write data And a write data conversion circuit 230 for generating.

  The operation mode of the flash memory 1000 is not particularly limited, but is instructed by an access control signal supplied from the outside to the chip control unit 200 or command data supplied via a data bus or the like, and data rewriting (erasing and writing). And data read mode.

  Also in the AND type quaternary flash memory 1000 shown in FIG. 1, the information storage state of one memory cell is the erase state, the first write state, the second write state, or the third write state. One state selected from.

  For this purpose, the flash memory 1000 also sets three different write verify voltages to be applied to the word line during the write operation, and sequentially switches these to perform the write process in three steps. However, as will be described later, it is possible to shorten the writing time and the reading time by devising the arrangement of 2-bit data corresponding to the above four information storage states and the order of these three writing processes. To do.

  In each of these write operations, the control circuit 210 controls the write data conversion circuit 230, and in each write operation based on the write data held in the data latches DL-L and DL-R, The calculation of binary (1 bit) latch data “0” or “1” (“L” or “H”) to be held in the sense latch SL included in the sense latch circuit 120 is performed. The control circuit 210 controls the write operation by setting a corresponding write verify voltage for each of the write operations divided into the above three times.

  Here, in the configuration of the conventional flash memory 8000, the data latch circuits DL-L and DL-R each hold 2 divided data strings applied to the data input / output terminal group 10 at the same timing. There were two data columns.

  On the other hand, in the flash memory 1000 of the present application, unlike the configuration of the conventional flash memory 8000, the data latch circuits DL-L and DL-R are held at different timings as will be described later. Two sets of data columns applied to the same memory cell group applied to the data input / output terminal group 10 and coupled to the same word line, or memory cell groups coupled to the same word line but coupled to different bit lines Are two sets of data strings. With such a configuration, it is possible to write 4-level (2-bit) information in one memory cell.

  The flash memory 1000 also sets three types of voltages as word line selection levels to be applied to the word lines during a read operation, and sense latches binary (1 bit) data read from the memory cell in three read operations. The data is taken into the data latch circuits DL-L and DL-R via the circuit 120. The read data conversion circuit 220 sequentially converts the data held in these latch circuits into quaternary (2 bits) information during the three read operations, and the control circuit 210 outputs the data from the data input / output terminal group 10. .

Hereinafter, the write operation and the read operation described above will be described in more detail.
[Read operation of 4-level data]
As described above, flash memory 1000 according to the first embodiment is different from conventional flash memory 8000 in the method of storing data latches DL-L and DL-R of input / output data.

  The data stored in one memory cell is the data DQ0 and DQ4 and the data DQ1 and DQ5 among the 1-byte data input from the data input / output terminal group 10 at the same timing in the conventional multilevel flash memory 8000. As shown, it is composed of data in the same byte. In the quaternary flash memory 1000 of the present invention, the data stored in one memory cell is the same Y address of different word lines and corresponds to the same I / O bit, unlike the conventional binary flash memory. Or data corresponding to data of the same I / O where the Y address of the same sector (same word line) is somewhere different (data corresponding to the same I / O of a different Y address of the same sector) It is.

  2 to 7 are operation explanatory diagrams of the first embodiment of the present invention, and are held in data latches DL-L and DL-R and sense latch SL in the first to third processing steps of the read operation. It is a conceptual diagram which shows the threshold value and determination level of a memory cell at the time of data and reading.

  FIG. 2 shows data held in the respective latches in the first processing step of the read operation, and FIG. 3 shows threshold values and determination levels of the memory cells in the first processing step of the read operation.

  FIG. 4 shows data held in the respective latches in the second processing step of the read operation, and FIG. 5 shows threshold values and determination levels of the memory cells in the second processing step of the read operation.

  FIG. 6 shows data held in the respective latches in the third processing step of the read operation, and FIG. 7 shows threshold values and determination levels of the memory cells in the third processing step of the read operation.

  First, referring to FIG. 2 and FIG. 3, in the first processing step of the read operation, a plurality of memory cells connected to the same word line, for example, memory cells for 1 kByte, are subjected to the second determination level Vj2. Then, reading is performed at once and the result is stored in the sense latch circuit 120.

  In FIG. 2, in the sense latch circuit 120, a read latch for one sector, a sense latch SL that first holds one byte of data output from the data input / output terminal group 10, and a corresponding data latch DL-L and DL-R are extracted and shown. In the read operation for one sector, the same processing as described below is performed in parallel for the data read from the data input / output terminal group 10 following the data for one byte.

  Data “11”, “01”, “00”, and “10” are respectively stored in the memory cell columns MC0 to MC7 that hold a data column including data of 1 byte that is output first from the data input / output terminal group 10. ”,“ 01 ”,“ 00 ”,“ 10 ”, and“ 11 ”are held. Therefore, in FIG. 2, the data held in the 1-byte area of the sense latch circuit 120 is C9h in hexadecimal notation.

  Data read at a time at the second determination level Vj2 is stored in the data latch DL-L from the sense latch SL. At this time, the data stored in the data latch DL-L is sequentially output from the data input / output terminal group 10 byte by byte under the control of the control circuit 210. At this time, the data stored in the data latch circuit DL-L corresponds to half of the data for one sector in the read operation of the conventional binary flash memory.

  As described above, in the first processing step of the read operation, the read operation is first performed at the second determination level Vj2, as shown in FIG. This is because it is determined whether the data is “0” or “1”. That is, 0 or 1 of the upper bits of the data stored in the memory cells MC0 to MC7 is determined.

  4 and 5, in the second processing step of the read operation, data is stored from sense latch SL to data latch DL-L in the first processing step, and sense latch SL is cleared. At that time, a read operation is performed at the first determination level Vj1, and the read data is stored in the sense latch circuit 120. That is, data is transferred from the sense latch SL to the data latch DL-R while data is being output from the data latch circuit DL-L. After data transfer to the data latch DL-R, the sense latch circuit 120 is cleared.

  6 and FIG. 7, in the third processing step of the read operation, the read operation is performed at the third determination level Vj3 and data is stored in the sense latch circuit 120. The read data conversion circuit 220 performs an operation between the data held in the sense latch SL and the data held in the data latch DL-R, and only the bit data of “0” is the data latch DL-R. Is changed to “1”.

  After the data output of the data latch DL-L is completed, the control circuit 210 starts data output from the data latch DL-R to the data input / output terminal group 10.

  In the conventional quaternary flash memory 8000, the sector size is, for example, 2 KB, and the output operation is performed at 50 ns per 1 byte. Therefore, it takes 50 μs to output 1 KByte, which is half of the sector.

  Even in the conventional quaternary flash memory 8000, that is, when data output is started for the first time after performing the read operation three times, the time immediately before the output (referred to as first access time) is completed in 50 μs. In the quaternary flash memory 1000, the access operation from the first determination level to the third determination level can be completed while data for 1/2 sector is being output.

  Therefore, in the quaternary flash memory 1000, it suffices that the time until the determination result of the second determination level Vj2 is obtained after the read command is input until the data is output. This is equivalent to the binary read time, and means that the speed is not deteriorated due to the quaternary data stored in the memory cell.

  If the output of the data latch DL-L is finished before the output of the data latch DL-R is finalized before the output speed is very high (or the first access time is very long) and the data of the data latch DL-R is determined, the data latch DL-L And a waiting time occurs between data output from the data latch DL-R. However, even in this case, the reading speed is improved as compared with the conventional data reading operation by the output time of the data value DL-L.

  However, normally, the sector size is adjusted so that such a waiting time does not occur. That is, the sector size (the amount of data output from the memory cells connected to one word line) can be determined by the read time (first access time).

In order to satisfy these conditions, the sector size needs to satisfy the following equation. {Sector size (bytes) × (output time per byte) × 1/2} ≧ {one read time × 2} (1)
FIG. 8 is a timing chart for explaining the read operation of the flash memory 1000 according to the first embodiment.

  Referring to FIG. 8, at time t 1, first, a read operation at second determination level Vj 2 is performed and stored in sense latch circuit 120.

  Subsequently, at time t2, the data held in the sense latch circuit 120 is transferred to the data latch DL-L, and the sense latch circuit 120 is cleared.

  At time t3, a read operation based on the first determination level Vj1 is started. On the other hand, at time t4, under the control of the control circuit 210, output of data for 1/2 sector held in the data latch DL-L is started.

  At time t5, data read based on the first determination level Vj1 and held in the sense latch circuit 120 is stored in the data latch DL-R. On the other hand, the sense latch circuit 120 is cleared.

  At time t6, a read operation based on third determination level Vj3 is started, and read data is stored in sense latch circuit 120.

  After completion of the read operation based on the third determination level Vj3, at time t7, the read data conversion circuit 220 controls the data held in the sense latch circuit 120 and the data latch circuit DL-R under the control of the control circuit 210. The bit data held in the data latch DL-R is changed to “1” only for the bit data of “0”.

  At time t9, output of data for the remaining ½ sectors held in the data latch circuit DL-R is started. At time t10, data output for one sector is completed.

  As described above, the read operation of the data string to be output subsequent to this data string is completed during the period in which the data string read at time t1 is being output. It is possible to reduce the delay time when outputting read data from the memory cell.

[Variation 1 of Embodiment 1]
In the first embodiment, after the processing shown in FIGS. 2 and 3 is performed, the data held in the data latch DL-L is output, and the processing shown in FIGS. 4 and 5 and the processing shown in FIGS. It was the composition which performs the processing which is. However, the present invention is not necessarily limited to the order of such processing. For example, after performing the processing shown in FIGS. 4 and 5 and the processing shown in FIGS. Then, reading is performed at the first determination level Vj1, and the reading result is stored in the data latch DL-R. Subsequently, reading is performed at the third determination level Vj3, the data stored in the sense latch SL, and the data latch The processing shown in FIGS. 2 and 3 may be performed while the data output from the data latch DL-R is performed after the operation with the data stored in the DL-R. In this case, after the data output from the data latch DL-R is completed, the output of the data read at the second determination level and stored in the data data latch DL-L is started.

  Although the effect of shortening the read operation time is small as compared with the first embodiment, it is possible to read data in a shorter time than the conventional quaternary flash memory 8000.

  Of course, it is not always necessary to continuously perform the first to third reading processes as described above, and the data held in the memory cells MC0 to MC7 is read bit by bit, the upper bit or the lower bit one by one. It is also possible to do.

[Modification 2 of Embodiment 1]
As described above, in the first embodiment, in the first processing step of the read operation, the read operation is first performed at the second determination level Vj2, so that the four types of data in the memory cell are “0” or The write level is associated with the write data so as to determine which one is “1”.

  On the contrary, FIGS. 9 to 12 show examples of associating the write level with the write data so that neither the upper bit nor the lower bit can be determined in such a single read process. In each of the cases shown in FIGS. 9 to 12, even when the data array is replaced with “0” and “1”, both the upper bit and the lower bit are determined in one reading process. Can not.

  On the other hand, in the read operation of the second modification of the first embodiment, an example of another correspondence relationship between the write data and the write level that can reduce the read time is given as in the first embodiment.

  FIG. 13 shows data held in each latch in the second processing step of the read operation of the second modification of the first embodiment, and FIG. 14 shows the second read operation of the second modification of the first embodiment. The threshold value and determination level of the memory cell in the processing step are shown.

  That is, as shown in FIG. 14, in the data arrangement shown in FIG. 3, even in the data arrangement in which the data “00” and the data “01” are exchanged, the reading time is shortened by the same process as in the first embodiment. Is possible.

  In this case, first, in the first processing step of the reading operation, reading is performed collectively from the plurality of memory cells connected to the same word line at the second determination level Vj2, and the result is sense latch circuit 120. To store.

  Data “11”, “00”, “01”, “10” are respectively stored in the memory cell columns MC0 to MC7 that hold a data column including data of 1 byte output first from the data input / output terminal group 10. ”,“ 00 ”,“ 01 ”,“ 10 ”, and“ 11 ”are held. Therefore, the data held in the 1-byte area of the data latch circuit DL-L is C9h in hexadecimal notation.

  Data collectively read at the second determination level Vj2 is stored in both the data latches DL-L and DL-R from the sense latch SL. At this time, the data stored in the data latch DL-L is sequentially output from the data input / output terminal group 10 byte by byte under the control of the control circuit 210. At this time, the data stored in the data latch circuits DL-L and DL-R correspond to half of the data for one sector in the read operation of the conventional binary flash memory.

  As described above, also in the first processing step of the read operation of the second modification of the first embodiment, the read operation is first performed at the second determination level Vj2, whereby the upper bits of the four types of data in the memory cell are obtained. Is “0” or “1”.

  Referring to FIGS. 13 and 14, in the second processing step of the read operation, data is stored from sense latch SL to data latches DL-L and DL-R in the first processing step and sensed. When the latch SL is cleared, a read operation is performed at the first determination level Vj1, and the read data is stored in the sense latch circuit 120. While data output from data latch DL-L is being performed, read data conversion circuit 220 performs an operation between data held in sense latch SL and data held in data latch DL-R. When the bit data of the sense latch SL is “0” and the corresponding bit data of the data latch DL-R is “1”, the corresponding bit data of the data latch DL-R is “0”. In other cases, the bit data of the data latch DL-R is changed to “1”. After changing the data in the data latch DL-R, the sense latch circuit 120 is cleared.

  Next, in the third processing step of the read operation, the read operation is performed at the third determination level Vj3 and data is stored in the sense latch circuit 120. The read data conversion circuit 220 performs an operation between the data held in the sense latch SL and the data held in the data latch DL-R, and only the bit data of “0” is the data latch DL-R. Is changed to “1”.

  After the data output of the data latch DL-L is completed, the control circuit 210 starts data output from the data latch DL-R to the data input / output terminal group 10.

  FIG. 15 is a timing chart for explaining the read operation of the flash memory according to the second modification of the first embodiment.

  Referring to FIG. 15, at time t <b> 1, first, a read operation at second determination level Vj <b> 2 is performed and stored in sense latch circuit 120.

  Subsequently, at time t2, the data held in the sense latch circuit 120 is transferred to the data latches DL-L and DL-R, and the sense latch circuit 120 is cleared.

  At time t3, a read operation based on the first determination level Vj1 is started. On the other hand, at time t4, under the control of the control circuit 210, output of data for 1/2 sector held in the data latch DL-L is started.

  At time t5, read data conversion circuit 220 starts an operation between the data held in sense latch SL and the data held in data latch DL-R. From time t6, the bit data of sense latch SL is changed. When it is “0” and the corresponding bit data of the data latch DL-R is “1”, the corresponding bit data of the data latch DL-R is set to “0”, otherwise Changes the bit data of the data latch DL-R to “1”.

At time t7, the sense latch circuit 120 is cleared.
At time t8, a read operation based on the third determination level Vj3 is started, and read data is stored in the sense latch circuit 120.

  After completion of the read operation based on the third determination level Vj3, the read data conversion circuit 220 is controlled by the control circuit 210 at time t9, so that the read data conversion circuit 220 and the data latch circuit DL-R And the bit data held in the data latch DL-R is changed to “1” only at bit data of “0” from time t10.

  At time t11, data output for the remaining ½ sector held in the data latch circuit DL-R is started.

At time t12, data output for one sector is completed.
The above read operation can provide the same effect as the read operation of the first embodiment.

[Embodiment 2]
FIG. 16 is a diagram showing a concept of a switching method of connection between the sense latch circuit 120 and the bit line of the flash memory according to the second embodiment. FIG. 16A shows 1-bit data in the sense latch circuit 120. FIG. 16B shows the case where the bit line BL2 is connected to the sense latch SL. FIG. 16B shows the case where the bit line BL2 is connected to the sense latch SL.

  The configuration of the flash memory of the second embodiment is basically the same as the configuration of the flash memory 1000 of the first embodiment except for the configuration shown in FIG. 16 and the control operation of the control circuit 210.

  With the configuration as shown in FIG. 16, in the state where one word line WL is selected, the data fetch from the bit line to the sense latch circuit 120 is divided for adjacent memory cell columns. In this case, each time data is read from each memory cell column, the first to third processing steps can be divided and processed in parallel. As described below, the processing speed can be further increased. It becomes possible.

  FIG. 17 is a diagram showing a circuit configuration for specifically realizing the concept shown in FIG. In FIG. 17, the configuration relating to two of the sense latches corresponding to each bit data in the sense latch circuit 120 is extracted and shown as a representative.

  Referring to FIG. 17, for example, the drains of memory cell transistors MC1nm, MC2nm, MC1nm + 1, MC2nm + 1 having gates connected to one word line WLn are connected to sub-bit lines SBL1m, SBL2m, SBL1m + 1, SBL2m + 1, respectively. The memory cell transistor is a so-called floating gate transistor having a control gate and a floating gate.

  The sub bit lines SBL1m and SBL2m are connected to the main bit line MBLm via transistors Tr1m and Tr2m, respectively. The gate of the transistor Tr1m is controlled by the signal BSS1, and the gate of the transistor Tr2m is controlled by the signal BSS2.

  The sub bit lines SBL1m + 1 and SBL2m + 1 are connected to the main bit line MBLm + 1 via transistors Tr1m + 1 and Tr2m + 1, respectively. The gate of the transistor Tr1m + 1 is controlled by the signal BSS1, and the gate of the transistor Tr2m + 1 is controlled by the signal BSS2.

  Main bit line MBLm is connected to latch circuit SLm corresponding to 1-bit data in sense latch circuit 120 via gate transistor TGm whose gate potential is controlled by signal STG. The main bit line MBLm + 1 is connected to a latch circuit SLm + 1 corresponding to other 1-bit data in the sense latch circuit 120 via a gate transistor TGm + 1 whose gate potential is controlled by a signal STG.

  The number of sub-bit lines connected to one main bit line is not limited to two as shown in FIG. 17, and may be larger.

  18 to 29 are operation explanatory views of the second embodiment of the present invention, and are held in data latches DL-L and DL-R and sense latch SL in the first to sixth processing steps of the read operation. It is a conceptual diagram which shows the threshold value and determination level of a memory cell at the time of data and reading.

  FIG. 18 shows data held in the respective latches in the first processing step of the read operation, and FIG. 19 shows threshold values and determination levels of the memory cells in the first processing step of the read operation.

  FIG. 20 shows data held in the respective latches in the second processing step of the read operation, and FIG. 21 shows thresholds and determination levels of the memory cells in the second processing step of the read operation.

  FIG. 22 shows data held in each latch in the third processing step of the read operation, and FIG. 23 shows memory cell threshold values and determination levels in the third processing step of the read operation.

  FIG. 24 shows data held in the respective latches in the fourth processing step of the read operation, and FIG. 25 shows thresholds and determination levels of the memory cells in the fourth processing step of the read operation.

  FIG. 26 shows data held in the respective latches in the fifth processing step of the read operation, and FIG. 27 shows thresholds and determination levels of the memory cells in the fifth processing step of the read operation.

  FIG. 28 shows data held in the respective latches in the sixth processing step of the read operation, and FIG. 29 shows thresholds and determination levels of the memory cells in the sixth processing step of the read operation.

  First, referring to FIG. 18 and FIG. 19, in the first processing step of the read operation, the second determination level Vj2 is obtained from a plurality of memory cells connected to the same word line, for example, 1 kByte memory cells. Then, reading is performed at once and the result is stored in the sense latch circuit 120.

  In FIG. 18, in the sense latch circuit 120, in a read operation for one sector, a sense latch SL that first holds data for one byte that is output from the data input / output terminal group 10, and a corresponding data latch DL-L and DL-R are extracted and shown. In the read operation for one sector, the same processing as described below is performed in parallel for the data read from the data input / output terminal group 10 following the data for one byte.

  Memory connected to the sub bit lines SBL1m, SBL1m + 1, etc. selected by the signal BSS1 among the sub bit lines in FIG. 17 and holding a data string including data of 1 byte output first from the data input / output terminal group 10 It is assumed that data “11”, “01”, “00”, “10”, “01”, “00”, “10”, “11” are held in the cell columns MC1n0 to MC1n7, respectively. Accordingly, in FIG. 18, the data held in the 1-byte area of the sense latch circuit 120 is C9h in hexadecimal notation.

  Data read at a time at the second determination level Vj2 is stored in the data latch DL-L from the sense latch SL. At this time, the data stored in the data latch DL-L is sequentially output from the data input / output terminal group 10 byte by byte under the control of the control circuit 210. At this time, the data stored in the data latch circuit DL-L corresponds to ¼ of the data for one sector in the read operation of the conventional binary flash memory.

  As described above, in the first processing step of the read operation, the read operation is first performed at the second determination level Vj2. By reading at this level, as shown in FIG. This is because it is determined whether the data is “0” or “1”. That is, 0 or 1 of the upper bits of the data stored in the memory cells MC1n0 to MC1n7 is determined.

  Next, referring to FIGS. 20 and 21, in the second processing step of the read operation, data is stored from sense latch SL to data latch DL-L in the first processing step, and sense latch SL is cleared. At that time, at the second determination level Vj2, the read operation is performed from the memory cell columns MC2n0 to MC2n7 connected to the sub bit lines SBL2m, SBL2m + 1, etc. selected by the signal BSS2 among the sub bit lines in FIG. The stored data is stored in the sense latch circuit 120.

  It is assumed that data “11”, “01”, “00”, “10”, “01”, “00”, “10”, “11” are also held in the memory cell columns MC2n0 to MC2n7, respectively. . Therefore, in FIG. 20, the data held in the 1-byte area of the sense latch circuit 120 is also C9h in hexadecimal notation.

  That is, data is transferred from the sense latch SL to the data latch DL-R while data is being output from the data latch circuit DL-L. Subsequent to data output from the data latch DL-L, data output from the data latch DL-R is performed.

  Similar processing is performed in parallel for memory cells connected to the same word line and other than the memory cell columns MC2n0 to MC2n7 and connected to the sub-bit line selected by the signal BSS2 among the sub-bit lines in FIG. It is done.

  Next, referring to FIGS. 22 and 23, in the third processing step of the read operation, data is stored from sense latch SL to data latch DL-L in the second processing step, and sense latch SL is cleared. At that time, a read operation is performed at the first determination level Vj1, and the read data is stored in the sense latch circuit 120.

  Subsequently, data is transferred from the sense latch SL to the data latch DL-L while data is being output from the data latch circuit DL-R. After the data transfer to the data latch DL-L, the sense latch circuit 120 is cleared.

  Next, referring to FIG. 24 and FIG. 25, in the fourth processing step of the read operation, the read operation is performed from memory cells MC1n0 to MC1n7 at the third determination level Vj3, and data is transferred to the sense latch circuit 120. Store.

  The read data conversion circuit 220 performs an operation between the data held in the sense latch SL and the data held in the data latch DL-L, and only the bit data of “0” is the data latch DL-L. Is changed to “1”. At this time, data is being output from the data latch DL-R.

  After the data output from the data latch DL-R is completed, the control circuit 210 starts data output from the data latch DL-L to the data input / output terminal group 10.

  Next, referring to FIGS. 26 and 27, in the fifth processing step of the read operation, data is stored from sense latch SL to data latch DL-L in the fourth processing step, and sense latch SL is cleared. At this point, the read operation is performed from the memory cells MC2n0 to MC2n7 at the first determination level Vj1, and the read data is stored in the sense latch circuit 120.

  Subsequently, data is transferred from the sense latch SL to the data latch DL-R while data is being output from the data latch circuit DL-L. After data transfer to the data latch DL-R, the sense latch circuit 120 is cleared.

  Next, referring to FIGS. 28 and 29, in the sixth processing step of the read operation, the read operation is performed from memory cells MC2n0 to MC2n7 at third determination level Vj3, and data is transferred to sense latch circuit 120. Store.

  The read data conversion circuit 220 performs an operation between the data held in the sense latch SL and the data held in the data latch DL-R, and only the bit data of “0” is the data latch DL-R. Is changed to “1”. At this time, data is being output from the data latch DL-L.

  After the data output from the data latch DL-L is completed, the control circuit 210 starts data output from the data latch DL-R to the data input / output terminal group 10.

  Therefore, in quaternary flash memory 1000 of the second embodiment, the determination of second determination level Vj2 is performed on the data for 1/4 sector until the data is output after the read command is input. It suffices to pass the time until the result is obtained. Therefore, the reading time can be further reduced as compared with the case of the first embodiment.

  FIG. 30 is a timing chart for explaining the read operation of the flash memory according to the second embodiment.

  Referring to FIG. 30, at time t1, a read operation from memory cells MC1n0 to MC1n7 etc. is first performed at second determination level Vj2, and stored in sense latch circuit 120.

  Subsequently, at time t2, the data held in the sense latch circuit 120 is transferred to the data latch DL-L, and the sense latch circuit 120 is cleared.

  At time t3, the read operation from the memory cells MC2n0 to MC2n7 and the like is started at the second determination level Vj2, and the read data is stored in the sense latch circuit 120.

Subsequently, at time t4, data output from the data latch DL-L is started.
At time t5, read data at the second determination level Vj2 from the memory cells MC2n0 to MC2n7 and the like is stored in the data latch DL-R.

  At time t6, the read operation is started from the memory cells MC1n0 to MC1n7 based on the first determination level Vj1. On the other hand, at time t7, under the control of the control circuit 210, output of read data from the memory cells MC2n0 to MC2n7 and the like for 1/4 sector held in the data latch DL-R is started.

  At time t8, data read based on the first determination level Vj1 and held in the sense latch circuit 120 is stored in the data latch DL-L. On the other hand, the sense latch circuit 120 is cleared.

  At time t9, based on the third determination level Vj3, the read operation is started from the memory cells MC1n0 to MC1n7 and the like, and the read data is stored in the sense latch circuit 120.

  Based on the read data based on the third determination level Vj3 from the memory cells MC1n0 to MC1n7, etc., the read data conversion circuit 220 is controlled by the control circuit 210 at time t10, and the read data conversion circuit 220 holds the data held in the sense latch circuit 120. And the data held in the data latch circuit DL-L, and the bit data held in the data latch DL-L is changed to “1” only for the bit data of “0”. .

  On the other hand, at time t11, based on the first determination level Vj1, the read operation is started from the memory cells MC2n0 to MC2n7. On the other hand, at time t12, under the control of the control circuit 210, output of read data from the memory cells MC1n0 to MC1n7 and the like for ¼ sectors held in the data latch DL-L is started.

  At time t13, data read based on the first determination level Vj1 and held in the sense latch circuit 120 is stored in the data latch DL-R. On the other hand, the sense latch circuit 120 is cleared.

  At time t14, based on the third determination level Vj3, the read operation is started from the memory cells MC2n0 to MC2n7 and the like, and the read data is stored in the sense latch circuit 120.

  Based on the read data based on the third determination level Vj3 from the memory cells MC2n0 to MC2n7, etc., the read data conversion circuit 220 is controlled by the control circuit 210 at time t15, and the read data conversion circuit 220 holds the data held in the sense latch circuit 120. And the data held in the data latch circuit DL-R, and the bit data held in the data latch DL-R is changed to “1” only for the bit data of “0”. .

  At time t16, output of data for 1/4 sector held in the data latch circuit DL-R is started. At time t17, data output for one sector is completed.

  As described above, during the period in which the data string read at times t1 and t3 is being output, the read operation of the data string to be output subsequent to this data string is completed. It is possible to reduce the delay time when outputting read data from the quaternary memory cell.

[Embodiment 3]
Next, an example of a data write operation in the configuration of the flash memory 1000 of the first embodiment will be described as a third embodiment.

  FIGS. 31 to 36 are diagrams for explaining the operation of the third embodiment of the present invention. In the first to third processing steps of the write operation, they are held in the data latches DL-L and DL-R and the sense latch SL. FIG. 6 is a conceptual diagram showing data and threshold values and determination levels of memory cells at the time of writing.

  FIG. 31 shows data held in the respective latches in the first processing step of the write operation, and FIG. 32 shows threshold values and determination levels of the memory cells in the first processing step of the write operation.

  FIG. 33 shows data held in the respective latches in the second processing step of the write operation, and FIG. 34 shows thresholds and determination levels of the memory cells in the second processing step of the write operation.

  FIG. 35 shows data held in the respective latches in the third processing step of the write operation, and FIG. 36 shows thresholds and determination levels of the memory cells in the third processing step of the write operation.

  First, for the memory cell block in which the write operation is performed, the threshold value corresponding to the data “11” is set for all the memory cells.

  Next, referring to FIGS. 31 and 32, in the first processing step of the write operation, the input data (1/2 sector: C9h in hexadecimal representation) is stored in data latch DL-L. Then, the data is transferred to the sense latch SL. Based on the second determination level Vj2, writing up to a threshold value corresponding to level 3 is performed. During the write operation at the second determination level Vj2, the remaining 1/2 sector data (93h in hexadecimal notation) is stored in the data latch DL-R.

  Next, referring to FIGS. 33 and 34, in the second processing step of the write operation, write data conversion circuit 230 responds to the data included in data latches DL-R and DL-L. By calculating the bit data set, the bit held in the data latch DL-L is “0”, and the bit held in the data latch DL-R is “1”. Only the bit data of the sense latch SL is set to “0” level.

  As shown in FIG. 33, after such an operation is performed, data “10110111” is held in the sense latch SL. Based on the data held in the sense latch SL in this way, data is written into the memory cells MC0 to MC7 corresponding to the respective bits of the sense latch SL. Here, the memory cells MC0 to MC7 are connected to the same word line WL. Further, the third determination value Vj3 is used as the determination value for the verify operation.

  At this time, data is written to the memory cell corresponding to data “0” in the sense latch. Therefore, level 4 data (corresponding to data “01”) is written into memory cells MC1 and MC4 corresponding to the first bit and the fourth bit of the sense latch.

  Data is written using a FN (Fowler-Nordheim) tunnel current by applying a high voltage to the word line WL.

  A voltage equal to or lower than the word line voltage is applied to the bit line BL corresponding to the bit whose bit data of the sense latch SL is “1” in order to relax the voltage applied from the word line WL. As a result, data is written only to the memory cells connected to the bit line BL corresponding to the bit data held in the sense latch of “0”.

  Next, referring to FIGS. 35 and 36, in the third step of the write operation, write data conversion circuit 230 performs an operation on the data held in data latches DL-R and DL-L, and data latch DL The bit data held in −L is “1” and the bit of the sense latch SL corresponding to the data set in which the bit data held in the data latch DL-R is “0” is written “0”. Is included. After the determination value in the verify operation is changed to the first determination level Vj1, data is written only in the memory cells MC3 and MC6.

  As is apparent from the above description, in the writing of FIG. 31 and FIG. 32, the data is once written at level 3 even for the memory cell to which data should be originally written as level 4. In FIG. 33 and FIG. 34, all the memory cells that are written as level 4 are included in the memory cells that are written as level 3 in FIG. 31 and FIG.

  Similarly, in FIG. 35 and FIG. 36, the memory cell to which writing as level 2 is performed is included in the memory cell having the threshold value of level 1 until just before that.

  That is, at the time of writing in FIG. 31 and FIG. 32, the memory cells to which level 4 and 3 are written are separated from the memory cells to which the memories 2 and 1 are written.

  Therefore, in the quaternary flash memory according to the third embodiment, after the write command is input, the write operation is already started during the data input time of 1/2 sector to the data latch DL-R. Can be shortened.

In particular, when the condition of the following expression (2) is satisfied, the effect of shortening is large. {Sector size (Byte) × (Input time per 1 byte) × 1/2} ≧ {Level 3 write time} (2)
FIG. 37 is a timing chart for explaining the write operation of the flash memory 1000 according to the third embodiment.

  Referring to FIG. 37, at time t1, first, input of data for 1/2 sector (upper bit data) is started, and storage into data latch DL-L starts from time t2.

  When the input of data for the first half of the sector is completed at time t3, the data stored in the data latch DL-L is transferred to the sense latch SL.

  On the other hand, input of 1/2 sector data (lower bit data) is started at time t3, and storage into the data latch DL-R starts from time t4.

  At time t5, a write operation is performed in accordance with second determination level Vj2 based on the data stored in sense latch SL.

  When the write operation at the second determination level is completed at time t6, the sense latch SL is cleared.

  At time t7, the write data conversion circuit 230 starts an operation on the corresponding bit data set for the data included in the data latches DL-R and DL-L, and is held in the data latch DL-L from time t8. Only the bit data of the sense latch SL corresponding to the data whose bit is “0” and the bit held in the data latch DL-R is “1” is set to the “0” level.

  At time t9, a write operation is performed according to the third determination level Vj3 based on the data stored in the sense latch SL.

  When the write operation at the third determination level is completed at time t10, the sense latch SL is cleared.

  At time t11, the write data conversion circuit 230 starts calculating the data held in the data latches DL-R and DL-L, and the bit data held in the data latch DL-L is “1” from time t12. Then, “0” is written to the bit of the sense latch SL corresponding to the data set in which the bit data held in the data latch DL-R is “0”.

  At time t13, a write operation is performed in accordance with the first determination level Vj1 based on the data stored in the sense latch SL.

  As described above, since the operation of storing the data string to be written following this data string is completed during the period in which the data string input at time t1 is being written, the quaternary memory It is possible to reduce the delay time when writing data to the cell.

[Modification of Embodiment 3]
In the write operation of the third embodiment, the write time can be shortened. On the other hand, it is possible to reduce the number of data latches used in the write operation.

  38 and 39 are diagrams for explaining the operation of the modification of the third embodiment of the present invention. In the second processing step of the write operation, the data latches DL-L and DL-R and the sense latch SL hold the data. It is a conceptual diagram which shows the threshold value and determination level of a memory cell at the time of data and reading.

  FIG. 38 shows data held in the respective latches in the second processing step of the write operation, and FIG. 39 shows threshold values and determination levels of the memory cells in the read operation in the second processing step of the write operation. Indicates.

  First, as in FIGS. 31 and 32, data is written into the memory cell in the first processing step of the write operation.

  Subsequently, in the second processing step of the write operation, the remaining 1/2 sector data is again taken into the data latch DL-L. On the other hand, at the second determination level Vj2, the data written in the memory cell in the first processing step is read and stored in the sense latch SL. The write data conversion circuit 230 performs the same operation as in FIGS. 33 and 34 between the data held in the data latch DL-L and the data held in the sense latch SL, and the contents of the sense latch SL Rewrite. Based on the data of the sense latch SL, a write operation corresponding to the third determination level Vj3 is executed.

  Subsequently, similarly, the data written in the memory cell at the second determination level Vj2 is read again and stored in the sense latch SL. Write data conversion circuit 230 performs the same operation as in FIGS. 35 and 36 between the data held in data latch DL-L and the data held in sense latch SL, and the contents of sense latch SL Rewrite. Based on the data of the sense latch SL, a write operation corresponding to the first determination level Vj1 is executed.

  With the above operation, the number of data latches required for data writing can be reduced.

[Embodiment 4]
In the write operation of the fourth embodiment, in order to further reduce the time required for the write operation of the third embodiment, the write operation at the determination value level Vj3 described in FIGS. 35 and a writing process capable of simultaneously performing the writing at the judgment value level Vj1 described with reference to FIG.

  In the writing process of the third embodiment, writing to threshold level 4 at judgment value level Vj3, writing to threshold level 3 at judgment value level Vj2, threshold level 2 at judgment value level Vj1 In the write process to the memory cell, as shown in Table 1, a write inhibition voltage is applied to the drain of the memory cell where data is not written.

  FIGS. 40 and 41 are diagrams for explaining the operation of the fourth embodiment of the present invention. In the second processing step of the write operation, the data latches DL-L and DL-R and the data held in the sense latch SL and It is a conceptual diagram which shows the threshold value and determination level of a memory cell at the time of writing.

  FIG. 40 shows data held in the respective latches in the second processing step of the write operation, and FIG. 41 shows threshold values and determination levels of the memory cells in the write operation in the second processing step of the write operation. Indicates.

  First, as in FIGS. 31 and 32, data is written to the memory cell based on the second determination level Vj2 in the first processing step of the write operation.

  Subsequently, in the second processing step of the write operation, the remaining ½ sector data is taken into the data latch DL-R. The write data conversion circuit 230 calculates the bit data held in the data latch DL-L and the data latch by calculating the corresponding bit data set for the data included in the data latches DL-R and DL-L. Only when the bit data held in DL-R is different, the bit data of the corresponding sense latch SL is set to the “0” level. This corresponds to inversion processing of the exclusive OR operation result of each bit data held in the data latches DL-R and DL-L.

  Based on the value of the sense latch SL rewritten in this manner, data is written into the memory cell so as to satisfy the conditions in Table 2 below. That is, for the memory cell to which data is written, the drain voltage is changed as shown in Table 2 depending on whether the data to be written is “01” or “10”.

  In Table 2, the relationship of voltage V1 <voltage V2 <voltage V3 is established. When the set values of the threshold voltages of the memory cell transistors are different, the voltages V1, V2, and V3 may be changed while maintaining this relationship.

  With the operation as described above, it is possible to further reduce the time required for data writing.

[Embodiment 5]
In the above description, the data read and write operations have been described when the data held in one memory cell is 2 bits, that is, 4 values.

More generally, when n ≧ m + 1, m ≧ 0, and n and m are natural numbers, if the data held in one memory cell is a 2 ⁿ value, the memory cell transistor corresponding to the write data and the write data When there is a fixed relationship with the threshold level of 1 bit, 1 bit out of n bits is read out at the second ^n-1 decision level among the n bit data held in each memory cell. A bit (eg, the most significant bit) can be determined.

Furthermore, one bit out of n bits can be determined by reading processing at the second ⁿ⁻² determination level and the (2 ⁿ⁻¹ +2 ⁿ⁻² ) determination level.

Moreover, (the sigma, the sum of Y from Y = 0 to Y = m: m ≧ 0, n ≧ m + 1) first ^{Σ (2 n-1-m} + Y) determination level 2 ^m pieces of determination levels or the like By the reading process in step 1, one bit out of n bits can be determined.

Finally, one more bit of n bits is determined by the reading process at the first determination level, the third determination level, the fifth determination level,..., The second ⁿ⁻¹ determination level. Can be.

  FIG. 42 shows the write data and the threshold value of the memory cell transistor corresponding to the write data when data can be read as described above when 3-bit, that is, 8-level data is written in one memory cell. It is a figure which shows matching with a level.

  The most significant bit is determined by reading at the fourth determination level, the middle bit is determined by reading at the second and sixth determination levels, and at the reading at the first, third, fifth, and seventh determination levels. The least significant bit is fixed.

  On the other hand, in FIG. 43, when 3-bit, that is, 8-level data is written to one memory cell, the write data and the memory cell transistor corresponding to the write data corresponding to the write data cannot be read as described above. It is a figure which shows matching with the level of a threshold value.

  Although the most significant bit is determined by reading at the fourth determination level, the middle bit is not determined by reading at the second and sixth determination levels.

[Reading operation of 16-value data]
In the following, the read operation will be described by taking the case of 16 (= 2 ⁿ : n = 4) as an example. As will be described below, the data latch circuit is changed from the two systems DL-L and DL-R to the four systems DL-1 to DL-4, and the operation of the control circuit 210 is different except for the operation of the control circuit 210. The configuration of the flash memory is the same as that of the flash memory 1000 of the first embodiment.

  44 to 81 are explanatory diagrams of the operation of the fifth embodiment of the present invention, and are held in the data latches DL-1 to DL-4 and the sense latch SL in the first to nineteenth processing steps of the read operation. It is a conceptual diagram which shows the threshold value and determination level of a memory cell at the time of data and reading.

  FIG. 44 shows data held in the respective latches in the first processing step of the read operation, and FIG. 45 shows threshold values and determination levels of the memory cells in the first processing step of the read operation.

First, referring to FIG. 44 and FIG. 45, in the first processing step of the read operation, from the plurality of memory cells connected to the same word line, for example, memory cells for 1 kByte, the eighth (= 2 ^{n -1} : n = 4), the data is read collectively at the determination level Vj8, and the result is stored in the sense latch circuit 120.

  In FIG. 44, in the sense latch circuit 120, in the read operation for one sector, the sense latch SL that first holds the data for 2 bytes that is output from the data input / output terminal group 10, and the corresponding data latch DL-1 to DL-4 are extracted and shown. In the reading operation for one sector, the same processing as described below is performed in parallel for the data read from the data input / output terminal group 10 following the data for 2 bytes.

  Data “0111”, “0110”, “0100”, “0101” are respectively stored in the memory cell columns MC0 to MC15 holding the data column including data of 1 byte output first from the data input / output terminal group 10. ”,“ 0001 ”,“ 0000 ”,“ 0010 ”,“ 0011 ”,“ 1011 ”,“ 1010 ”,“ 1000 ”,“ 1001 ”,“ 1101 ”,“ 1100 ”,“ 1110 ”,“ 1111 ” It shall be retained.

  As shown in FIG. 45, the write data corresponding to the levels from the higher level 16 of the memory cell to the lower level 1 are “0111”, “0110”, “0100”, “0101”, respectively. ”,“ 0001 ”,“ 0000 ”,“ 0010 ”,“ 0011 ”,“ 1011 ”,“ 1010 ”,“ 1000 ”,“ 1001 ”,“ 1101 ”,“ 1100 ”,“ 1110 ”,“ 1111 ” It shall be.

  Therefore, in FIG. 44, the data held in the 2-byte area of the sense latch circuit 120 is expressed in hexadecimal and is 00h and FFh.

  Data collectively read at the eighth determination level Vj8 is stored in the data latch DL-1 from the sense latch SL. At this time, under the control of the control circuit 210, the data stored in the data latch DL-1 is sequentially output from the data input / output terminal group 10 byte by byte (or byte by byte).

  As described above, in the first processing step of the read operation, the read operation is first performed at the eighth determination level Vj2 by reading at this level as shown in FIG. This is because it is determined whether the data is “0” or “1”. That is, 0 or 1 of the most significant bit of data stored in the memory cells MC0 to MC15 is determined.

  FIG. 46 shows data held in the respective latches in the second processing step of the read operation, and FIG. 47 shows threshold values and determination levels of the memory cells in the second processing step of the read operation.

46 and 47, in the second processing step of the read operation, data is stored from sense latch SL to data latch DL-1 in the first processing step, and sense latch SL is cleared. At that time, a read operation is performed at the fourth (= 2 ⁿ⁻² : n = 4) determination level Vj 4, and the read data is stored in the sense latch circuit 120. In other words, data is transferred from the sense latch SL to the data latch DL-2 while data is being output from the data latch circuit DL-1. After data transfer to the data latch DL-2, the sense latch circuit 120 is cleared.

  FIG. 48 shows data held in the respective latches in the third processing step of the read operation, and FIG. 49 shows thresholds and determination levels of the memory cells in the third processing step of the read operation.

Next, with reference to FIGS. 48 and 49, in the third processing step of the read operation, the read operation is performed at the twelfth (= 2 ⁿ⁻¹ +2 ⁿ⁻² : n = 4) determination level Vj12. The data is stored in the sense latch circuit 120. Read data conversion circuit 220 converts the data bit in data latch DL2 according to the result of the NOR operation between the inverted data of data held in sense latch SL and the data held in data latch DL-2. change.

  FIG. 50 shows data held in the respective latches in the fourth processing step of the read operation, and FIG. 51 shows threshold values and determination levels of the memory cells in the fourth processing step of the read operation.

50 and 51, in the fourth processing step of the read operation, data is stored from sense latch SL to data latch DL-1 in the third processing step, and sense latch SL is cleared. At that time, the read operation is performed at the second (= 2 ⁿ⁻³ : n = 4) determination level Vj 2, and the read data is stored in the sense latch circuit 120. Data is output from the data latch circuit DL-1, and after the output, data is transferred from the sense latch SL to the data latch DL-3 while data is output from the data latch circuit DL-2. After data transfer to the data latch DL-3, the sense latch circuit 120 is cleared.

  52 shows data held in the respective latches in the fifth processing step of the read operation, and FIG. 53 shows threshold values and determination levels of the memory cells in the fifth processing step of the read operation.

52 and 53, in the fifth processing step of the read operation, the read operation is performed at the sixth (= 2 ⁿ⁻² +2 ⁿ⁻³ : n = 4) determination level Vj6. The data is stored in the sense latch circuit 120. Read data conversion circuit 220 converts the data bit in data latch DL3 according to the result of the NOR operation between the inverted data of data held in sense latch SL and the data held in data latch DL-3. change.

  FIG. 54 shows data held in the respective latches in the sixth processing step of the read operation, and FIG. 55 shows thresholds and determination levels of the memory cells in the sixth processing step of the read operation.

Next, referring to FIGS. 54 and 55, in the sixth processing step of the read operation, data is stored from sense latch SL to data latch DL-3 in the fifth processing step, and sense latch SL is cleared. At that time, a read operation is performed at the 10th (= 2 ⁿ⁻¹ +2 ⁿ⁻³ : n = 4) determination level Vj 10, and the read data is stored in the sense latch circuit 120. Data is output from the data latch circuit DL-1, and after the output, data is transferred from the sense latch SL to the data latch DL-4 while data is output from the data latch circuit DL-2. After data transfer to the data latch DL-4, the sense latch circuit 120 is cleared.

  56 shows data held in the respective latches in the seventh processing step of the read operation, and FIG. 57 shows threshold values and determination levels of the memory cells in the seventh processing step of the read operation.

Next, referring to FIG. 56 and FIG. 57, in the seventh processing step of the read operation, at the fourteenth (= 2 ⁿ⁻¹ +2 ⁿ⁻² +2 ⁿ⁻³ : n = 4) determination level Vj14. A read operation is performed, and data is stored in sense latch circuit 120. Read data conversion circuit 220 converts the data bit in data latch DL4 according to the result of the NOR operation between the inverted data of data held in sense latch SL and the data held in data latch DL-4. change.

  58 shows data held in the respective latches in the eighth processing step of the read operation, and FIG. 59 shows threshold values and determination levels of the memory cells in the eighth processing step of the read operation.

  Next, with reference to FIGS. 58 and 59, read data conversion circuit 220 performs an OR operation between the bit data held in data latches DL-3 and DL-4, and outputs the result as data latch circuit DL-3. To store.

  FIG. 60 shows data held in the respective latches in the ninth processing step of the read operation, and FIG. 61 shows thresholds and determination levels of the memory cells in the ninth processing step of the read operation.

Next, referring to FIGS. 60 and 61, during the data output from data latch DL-2, the read operation is performed at the first (= 2 ⁿ⁻⁴ : n = 4) determination level Vj1, and the sense latch Data is stored in the circuit 120. Data in the sense latch SL is transferred to the data latch DL-4. The read data conversion circuit 220 outputs the inverted data of the data held in the data latch DL-3 to the data input / output terminal after the data output from the data latch DL-2 is completed.

  FIG. 62 shows data held in the respective latches in the tenth processing step of the read operation, and FIG. 63 shows threshold values and determination levels of the memory cells in the tenth processing step of the read operation.

Next, with reference to FIGS. 62 and 63, in the tenth processing step of the read operation, the read operation is performed at the third (= 2 ⁿ⁻³ +2 ⁿ⁻⁴ : n = 4) determination level Vj3. The data is stored in the sense latch circuit 120. Read data conversion circuit 220 converts the data bit in data latch DL4 according to the result of the NOR operation between the inverted data of data held in sense latch SL and the data held in data latch DL-4. change.

  FIG. 64 shows data held in the respective latches in the eleventh processing step of the read operation, and FIG. 65 shows threshold values and determination levels of the memory cells in the eleventh processing step of the read operation.

Next, referring to FIGS. 64 and 65, the read operation is performed at the fifth (= 2 ⁿ⁻² +2 ⁿ⁻⁴ : n = 4) determination level Vj5 during the data output from the data latch DL-2. The data is stored in the sense latch circuit 120. Data in the sense latch SL is transferred to the data latch DL-1.

  FIG. 66 shows data held in the respective latches in the twelfth processing step of the read operation, and FIG. 67 shows memory cell threshold values and determination levels in the twelfth processing step of the read operation.

Next, referring to FIGS. 66 and 67, in the twelfth processing step of the read operation, at the seventh (= 2 ⁿ⁻² +2 ⁿ⁻³ +2 ⁿ⁻⁴ : n = 4) determination level Vj7 A read operation is performed, and data is stored in sense latch circuit 120. Read data conversion circuit 220 converts the data bit in data latch DL1 according to the result of the NOR operation between the inverted data of data held in sense latch SL and the data held in data latch DL-1. change.

  68 shows data held in the respective latches in the thirteenth processing step of the read operation, and FIG. 69 shows memory cell threshold values and determination levels in the thirteenth processing step of the read operation.

  68 and 69, read data conversion circuit 220 performs an OR operation between the bit data held in data latches DL-1 and DL-4, and outputs the result as data latch circuit DL-4. To store.

  FIG. 70 shows data held in the respective latches in the fourteenth processing step of the read operation, and FIG. 71 shows thresholds and determination levels of the memory cells in the fourteenth processing step of the read operation.

Next, referring to FIG. 70 and FIG. 71, the data is read at the ninth (= 2 ⁿ⁻¹ +2 ⁿ⁻⁴ : n = 4) determination level Vj9 during the data output from the data latch DL-2 or DL3. The operation is performed and data is stored in the sense latch circuit 120. Data in the sense latch SL is transferred to the data latch DL-1.

  72 shows data held in the respective latches in the fifteenth processing step of the read operation, and FIG. 73 shows thresholds and determination levels of the memory cells in the fifteenth processing step of the read operation.

Next, referring to FIG. 72 and FIG. 73, in the fifteenth processing step of the read operation, at the eleventh (= 2 ⁿ⁻¹ +2 ⁿ⁻³ +2 ⁿ⁻⁴ : n = 4) determination level Vj11 A read operation is performed, and data is stored in sense latch circuit 120. Read data conversion circuit 220 converts the data bit in data latch DL1 according to the result of the NOR operation between the inverted data of data held in sense latch SL and the data held in data latch DL-1. change.

  74 shows data held in the respective latches in the sixteenth processing step of the read operation, and FIG. 75 shows thresholds and determination levels of the memory cells in the sixteenth processing step of the read operation.

  74 and 75, read data conversion circuit 220 performs an OR operation between the bit data held in data latches DL-1 and DL-4, and outputs the result as data latch circuit DL-4. To store.

  FIG. 76 shows data held in the respective latches in the seventeenth processing step of the read operation, and FIG. 77 shows thresholds and determination levels of the memory cells in the seventeenth processing step of the read operation.

Next, referring to FIG. 76 and FIG. 77, the thirteenth (= 2 ⁿ⁻¹ +2 ⁿ⁻² +2 ⁿ⁻⁴ : n = 4) determination during data output from the data latch DL-2 or DL3 Read operation is performed at level Vj13, and data is stored in sense latch circuit 120. Data in the sense latch SL is transferred to the data latch DL-1.

  78 shows data held in the respective latches in the eighteenth processing step of the read operation, and FIG. 79 shows thresholds and determination levels of the memory cells in the eighteenth processing step of the read operation.

78 and 79, in the eighteenth processing step of the read operation, the fifteenth (= 2 ^n-1 +2 ^n-2 +2 ^n-3 +2 ^n-4 : n = 4) Read operation is performed at determination level Vj15, and data is stored in sense latch circuit 120. Read data conversion circuit 220 converts the data bit in data latch DL1 according to the result of the NOR operation between the inverted data of data held in sense latch SL and the data held in data latch DL-1. change.

  FIG. 80 shows data held in the respective latches in the nineteenth processing step of the read operation, and FIG. 81 shows thresholds and determination levels of the memory cells in the nineteenth processing step of the read operation.

  Next, with reference to FIGS. 80 and 81, read data conversion circuit 220 performs an OR operation between the bit data held in data latches DL-1 and DL-4, and outputs the result as data latch circuit DL-4. To store.

  After the data output of the data latch DL-3 is completed, the control circuit 210 starts outputting the inverted data of the data held in the data latch DL-4 to the data input / output terminal group 10.

  By the operation as described above, it is possible to shorten the data reading time from the memory cell capable of holding 16-value data.

  In the above description, two sets from the lowest determination level are grouped, the higher determination level value of each group is inverted, the two determination results are NORed, and finally the result of each group is ORed is doing. The present invention is not limited to such a configuration, and, for example, two sets from the higher determination level may be used.

[16-value data write operation]
Next, a data write operation will be described.

  82 to 87 show data held in data latches DL-1 to DL-4 and sense latch SL in the first to seventh processing steps of the write operation, and threshold values of memory cells at the time of writing. It is a conceptual diagram which shows a determination level.

  82 shows data held in the respective latches in the first processing step of the write operation, and FIG. 83 shows threshold values and determination levels of the memory cells in the first processing step of the write operation.

  FIG. 84 shows data held in the respective latches in the second and third processing steps of the write operation, and FIG. 85 shows the threshold value of the memory cell in the second and third processing steps of the write operation. Indicates the level.

  FIG. 86 shows data held in the respective latches in the fourth to seventh processing steps of the write operation, and FIG. 87 shows the threshold value of the memory cell in the fourth to seventh processing steps of the write operation. Indicates the level.

  First, for a memory cell block in which a write operation is performed, a threshold value corresponding to data “1111” is set for all memory cells.

  82 and 83, in the first processing step of the write operation, the input data (00h and FFh in hexadecimal notation) is stored in data latch DL-1, and sense latch Transfer to SL. Based on the eighth determination level Vj8, writing up to a threshold value corresponding to level 9 is performed. During the write operation at the eighth determination level Vj8, data of 2 bytes among the remaining data is further stored in the data latch DL-2.

  Referring to FIGS. 84 and 85, in the second processing step of the write operation, write data conversion circuit 230 responds to the data included in data latches DL-1 and DL-2. By operating on a set of bit data, it corresponds to data in which the bit held in the data latch DL-1 is “1” and the bit held in the data latch DL-2 is “0”. Only the bit data of the sense latch SL is set to “0” level.

  In this manner, based on the data held in the sense latch SL, data is written into the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL. Here, the memory cells MC0 to MC15 are connected to the same word line WL. Further, the fourth determination value Vj4 is used as the verify operation determination value, and writing is performed up to the threshold level of level 5.

  At this time, data is written to the memory cell corresponding to data “0” in the sense latch.

  Data is written using a FN (Fowler-Nordheim) tunnel current by applying a high voltage to the word line WL.

  A voltage equal to or lower than the word line voltage is applied to the bit line BL corresponding to the bit whose bit data of the sense latch SL is “1” in order to relax the voltage applied from the word line WL. As a result, data is written only to the memory cells connected to the bit line BL corresponding to the bit data held in the sense latch of “0”.

  Further, referring to FIGS. 84 and 85, in the third processing step of the write operation, write data conversion circuit 230 applies the corresponding bit to the data included in data latches DL-1 and DL-2. By operating on the data set, sense corresponding to data in which the bit held in the data latch DL-1 is “0” and the bit held in the data latch DL-2 is “1”. Only the bit data of the latch SL is set to the “0” level.

  In this manner, based on the data held in the sense latch SL, data is written into the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL. Here, the twelfth determination value Vj12 is used as the determination value for the verify operation, and writing is performed up to the threshold level 13.

  During the write operation at the twelfth determination level Vj12, data for the remaining ¼ sector is stored in the data latch DL-3.

  Next, with reference to FIGS. 86 and 87, in the fourth processing step of the write operation, write data conversion circuit 230 receives data included in data latches DL-1, DL-2, and DL-3. , The bit held in the data latch DL-1 is "1", the bit held in the data latch DL-2 is "1", and the data latch DL Only bit data of the sense latch SL corresponding to data in which the bit held in −3 is “0” is set to the “0” level.

  In this manner, based on the data held in the sense latch SL, data is written into the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL. Here, the second determination value Vj2 is used as the determination value for the verify operation, and writing is performed up to level 3 of the threshold level.

  Further, referring to FIGS. 86 and 87, in the fifth processing step of the write operation, write data conversion circuit 230 operates on data included in data latches DL-1, DL-2 and DL-3. The bit held in the data latch DL-1 is “1” and the bit held in the data latch DL-2 is “0” by calculating the corresponding bit data set, and the data latch DL Only bit data of the sense latch SL corresponding to data in which the bit held in −3 is “1” is set to the “0” level.

  In this manner, based on the data held in the sense latch SL, data is written into the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL. Here, the sixth determination value Vj6 is used as the determination value for the verify operation, and writing is performed up to the threshold level 7.

  Similarly, in the sixth processing step of the write operation, the set of bit data of data held in the data latches DL-1, DL-2, DL-3 is set to (0, 0, 0). The corresponding sense latch bit data is set to “0”. After that, the tenth determination value Vj10 is used as the determination value for the verify operation, and writing is performed up to the threshold level 11.

  In the seventh processing step of the write operation, the set of bit data of the data held in the data latches DL-1, DL-2, DL-3 is the sense latch corresponding to (0, 1, 1). Bit data is set to “0”. Then, the 14th determination value Vj14 is used as the determination value for the verify operation, and writing is performed up to the threshold level 15. During the write operation period up to level 15, the remaining 2 bytes of data are stored in the data latch circuit DL-4.

  Further, although not shown, in the eighth to fifteenth processing steps of the write operation, a set of bit data of the data held in the data latches DL-1, DL-2, DL-3, DL-4 is set. , (1, 1, 1, 0), (1, 1, 0, 1), (1, 0, 0, 0), (1, 0, 1, 1), (0, 0, 1, 0) , (0, 0, 0, 1), (0, 1, 0, 0), bit data of the sense latch corresponding to (0, 1, 1, 1) is set to “0”. Then, the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth determination values are used as determination values for the verify operation, and writing is performed up to the threshold level corresponding to each step.

  As described above, in the 16-value flash memory according to the fifth embodiment, after the write command is input, the write operation is already started during the data input time to at least one of the plurality of data latch circuits. It is possible to shorten the writing time.

[Embodiment 6]
In the above description, the number of data latch circuits is four. However, the number of data latch circuits is one for data output, one for NOR operation of data, and OR operation between each bit. A total of three is sufficient.

  In the following, the flow of processing when data is written in the three data latch circuits DL-1 to DL-3 in writing data to a 16-value memory cell will be described.

  88 to 117 show the data latches DL-1 to DL-3 and the data held in the sense latch SL and the threshold value of the memory cell at the time of writing in the first to fifteenth processing steps of the writing operation. It is a conceptual diagram which shows a determination level.

  88 shows data held in the respective latches in the first processing step of the write operation, and FIG. 89 shows threshold values and determination levels of the memory cells in the first processing step of the write operation.

  First, for a memory cell block in which a write operation is performed, a threshold value corresponding to data “1111” is set for all memory cells.

  Referring to FIGS. 88 and 89, in the first processing step of the write operation, the input data (00h and FFh in hexadecimal representation) is stored in data latch DL-1, and sense latch Transfer to SL. Based on the eighth determination level Vj8, writing up to a threshold value corresponding to level 9 is performed. Thereafter, the data latch DL-1 is cleared. During the write operation at the eighth determination level Vj8, data of 2 bytes among the remaining data is further stored in the data latch DL-2.

  Here, reading is again performed at the eighth determination level Vj8, and the read data is stored in the sense latch SL.

  90 shows data held in the respective latches in the second processing step of the write operation, and FIG. 91 shows threshold values and determination levels of the memory cells in the second processing step of the write operation.

  Referring to FIGS. 90 and 91, in the second processing step of the write operation, write data conversion circuit 230 responds to the data included in sense latch SL and data latch DL-2. By operating on a set of bit data, a sense latch corresponding to data in which the bit held in the sense latch SL is “1” and the bit held in the data latch DL-2 is “0”. Only bit data of SL is set to “0” level.

  In this manner, based on the data held in the sense latch SL, data is written into the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL. Here, the fourth determination value Vj4 is used as the determination value for the verify operation, and writing is performed from level 1 to level 5 of the threshold level.

  Further, referring to FIG. 90 and FIG. 91, also in the second processing step of the write operation, reading is performed at the eighth determination level Vj8 and the read data is stored in the sense latch SL. The write data conversion circuit 230 calculates the corresponding bit data set for the data included in the sense latch circuits SL and DL-2, so that the bit held in the sense latch SL is “0”. Only the bit data of the sense latch SL corresponding to data in which the bit held in the data latch DL-2 is “1” is set to the “0” level.

  Based on the data held in the sense latch SL in this way, the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL are transferred from the threshold level level 9 according to the twelfth determination level Vj12. Writing is performed up to level 13.

  On the other hand, the remaining 2 bytes of data are further stored in data latch DL-3 during the period in which data is written up to level 13.

  In the operation up to the second processing step of the write operation, instead of performing the read operation at the determination level Vj8 each time, the data is held without clearing the data latch DL-1, and the sense is performed in the read operation. Instead of the data held in the latch SL, the data in the data latch DL-1 may be used. However, in the above description, the read operation at the determination level Vj8 is performed in order to be consistent with the following procedure.

  FIG. 92 shows data held in the respective latches in the third processing step of the write operation, and FIG. 93 shows thresholds and determination levels of the memory cells in the third processing step of the write operation.

  Referring to FIGS. 92 and 93, in the third processing step of the write operation, data is first read at eighth determination level Vj8, and the read data is stored in sense latch SL. The Control circuit 210 transfers the inverted data of sense latch SL to data latch DL-1.

  FIG. 94 shows data held in the respective latches in the fourth processing step of the write operation, and FIG. 95 shows threshold values and determination levels of the memory cells in the fourth processing step of the write operation.

  In the fourth processing step of the write operation, data is first read at the fourth determination level Vj4, and the read data is stored in the sense latch SL.

  The write data conversion circuit 230 stores, in the data latch DL1, the result of performing an OR operation on the corresponding bit data set for the data included in the sense latch SL and the data latch DL-1.

  FIG. 96 shows data held in the respective latches in the fifth processing step of the write operation, and FIG. 97 shows threshold values and determination levels of the memory cells in the fifth processing step of the write operation.

  The write data conversion circuit 230 calculates the corresponding bit data set for the data included in the data latch DL-3 and the sense latch SL, and the bit held in the data latch DL-3 is “1”. Only the bit data of the sense latch SL corresponding to the data in which the bit held in the sense latch SL is “1” is set to the “0” level.

  Based on the data held in the sense latch SL in this way, the determination level Vj2 is used as the verify voltage, and the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL are transferred to the threshold level from level 1 to level 3. Data is written to the memory.

  During the write operation at the second determination level Vj2, the remaining 2 bytes of data are stored in the data latch DL-2.

  FIG. 98 shows data held in the respective latches in the sixth processing step of the write operation, and FIG. 99 shows threshold values and determination levels of the memory cells in the sixth processing step of the write operation.

  The write data conversion circuit 230 calculates the corresponding bit data set for the data included in the data latch DL-1 and the data latch DL-3, and the bit held in the data latch DL-1 is “0”. Therefore, only the bit data of the sense latch SL corresponding to the data in which the bit held in the data latch DL-3 is “1” is set to the “0” level.

  Based on the data held in the sense latch SL in this way, the decision level Vj6 is used as the verify voltage, and the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL are transferred to the threshold levels 5 to 7 respectively. Data is written to the memory.

  FIG. 100 shows data held in the respective latches in the seventh processing step of the write operation, and FIG. 101 shows threshold values and determination levels of the memory cells in the seventh processing step of the write operation.

  In the seventh processing step of the write operation, data is read at the eighth determination level Vj8 and stored in the sense latch SL, and then the control circuit 210 transfers the data from the sense latch SL to the data latch DL-1.

  FIG. 102 shows data held in the respective latches in the eighth processing step of the write operation, and FIG. 103 shows threshold values and determination levels of the memory cells in the eighth processing step of the write operation.

  In the eighth processing step of the write operation, data is read at the twelfth determination level Vj12 and stored in the sense latch SL.

  The write data conversion circuit 230 performs an OR operation on a set of corresponding bit data with respect to the inverted data of the data held in the sense latch SL and the data included in the data latch DL-1, and the operation result is obtained from the data latch DL-1. To store.

  104 shows data held in the respective latches in the ninth processing step of the write operation, and FIG. 105 shows thresholds and determination levels of the memory cells in the ninth processing step of the write operation.

  The write data conversion circuit 230 calculates the corresponding bit data set for the data included in the data latch DL-1 and the data latch DL-3, and the bit held in the data latch DL-1 is “0”. Therefore, only the bit data of the sense latch SL corresponding to the data in which the bit held in the data latch DL-3 is “0” is set to the “0” level.

  Based on the data held in sense latch SL in this way, determination level Vj10 is used as a verify voltage, and memory cells MC0 to MC15 corresponding to the respective bits of sense latch SL are transferred from threshold level 9 to level 11 respectively. The data is written.

  106 shows data held in the respective latches in the tenth processing step of the write operation, and FIG. 107 shows threshold values and determination levels of the memory cells in the tenth processing step of the write operation.

  In the tenth processing step of the write operation, data is read at the twelfth determination level Vj12 and stored in the sense latch SL.

  The write data conversion circuit 230 calculates the corresponding bit data set for the data included in the sense latch SL and the data latch DL-3, the bit held in the sense latch is “0”, and the data latch Only bit data of the sense latch SL corresponding to data in which the bit held in DL-3 is “1” is set to the “0” level.

  108 shows data held in the respective latches in the eleventh processing step of the write operation, and FIG. 109 shows threshold values and determination levels of the memory cells in the eleventh processing step of the write operation.

  In the eleventh processing step of the write operation, the threshold level is applied to the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL using the determination level Vj14 as the verify voltage based on the data held in the sense latch SL. Level level 13 to level 15 data are written.

  110 shows data held in the respective latches in the twelfth processing step of the write operation, and FIG. 111 shows memory cell threshold values and determination levels in the twelfth processing step of the write operation.

  In the twelfth processing step of the write operation, data is read at the second determination level Vj2 and stored in the sense latch SL. Control circuit 210 transfers the data in sense latch SL to data latch DL1.

  The write data conversion circuit 230 calculates the corresponding bit data set for the data included in the sense latch SL and the data latch DL-2, the bit held in the sense latch is “1”, and the data latch Only bit data of the sense latch SL corresponding to data in which the bit held in DL-2 is “0” is set to the “0” level.

  112 shows data held in the respective latches in the thirteenth processing step of the write operation, and FIG. 113 shows threshold values and determination levels of the memory cells in the thirteenth processing step of the write operation.

  In the thirteenth processing step of the write operation, the threshold level is applied to the memory cells MC0 to MC15 corresponding to the respective bits of the sense latch SL using the determination level Vj1 as the verify voltage based on the data held in the sense latch SL. Data is written from level 1 to level 2.

  114 shows data held in the respective latches in the fourteenth processing step of the write operation, and FIG. 115 shows threshold values and determination levels of the memory cells in the fourteenth processing step of the write operation.

  In the fourteenth processing step of the write operation, data is read at the fourth determination level Vj4 and stored in the sense latch SL.

  The write data conversion circuit 230 performs an OR operation on a set of corresponding bit data with respect to the inverted data of the data held in the sense latch SL and the data included in the data latch DL-1, and the operation result is obtained from the data latch DL-1. To store.

  116 shows data held in the respective latches in the fifteenth processing step of the write operation, and FIG. 117 shows memory cell threshold values and determination levels in the fifteenth processing step of the write operation.

  The write data conversion circuit 230 calculates the corresponding bit data set for the data included in the data latch DL1 and the data latch DL-2, and the bit held in the data latch DL-1 is “0”. Thus, only the bit data of the sense latch SL corresponding to the data in which the bit held in the data latch DL-2 is “1” is set to the “0” level.

  Based on the data held in sense latch SL in this way, determination level Vj3 is used as a verify voltage, and memory cells MC0-MC15 corresponding to the respective bits of sense latch SL are transferred to threshold level level 3 to level 4 respectively. Data is written to the memory.

In the same manner, writing to levels 6, 8, 10, 12, 14, and 16 is performed.
That performs writing at decision level discernible binary or less, in each processing level, 4-level, 8-level, ..., writing at the level that can be identified 2 ⁿ values. At each processing level, two of the determination levels written first (for example, three determination levels that can determine four values when the four-level processing level is changed to the eight-level processing level) are used. Reading is performed by selecting (one at the upper and lower ends), bit data to be written is determined at the processing level, and writing is performed.

  As described above, in the 16-level flash memory according to the sixth embodiment, it is possible to reduce the number of data latch circuits and perform data writing from the memory cell holding 16-level data.

  In the above description, data is written from a lower determination level, but conversely, data may be written from a higher determination level.

  Similar to the writing to the quaternary memory cell of the fourth embodiment, the writing to the threshold levels 5 and 13, the writing to the levels 3 and 11, the writing to the levels 7 and 15, Writing to level 2 and level 10, writing to level 4 and level 12, writing to level 6 and level 14, and writing to level 8 and level 16 can be performed simultaneously. In any of these combinations, since the threshold voltage increases and the level difference (threshold voltage difference) of each set is equal, it is possible to use a similar set of drain voltages.

In the above description, a memory cell storing 16-value data is shown as an example, but more generally, the present invention can be applied to a memory cell storing 2 ⁿ -value data.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing a configuration of a flash memory 1000 that is a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. It is a figure which shows the data hold | maintained at each latch in the 1st process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 1st process step of read-out operation. It is a figure which shows the data hold | maintained at each latch in the 2nd process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 2nd processing step of read-out operation. It is a figure which shows the data hold | maintained at each latch in the 3rd process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 3rd process step of read-out operation. 3 is a timing chart for explaining a read operation of the flash memory 1000 according to the first embodiment. It is a figure which shows the 1st example of matching of the write level and write data which cannot determine both a high-order bit and a low-order bit by one read process. It is a figure which shows the 2nd example of matching of the write level and write data in which neither a high-order bit or a low-order bit can be decided by one read process. It is a figure which shows the 3rd example of matching of the write level and write data in which neither a high-order bit or a low-order bit can be decided by one read process. It is a figure which shows the 4th example of matching of the write level and write data in which neither a high-order bit or a low-order bit can be decided by one read process. FIG. 11 is a diagram showing data held in each latch in the second processing step of the read operation in the second modification of the first embodiment. FIG. 11 is a diagram showing a threshold value and a determination level of a memory cell in a second processing step of a read operation according to the second modification of the first embodiment. 11 is a timing chart for explaining a read operation of the flash memory according to the second modification of the first embodiment. It is a figure which shows the concept of the switching method of the connection of the sense latch circuit 120 and a bit line. It is a figure which shows the circuit structure for implement | achieving the concept shown in FIG. 16 concretely. It is a figure which shows the data hold | maintained at each latch in the 1st process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 1st process step of read-out operation. It is a figure which shows the data hold | maintained at each latch in the 2nd process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 2nd processing step of read-out operation. It is a figure which shows the data hold | maintained at each latch in the 3rd process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 3rd process step of read-out operation. It is a figure which shows the data hold | maintained at each latch in the 4th process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 4th process step of read-out operation | movement. It is a figure which shows the data hold | maintained at each latch in the 5th process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 5th process step of read-out operation. It is a figure which shows the data hold | maintained at each latch in the 6th process step of read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 6th process step of read-out operation. 12 is a timing chart for explaining a read operation of the flash memory according to the second embodiment. It is a figure which shows the data hold | maintained at each latch in the 1st process step of write-in operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 1st process step of write-in operation. It is a figure which shows the data hold | maintained at each latch in the 2nd process step of write-in operation. It is a figure which shows the threshold value and determination level of a memory cell in the 2nd process step of write-in operation. It is a figure which shows the data hold | maintained at each latch in the 3rd process step of write-in operation. It is a figure which shows the threshold value and determination level of a memory cell in the 3rd process step of write-in operation. 12 is a timing chart for explaining a write operation of the flash memory 1000 according to the third embodiment. It is a figure which shows the data hold | maintained at each latch in the 2nd process step of write-in operation. It is a figure which shows the threshold value and determination level of the memory cell of read-out operation in the 2nd processing step of write-in operation. It is a figure which shows the data hold | maintained at each latch in the 2nd process step of write-in operation. It is a figure which shows the threshold value and determination level of the memory cell of the write operation in the 2nd process step of a write operation. FIG. 4 is a diagram showing correspondence between write data writable by the procedure of the first embodiment and a threshold level of a memory cell transistor. FIG. 6 is a diagram showing correspondence between write data that cannot be written by the procedure of the first embodiment and a threshold level of a memory cell transistor. FIG. 25 is a diagram showing data held in each latch in the first processing step of the read operation according to the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in the first processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the second processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in a second processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the third processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in a third processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the fourth processing step of the read operation in the fifth embodiment. FIG. 24 is a diagram showing threshold values and determination levels of memory cells in the fourth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the fifth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in the fifth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the sixth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the sixth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the seventh processing step of the read operation of the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in a seventh processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the eighth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the eighth processing step of the read operation in the fifth embodiment. FIG. 24 is a diagram showing data held in each latch in the ninth processing step of the read operation in the fifth embodiment. FIG. 24 is a diagram showing threshold values and determination levels of memory cells in the ninth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the tenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in the tenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the eleventh processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in an eleventh processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the twelfth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the twelfth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the thirteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the thirteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the fourteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the fourteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the fifteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the fifteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the sixteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the sixteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the seventeenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in a seventeenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the eighteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the eighteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the nineteenth processing step of the read operation in the fifth embodiment. FIG. 38 is a diagram showing threshold values and determination levels of memory cells in the nineteenth processing step of the read operation in the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the first processing step of the write operation according to the fifth embodiment. FIG. 25 is a diagram showing a threshold value and a determination level of a memory cell in the first processing step of the write operation according to the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the second and third processing steps of the write operation according to the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the second and third processing steps of the write operation of the fifth embodiment. FIG. 17 is a diagram illustrating data held in each latch in the fourth to seventh processing steps of the write operation according to the fifth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the fourth to seventh processing steps of the write operation according to the fifth embodiment. FIG. 25 is a diagram showing data held in each latch in the first processing step of the write operation according to the sixth embodiment. FIG. 38 is a diagram showing a threshold value and a determination level of a memory cell in the first processing step of the write operation according to the sixth embodiment. FIG. 25 is a diagram showing data held in each latch in the second processing step of the write operation according to the sixth embodiment. FIG. 32 is a diagram showing a threshold value and a determination level of a memory cell in the second processing step of the write operation according to the sixth embodiment. FIG. 38 is a diagram showing data held in each latch in the third processing step of the write operation of the sixth embodiment. FIG. 32 is a diagram showing a threshold value and a determination level of a memory cell in a third processing step of the write operation according to the sixth embodiment. FIG. 25 is a diagram showing data held in each latch in the fourth processing step of the write operation of the sixth embodiment. FIG. 38 is a diagram showing a threshold value and a determination level of a memory cell in the fourth processing step of the write operation in the sixth embodiment. FIG. 29 is a diagram showing data held in each latch in the fifth processing step of the write operation of the sixth embodiment. FIG. 25 is a diagram showing threshold values and determination levels of memory cells in the fifth processing step of the write operation of the sixth embodiment. FIG. 29 is a diagram showing data held in each latch in the sixth processing step of the write operation of the sixth embodiment. FIG. 29 is a diagram showing a threshold value and a determination level of a memory cell in a sixth processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing data held in each latch in the seventh processing step of the write operation of the sixth embodiment. FIG. 38 is a diagram showing a threshold value and a determination level of a memory cell in a seventh processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing data held in each latch in the eighth processing step of the write operation of the sixth embodiment. FIG. 29 is a diagram showing a threshold value and a determination level of a memory cell in an eighth processing step of the write operation according to the sixth embodiment. FIG. 29 is a diagram showing data held in each latch in the ninth processing step of the write operation in the sixth embodiment. FIG. 32 is a diagram showing threshold values and determination levels of memory cells in the ninth processing step of the write operation of the sixth embodiment. FIG. 38 is a diagram showing data held in each latch in the tenth processing step of the write operation of the sixth embodiment. FIG. 38 is a diagram showing threshold values and determination levels of memory cells in the tenth processing step of the write operation in the sixth embodiment. FIG. 25 is a diagram showing data held in each latch in the eleventh processing step of the write operation of the sixth embodiment. FIG. 38 is a diagram showing a threshold value and a determination level of a memory cell in an eleventh processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing data held in each latch in the twelfth processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing a threshold value and a determination level of a memory cell in a twelfth processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing data held in each latch in the thirteenth processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing a threshold value and a determination level of a memory cell in a thirteenth processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing data held in each latch in the fourteenth processing step of the write operation of the sixth embodiment. FIG. 38 is a diagram showing a threshold value and a determination level of a memory cell in a fourteenth processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing data held in each latch in the fifteenth processing step of the writing operation in the sixth embodiment. FIG. 38 is a diagram showing threshold values and determination levels of memory cells in the fifteenth processing step of the write operation of the sixth embodiment. FIG. 10 is a schematic block diagram showing an overall configuration of a conventional AND type flash memory 8000. It is a figure which shows the relationship between the write data of the conventional binary AND type flash memory, and the threshold value of a memory cell transistor. It is a figure which shows the relationship between the write data of the conventional quaternary AND type flash memory 8000, and the threshold value of a memory cell transistor. It is a figure which shows the data hold | maintained at each latch in the 1st process step of the conventional write operation. It is a figure which shows the threshold value of the memory cell in the 1st process step of the conventional write operation. It is a figure which shows the data hold | maintained at each latch in the 2nd process step of the conventional write operation. It is a figure which shows the threshold value of the memory cell in the 2nd processing step of the conventional write operation. It is a figure which shows the data hold | maintained at each latch in the 3rd process step of the conventional write operation. It is a figure which shows the threshold value of the memory cell in the 3rd process step of the conventional write operation. It is a figure which shows the data hold | maintained at each latch in the 1st process step of the conventional read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 1st processing step of the conventional read-out operation | movement. It is a figure which shows the data hold | maintained at each latch in the 2nd process step of the conventional read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 2nd processing step of the conventional read-out operation | movement. It is a figure which shows the data hold | maintained at each latch in the 3rd process step of the conventional read-out operation | movement. It is a figure which shows the threshold value and determination level of a memory cell in the 3rd process step of the conventional read-out operation | movement.

Explanation of symbols

  10 data input / output terminals, 12 address signal input terminals, 14 command signal input terminals, 18, 20 signal lines, 100 memory cell arrays, 110 row decoders, 120 sense latch circuits, 130 column decoders, 142 data input / output buffers, 144 command signals Input buffer, 146 address signal input buffer, 150 power generation unit, 200 chip control circuit, 210 control circuit, 220 read data conversion circuit, 230 write data conversion circuit, 1000 nonvolatile semiconductor memory circuit.

Claims (2)

A non-volatile semiconductor device,
A memory cell array in which a plurality of memory cells are arranged;
Each memory cell has a threshold voltage selectively set to any one of threshold levels of first to second ⁿ (where n is an integer of 3 or more), Storing any one of 2 ⁿ different data codes, each data code including first to nth data;
The first threshold level is lower than the first determination level, and the Nth threshold level (where N is an integer not less than 2 and not more than 2 ⁿ −1) is the (N−1) th threshold level. It is higher than the determination level and lower than the Nth determination level, the ^2nth threshold level is higher than the ( ^2n- 1) ^th determination level,
The first to second ⁿ threshold levels are the 2 ⁿ data codes,
i) In the first step, the first data of each data code is divided into two first groups and rearranged according to which of the first and second logics,
ii) In the j-th step (where j is an integer greater than or equal to 2 and less than or equal to n), each of the 2 ^{j-1 -th} (j-1) groups is further replaced with the j-th data of each data code Are sorted into two j-th groups depending on which of the first and second logics is.
Correspond to those sorted by the procedure corresponding to the procedure,
The first data of each data code corresponding to the ^first to second ^n-1 threshold levels is a first logic, and the (2 ^n-1 +1) to second ⁿ threshold values. The first data of each data code corresponding to the level is the second logic,
In the (j−1) th group in which the (j−1) th data in the data code is the first logic, the jth data is the first in the data code in which the jth data is the first logic. Corresponds to a threshold level lower than the data code which is the logic of 2,
In the (j−1) th group in which the (j−1) th data in the data code is the second logic, the data code in which the jth data is the first logic is more in the jth data. Corresponding to a threshold level higher than the data code that is logic of 2,
A cell selection circuit for collectively selecting any one of the plurality of memory cells of the memory cell array (where m is an integer of 2 or more) in response to an address signal;
Based on the first to (2 ⁿ -1) determination levels, a data read / write operation for reading / writing m data codes to m memory cells selected by the cell selection circuit. A writing circuit;
Between the outside of the non-volatile semiconductor device and the data read / write circuit, the first to nth data of the m data codes is k bits for every k bits (where k is a natural number). And a data input / output circuit that exchanges data via the input / output node.
The nonvolatile semiconductor memory device, wherein the first to nth data of each data code is exchanged via the same input / output node at different timings. A non-volatile semiconductor device,
A memory cell array in which a plurality of memory cells are arranged;
Each memory cell has a threshold voltage selectively set to any one of threshold levels of first to second ⁿ (where n is an integer of 3 or more), Storing any one of 2 ⁿ different data codes, each data code including first to nth data;
The first threshold level is lower than the first determination level, and the Nth threshold level (where N is an integer not less than 2 and not more than 2 ⁿ −1) is the (N−1) th threshold level. It is higher than the determination level and lower than the Nth determination level, the ^2nth threshold level is higher than the ( ^2n- 1) ^th determination level,
The first to second ⁿ threshold levels are the 2 ⁿ data codes,
i) In the first step, the first data of each data code is divided into two first groups and rearranged according to which of the first and second logics,
ii) In the j-th step (where j is an integer greater than or equal to 2 and less than or equal to n), each of the 2 ^{j-1 -th} (j-1) groups is further replaced with the j-th data of each data code Are sorted into two j-th groups depending on which of the first and second logics is.
Correspond to those sorted by the procedure corresponding to the procedure,
The first data of each data code corresponding to the ^first to second ^n-1 threshold levels is a first logic, and the (2 ^n-1 +1) to second ⁿ threshold values. The first data of each data code corresponding to the level is the second logic,
In the (j−1) th group in which the (j−1) th data in the data code is the first logic, the jth data is the first in the data code in which the jth data is the first logic. Corresponds to a threshold level lower than the data code which is the logic of 2,
In the (j−1) th group in which the (j−1) th data in the data code is the second logic, the data code in which the jth data is the first logic is more in the jth data. Corresponding to a threshold level higher than the data code that is logic of 2,
A cell selection circuit for collectively selecting any one of the plurality of memory cells of the memory cell array (where m is an integer of 2 or more) in response to an address signal;
A data read circuit that reads m data codes from m memory cells selected by the cell selection circuit based on the first to (2 ⁿ -1) determination levels;
The first to n-th data of the m data codes read by the data read circuit is stored in the nonvolatile semiconductor memory via k output nodes every k bits (where k is a natural number). A data output circuit for outputting to the outside of the device,
The nonvolatile semiconductor memory device, wherein the first to nth data of each data code are output via the same output node at different timings.

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