JP2007115084A - Radio transmitter of telemeter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent electromagnetic wave noise from affecting radio communication between a radio transmitter 100 and a radio receiver 200. <P>SOLUTION: In the radio transmitter 100, a digital modulation circuit 20 digitally modulates an oscillation signal outputted from an oscillation circuit 10 by an ASK (amplitude shift keying) system. Since a signal to be modulated, which is modulated by a digital modulation system, is transmitted by a transmitting antenna 30, it is possible prevent electromagnetic wave noise from affecting radio communications between the radio transmitter 100 and the radio receiver 200. In addition, since the radio transmitter 100 does not use an analog-to-digital modulation circuit, it does not cause the problem that a circuit scale becomes large. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a telemeter radio transmitter for detecting a physical quantity to be detected and transmitting it by radio.

  2. Description of the Related Art Conventionally, a telemeter (hereinafter referred to as a first telemeter) including a wireless transmitter that detects a physical quantity to be detected by a sensor and transmits a detection signal wirelessly, and a wireless receiver that receives a detection signal transmitted from the wireless transmitter. 1 telemeter) has been proposed.

  In this device, an analog / digital conversion circuit that converts a detection signal output from the sensor into a digital signal and a modulation circuit that digitally modulates the digital signal output from the analog / digital conversion circuit are provided. An output modulated signal is transmitted.

In addition, in the transmitter described in Patent Document 1, a detection signal output from a sensor is not converted into a digital signal, but an analog signal is FM-modulated and a modulated signal is transmitted (hereinafter referred to as a second meter). Telemeter) has been proposed.
Japanese Patent Laid-Open No. 3-18240

  In the above-described first telemeter, since the wireless transmitter transmits a modulated signal by digital modulation, even if electromagnetic wave noise is mixed in the transmission path, as wireless communication between the wireless transmitter and the wireless receiver, Although it is possible to make the influence of electromagnetic noise relatively difficult, an analog / digital conversion circuit or the like is required, resulting in a problem that the circuit scale of the wireless transmitter increases.

  On the other hand, in the above-described second telemeter, since the wireless transmitter modulates and transmits the analog signal as it is, an analog / digital conversion circuit or the like is unnecessary, but the wireless transmitter and the wireless receiver. The wireless communication between the two is likely to be affected by electromagnetic noise, and the wireless receiver may not be able to obtain the demodulated signal and thus the physical quantity to be detected.

  An object of the present invention is to provide a radio transmitter for a telemeter that is less affected by electromagnetic noise while suppressing an increase in circuit scale.

  The present invention includes an oscillation circuit that outputs an oscillation signal whose period changes with a change in a physical quantity detected by a sensor, and a digital modulation circuit that modulates the oscillation signal output from the oscillation circuit by a digital modulation method. The modulated signal output from the digital modulation circuit is transmitted as a detection signal.

  Therefore, since the modulated signal modulated by the digital modulation method is transmitted as the detection signal, it can be made less susceptible to electromagnetic noise. In addition, since the radio transmitter does not use an analog / digital conversion circuit, an increase in circuit scale can be suppressed.

(First embodiment)
1 and 2 show a first embodiment of a telemeter of the present invention. FIG. 1 is a circuit diagram showing a circuit configuration of a telemeter radio transmitter, and FIG. 2 is a circuit diagram showing a circuit configuration of a telemeter radio receiver.

  The telemeter is composed of a radio transmitter that detects a physical quantity to be detected by a sensor and transmits a detection signal indicating the detected physical quantity, and a radio receiver that receives a detection signal transmitted from the radio transmitter. Has been. In the sensor of this embodiment, the resistance value changes due to a change in the physical quantity of the detection target, such as a strain gauge or a platinum temperature sensor.

Hereinafter, specific electronic circuit configurations of the radio transmitter and the radio receiver of the present embodiment will be described. First, the radio transmitter will be described. As shown in FIG. 1, the radio transmitter 100 includes an oscillation circuit 10. , A digital modulation circuit 20, and a transmission antenna 30.

  The oscillation circuit 10 is an RC oscillation circuit including capacitors 11 a and 11 b, a resistance element 12, NOT gates 13 a, 13 b and 13 c, and a sensor 14, and the oscillation cycle changes according to the resistance value of the sensor 14.

  The digital modulation circuit 20 digitally modulates the oscillation signal output from the oscillation circuit 10 by an ASK (Amplitude shift keying) method. The transmission antenna 30 transmits the modulated signal modulated by the digital modulation circuit 20 using an electromagnetic wave as a medium.

  Next, the radio receiver will be described. As shown in FIG. 2, the radio receiver 200 includes a receiving antenna 40a, a digital demodulator circuit 40, a frequency divider 50, a counter 60, an AND gate 61, a NOT gate 62, a clock generator. And an electronic control unit 80.

  The digital demodulation circuit 40 digitally demodulates the modulated signal from the wireless transmitter 100 received via the receiving antenna 40a. The frequency divider 50 reduces the frequency of the oscillation signal demodulated by the digital demodulation circuit 40 to 1 / N (N is an integer of 2 or more). As will be described later, the clock generator 70 generates a clock signal for measuring a high level period of the output signal of the frequency divider 50.

  The AND gate 61 performs an AND operation with the clock signal, the output signal of the frequency divider 50, and the output signal of a NOT gate 62 described later as inputs. The counter 60 counts the number of clock signals output from the AND gate 61 and outputs a count result with n bits. The NOT gate 62 performs a logical negation operation with an overflow signal output from the counter 60 as input, as will be described later.

  The electronic control unit 80 stores physical quantity conversion data indicating the correspondence between the number of clocks of the counter 60 and the physical quantity to be detected, and detects the number of clocks counted by the counter 60 based on the physical quantity conversion data. Convert to the target physical quantity.

  Hereinafter, specific operations of the wireless transmitter 100 and the wireless receiver 200 of the present embodiment will be described.

  First, the oscillation circuit 10 of the wireless transmitter 100 will be described. Assume that point A in FIG. 1 is at a low level and the output level of the NOT gate 13b is at a high level. If this state is indicated by only passive elements, an equivalent circuit shown in FIG. 3 is obtained.

  That is, the switch SW, the capacitor 11b, the sensor 14, the capacitor 11a, and the resistance element 12 are connected in series between the power source and the ground. When the switch SW is turned on, the input voltage of the NOT gate 13c at this time is V (t ) Transient response is as shown in Equation 1 below.

V (t) = V · exp (−t / τ) (Equation 1)
Here, τ is a time constant determined by the resistance component R and the capacitance C of the sensor 14 (τ = R × C).

  Therefore, when V (t) decreases exponentially with time and becomes smaller than the input reference value of the NOT gate 13c, the output level of the NOT gate 13c (that is, point A in FIG. 1). Transition from a low level to a high level. If this state is shown only by passive elements, the equivalent circuit shown in FIG. 4 is obtained.

  Here, when the switch SW is turned on, the charge moves from the capacitor 11a side to the capacitor 11b side. Along with this, the transient response of V (t) is as shown in Equation 2 below, and V (t) increases exponentially with the passage of time.

V (t) = V · {1-exp (−t / τ)} (Expression 2)
Thereafter, when V (t) becomes larger than the input reference value of the NOT gate 13c, the output level of the NOT gate 13c (that is, the point A in FIG. 1) transitions from the high level to the low level. If this state is indicated by only passive elements, an equivalent circuit shown in FIG. 5 is obtained. The circuit of FIG. 5 is the same as the circuit of FIG. 3, but charges are stored in the capacitors 11a and 11b.

  Therefore, when the switch SW is turned on, the charge moves from the capacitor 11b side to the capacitor 11a side. Along with this, the transient response of V (t) is as shown in Equation 1 above, and V (t) decreases exponentially with time.

  For this reason, when V (t) decreases and becomes smaller than the input reference value of the NOT gate 13c, the output level of the NOT gate 13c again changes from the low level to the high level.

  As described above, V (t) is repeatedly increased and decreased, and the NOT gate 13a outputs an oscillation signal. The transient response of V (t) depends on the exp (−t / τ) described above. For this reason, τ increases as the resistance component R of the sensor 14 increases, and a delay occurs in the excessive response of V (t), so that the period of the oscillation signal becomes longer.

  When such an oscillation signal is input to the digital modulation circuit 20, the digital modulation circuit 20 digitally modulates the oscillation signal by the ASK method and outputs a modulated signal. The modulated signal is transmitted from the transmission antenna 30. The

  Thereafter, when the modulated signal transmitted from the transmitting antenna 30 is received by the receiving antenna 40a of the radio receiver 200, the received demodulated signal is demodulated by the digital demodulation circuit 40, and the result shown in FIG. The oscillation signal shown is output.

  Next, the frequency divider 50 outputs a frequency-divided signal as shown in FIG. This divided signal is input to the AND gate 61. In addition to the divided signal, the AND gate 61 receives a clock signal from the clock generator 70 and a high level signal as an output signal of the NOT gate 62.

  Here, the output signal of the NOT gate 62 is a signal indicating whether or not the counter 60 is in an overflow state. When the counter 60 is in a non-overflow state, the NOT gate 62 outputs a high level signal. .

  When the divided signal and the clock signal are input to the AND gate 61 together with such a high level signal, the AND gate 61 outputs the clock signal only during the high level period of the divided signal.

  Along with this, the counter 60 counts the number of clocks of the clock signal output from the AND gate 61. The electronic control unit 80 counts the number of clocks by the counter 60 based on the output signal of the counter 60 and the output signal of the frequency divider 50, and further determines the number of clocks by the counter 60 based on the physical quantity conversion data. Convert to physical quantity.

  In addition, when the wireless communication between the wireless transmitter 100 and the wireless receiver 200 is interrupted for some reason, as shown in FIGS. 7A and 7B, compared to the case where normal wireless communication is performed, The high level period of the divided signal becomes longer. As a result, before the counter 60 finishes counting the number of clocks of the clock signal, the counter 60 enters an overflow state as shown in FIG. 7C, and the counter 60 overflows as shown in FIG. A high level signal is output as a signal.

  Here, when the NOT gate 62 receives a high level signal as an overflow signal, the output level of the NOT gate 62 changes from the high level to the low level, so that the output of the AND gate 61 is shown in FIG. The level becomes low level. When the electronic control unit 80 receives a high level signal as an overflow signal, the counter 60 is reset to output a high level signal as a reset signal to the counter 60 as shown in FIG.

  According to the present embodiment described above, in the wireless transmitter 100, the digital modulation circuit 20 modulates the oscillation signal output from the oscillation circuit 10 by digital modulation using the ASK method. Since the modulated signal modulated by the digital modulation method is transmitted from the transmission antenna 30, it is possible to make it less susceptible to electromagnetic noise in wireless communication between the wireless transmitter 100 and the wireless receiver 200. In addition, since the wireless transmitter 100 does not use an analog / digital conversion circuit, there is no problem that the circuit scale becomes large.

  In the first embodiment described above, an example in which ASK (Amplitude shift keying) is used as the digital modulation method of the digital modulation circuit 20 has been described. Instead, FSK (Frequency shift keying) or PSK (Phase shift keying) is used. keying) may be used.

  In the first embodiment described above, the circuit having the circuit configuration shown in FIG. 1 is used as the oscillation circuit. However, the present invention is not limited to this, and the oscillation cycle may be changed according to the change in the physical quantity detected by the sensor. Any circuit may be used.

(Second Embodiment)
In the first embodiment described above, an example in which one sensor 14 is provided in the wireless transmitter 100 has been described. Instead, in the second embodiment, three sensors 14 are provided in the wireless transmitter 100. An example will be described. The circuit configuration of the wireless transmitter 100 in this case is shown in FIG.

  The wireless transmitter 100 of the second embodiment includes a digital modulation circuit 20, a transmission antenna 30, oscillation circuits 10A, 10B, and 10C, connection / cutoff circuits 101, 102, and 103, an encoder 110, a counter 120, and a clock generator 130. have.

  The digital modulation circuit 20 is the same as the digital modulation circuit 20 of the first embodiment described above, and the transmission antenna 30 is the same as the transmission antenna 30 of the first embodiment described above. In addition, the oscillation cycles of the oscillation circuits 10A, 10B, and 10C change in accordance with the change in the resistance value of the sensor 14 as in the oscillation circuit 10 of the first embodiment described above.

  The connection / cutoff circuit 101 connects or cuts off between the oscillation circuit 10 </ b> A and the digital modulation circuit 20. The connection / cutoff circuit 102 connects or cuts off between the oscillation circuit 10 </ b> B and the digital modulation circuit 20. The connection / cutoff circuit 103 connects or cuts off between the oscillation circuit 10 </ b> C and the digital modulation circuit 20. The connection / disconnection circuits 101, 102, 103 constitute connection / disconnection means described in the claims.

  As will be described later, the encoder 110 controls the connection / cutoff circuits 101, 102, and 103 based on the number of clocks counted by the counter 120, respectively. The counter 120 counts the clock output from the clock generator 130. The encoder 110 corresponds to control means described in the claims.

  Next, the wireless receiver 200 of this embodiment will be described with reference to FIG.

  The radio receiver 200 includes a reception antenna 40a, a digital demodulation circuit 40, a frequency divider 50, counters 60 and 250, an AND gate 61, a clock generator 70, an electronic control device 80, connection / cutoff circuits 210 and 220, and an AND gate 230. , A clock generator 231, and a one-shot multi-circuit 240. In FIG. 9, the same components as those in FIG.

  The one-shot multi-circuit 240 includes AND gates 241 and 242, NOT gates 243 and 244, a decimal counter 245, and a clock generator 246, and responds to an oscillation signal output from the digital demodulation circuit 40 as will be described later. To output a pulse signal. The connection / cutoff circuit 210 connects and cuts off between the counter 60 and the electronic control unit 80. The connection / disconnection circuit 210 connects and disconnects between the counter 250 and the electronic control unit 80.

  The AND gate 230 calculates the logical product of the clock signal output from the clock generator 231 and the output signal output from the one-shot multicircuit 240. The counter 250 counts the number of clock signals output from the AND gate 230.

  As will be described later, the electronic control unit 80 according to the present embodiment obtains a physical quantity to be detected based on the number of clocks by the counter 60, and which of the oscillation circuits 10A, 10B, and 10C has detected the physical quantity. Execute processing to determine.

  Hereinafter, specific operations of the wireless transmitter 100 and the wireless receiver 200 of the present embodiment will be described.

  In the wireless transmitter 100, when the clock generator 130 generates a clock signal as shown in FIG. 10A, the counter 120 counts the count number K of the clock signal output from the clock generator 130.

  Here, the encoder 110 executes the computer program according to the flowchart shown in FIG.

  First, in step S100, the count number n of the built-in counter is reset (n = 0), and in the next step 110, whether the count number K by the counter 120 is equal to “0” {n (= 0) × 15}. Determine whether or not. If the count number K = “0”, it is determined YES and the process proceeds to step S120. Here, as shown in FIG. 10C, a high level signal is output to the connection / cutoff circuit 101 during the period of the count number K = “0” “1”.

  Next, in step 130, it is determined whether or not the count number K by the counter 120 is equal to “4” {n (= 0) × 15 + 4}. When the count number K ≠ “4”, the determination process of step 130 is repeated until the count number K = “4”. Thereafter, when the count number K = “4”, YES is determined in step 130, and the process proceeds to the next step 140.

  Here, as shown in FIG. 10D, a high-level signal is output toward the connection / cutoff circuit 102 during the period of the count number K = “4” and “5”.

  Next, in step 150, it is determined whether or not the count number K by the counter 120 is equal to “9” {n (= 0) × 15 + 9}. When the count number K ≠ “9”, the determination process of step 150 is repeated until the count number K = “9”. Thereafter, when the count number K = “9”, YES is determined in step 150 and the process proceeds to the next step 160. Here, as shown in FIG. 10E, a high-level signal is output toward the connection / cutoff circuit 103 during the period of the count number K = “9” and “10”.

  Thereafter, the count number n of the built-in counter is incremented (n = n + 1), and the process returns to step S110. Therefore, count number determination (step S110), high level output (step S120), count number determination (step S130), high level output (step S140), count number determination (step S150), high level output (step S160) , And increment (step S170) are repeated.

  When the encoder 110 repeats each process as described above, the count K = {“0”, “1”}, {“15”, “16”}, {“30”, “31”}... {{N × 15 ”and“ n × 15 + 1 ”} (hereinafter referred to as a transmission period), a high level signal is output to the connection / cutoff circuit 101. Accordingly, the connection / cutoff circuit 101 connects the oscillation circuit 10A and the digital modulation circuit 20 in each transmission period.

  Further, the count K = {“4”, “5”}, {“19”, “20”}, {“34”, “35”}... {{N × 15 + 4 ”,“ n × 15 + 5 ”} During this transmission period, a high level signal is output toward the connection / cutoff circuit 102. Accordingly, the connection / cutoff circuit 102 connects the oscillation circuit 10B and the digital modulation circuit 20 in each transmission period.

  Furthermore, count K = {“9”, “10”}, {“24”, “25”}, {“39”, “40”}... {{N × 15 + 9 ”,“ n × 15 + 10 ”} A high-level signal is output to the connection / cutoff circuit 103 during the transmission period. Accordingly, the connection / cutoff circuit 103 connects between the oscillation circuit 10C and the digital modulation circuit 20 in each transmission period.

  As described above, only one oscillation circuit of the oscillation circuits 10A, 10B, and 10C is connected to the digital modulation circuit 20, and the connected oscillation circuit is switched in the order of the oscillation circuits 10A, 10B, 10C, 10A,.

  Here, after the connection between the oscillation circuit 10A and the digital modulation circuit 20 is completed, the transmission stop period T1 is provided until the connection between the oscillation circuit 10B and the digital modulation circuit 20 is started. The transmission stop period T1 corresponds to two clocks of the clock generator 130 and indicates identification information of the sensor circuit A.

  A transmission stop period T2 is provided after the connection between the oscillation circuit 10B and the digital modulation circuit 20 is completed and before the connection between the oscillation circuit 10C and the digital modulation circuit 20 is started. The transmission stop period T2 corresponds to three clocks of the clock generator 130, and indicates identification information of the sensor circuit B.

  Furthermore, a transmission stop period T3 is provided after the connection between the oscillation circuit 10C and the digital modulation circuit 20 is completed and before the connection between the oscillation circuit 10A and the digital modulation circuit 20 is started. The transmission stop period T3 corresponds to the number of clocks of the clock generator 130 and indicates identification information of the sensor circuit C. The transmission stop periods T1, T2, and T3 correspond to the predetermined periods described in the claims.

  As described above, when any of the oscillation circuits 10A, 10B, and 10C is connected to the digital modulation circuit 20, and the transmission stop periods T1, T2, and T3 are provided between the transmission periods, the digital modulation circuit 20 includes As shown in FIG. 10F, the oscillation signals from the sensor circuits 10A, 10B, and 10C are input.

  When the oscillation signal is input to the digital modulation circuit 20 in this way, the digital modulation circuit 20 digitally modulates the oscillation signal by the ASK method and outputs a modulated signal. The modulated signal is transmitted from the transmission antenna 30. The

  Next, the operation of the wireless receiver 200 will be described. First, when the modulated signal transmitted from the wireless transmitter 100 is received by the receiving antenna 40a of the wireless receiver 200, the digital demodulation circuit 40 demodulates the received modulated signal and outputs an oscillation signal. . The oscillation signal shown in FIG. 12A is input to the frequency divider 50, and the frequency divider 50 outputs the frequency division signal shown in FIG. 12C to the AND gate 61.

  Here, since the clock generator 70 outputs the clock signal to the AND gate 61, the AND gate 61 outputs the clock signal from the clock generator 70 only during the high level period of the divided signal. Then, the counter 60 counts the number of clock signals output from the AND gate 61.

  Further, the one-shot multi circuit 240 outputs a pulse output signal shown in FIG. 12B based on the oscillation signal from the digital demodulation circuit 40 described above.

  Specifically, when the pulse output signal of the one-shot multi-circuit 240 becomes low level at the reception start timing of the oscillation signal of the oscillation circuit A, and when a certain period Td elapses after reception of the oscillation signal of the oscillation circuit A, the one-shot multi-circuit The pulse output signal of the circuit 240 becomes high level.

  Thereafter, the pulse output signal of the one-shot multi-circuit 240 becomes a low level at the reception start timing of the oscillation signal of the oscillation circuit B, and when a certain period Td elapses after reception of the oscillation signal of the oscillation circuit B, the one-shot multi-circuit 240 The pulse output signal goes high.

  After that, at the timing when the oscillation signal of the oscillation circuit C starts to be received, the pulse output signal of the one-shot multi-circuit 240 becomes low level, and when a certain period Td elapses after reception of the oscillation signal of the oscillation circuit C, the one-shot multi-circuit 240 The pulse output signal becomes high level. The operation of the internal circuit of the one-shot multi-circuit 240 will be described later.

  Such a pulse output signal from the one-shot multi-circuit 240 and a clock signal output from the clock generator 231 are input to the AND gate 230, and the AND gate 230 is clocked only during the high level period of the pulse output signal. The clock signal from the generator 231 is output. Along with this, the counter 250 counts the number of clocks of the clock signal output from the AND gate 230.

  Next, the electronic control unit 80 counts the respective count numbers of the counter 250 and the counter 60, and obtains a physical quantity to be detected based on the count numbers. Hereinafter, specific processing of the electronic control unit 80 will be described with reference to FIGS. 13 and 14.

  FIG. 13 is a flowchart showing the data detection process, and FIG. 14 is a flowchart showing the data conversion process. Data detection processing and data conversion processing are performed alternately.

  First, the data detection process will be described. In step S200, the counters 60 and 250 are initialized. Next, in step S210, the connection / cutoff circuit 210 is controlled to connect between the counter 60 and the electronic control device 80, and the connection / cutoff circuit 220 is controlled to control the counter 250 and the electronic control device 80. Block between.

  In the next step S220, the count number counted by the counter 60 is fetched, and the count number Kav in the high level period of the divided signal is obtained according to the fetched count number and the divided signal.

  Thereafter, when the pulse output signal of the above-described one-shot multi-circuit 240 changes from the low level to the high level, the first transmission period T of the oscillation circuit (this oscillation circuit is any circuit of 10A, 10B, and 10C). If (that is, the first connection between the digital modulation circuit 20 and the oscillation circuit) is completed, YES is determined in step S230.

  Next, in step S240, the connection / cutoff circuit 210 is controlled to cut off between the counter 60 and the electronic control device 80, and the connection / cutoff circuit 220 is controlled to control the counter 250 and the electronic control device. 80 is connected.

  In the next step S250, the count number counted by the counter 250 is fetched. Thereafter, when the pulse output signal of the one-shot multi-circuit 240 becomes a low level, it is determined that the transmission stop period has ended (that is, the counting by the counter 250 has ended), YES in step S260, and the counter 250 counts The counted number K2 is stored.

  Next, the data conversion process will be described.

  First, in step S300, the physical quantity of the detection target corresponding to the count number Kav is obtained based on the physical quantity conversion data.

  Next, based on the count number K <b> 2 by the counter 250, it is determined which oscillation circuit identification information indicates the transmission stop period described above. Specifically, it is determined whether or not K2 is larger than α1 (step S310).

  When K2 is larger than α1, it is determined as YES. In this case, the process proceeds to step S350, and it is determined that the transmission stop period described above indicates the identification information of the oscillation circuit 10c. That is, it is determined that the physical quantity to be detected is detected by the oscillation circuit 10c.

  In step S310, when K2 is smaller than α1, it is determined as NO, and it is determined whether K2 is larger than α2 (<α1) (step S320).

  Here, when K2 is larger than α2, YES is determined. In this case, the process proceeds to step S330, and it is determined that the transmission stop period described above indicates the identification information of the oscillation circuit 10b. That is, it is determined that the physical quantity to be detected is detected by the oscillation circuit 10b.

  In step S320, when K2 is smaller than α2, it is determined NO, the process proceeds to step S340, and it is determined that the above-described transmission stop period indicates the identification information of the oscillation circuit 10a. That is, it is determined that the physical quantity to be detected is detected by the oscillation circuit 10a.

  Next, a specific operation of the one-shot multi-circuit 240 of the wireless receiver 200 will be described with reference to FIG. FIGS. 15A to 15D show the operation of the oscillation signal and the AND gates 241, 242 and the decimal counter 245.

  First, the clock generator 246 outputs a clock signal to the AND gate 241, and when the high level signal from the NOT gate 244 is input to the AND gate 241, the AND gate 241 outputs the clock signal from the clock generator 246 to 10th. Output to the decimal counter 245.

  The decimal counter 245 is reset when it detects the falling edge of the oscillation signal from the digital demodulation circuit 40. For this reason, the decimal counter 245 repeatedly detects the falling edge of the clock signal within the transmission period of the oscillation circuit 10A, but is reset each time.

  Thereafter, when the transmission period of the oscillation circuit 10A ends and the decimal counter 245 detects the final falling edge Tsa of the clock signal, it resets and starts counting the clock signal from the clock generator 246.

  Accordingly, the decimal counter 245 outputs 4-bit data “Q0, Q1, Q2, Q3”. The 4-bit data “Q 0, Q 1, Q 2, Q 3” becomes “0, 0, 0, 0”, “1, 0, 0, 0”, “0, 1” in accordance with the counting operation of the decimal counter 245. , 0, 0 "... (" 1 "indicates a high level signal and" 0 "indicates a low level signal).

  After that, when a certain period td has elapsed from the start of the count, the decimal counter 245 counts the seventh pulse of the clock signal from the clock generator 246 to obtain 4-bit data “Q0, Q1, Q2, Q3”. “1, 1, 1, 0” is output. Here, the fixed period td corresponds to the oscillation period Th × k (> 1, for example, k = 1.5) of the oscillation signal.

  At this time, since the bit data “Q3” (= 0) is input to the NOT gate 243, the NOT gate 243 outputs a high level signal to the AND gate 242. For this reason, “Q0, Q1, Q2” and the high level signal (“1”) from the NOT gate 243 are input to the AND gate 242, and the level of the output signal of the AND gate 242 changes from the low level to the high level. Along with this, the level of the output signal of the NOT gate 244 changes from the high level to the low level.

  Therefore, even if the level of the clock signal from the clock generator 246 changes in the AND gate 241, the output signal of the AND gate 241 is maintained at the low level.

  Accordingly, the clock operation by the decimal counter 245 is stopped, and the decimal counter 245 continues to output “1, 1, 1, 0” as the 4-bit data “Q0, Q1, Q2, Q3”. For this reason, since the output signal of the NOT gate 243 is maintained at a low level, the output signal of the AND gate 242 is maintained at a low level.

  Thereafter, the transmission period of the oscillation circuit 10B is started, and when the decimal counter 245 detects the falling edge of the first clock signal in the transmission period, the decimal counter 245 is reset.

  Accordingly, the decimal counter 245 outputs “0, 0, 0, 0” as the 4-bit data “Q0, Q1, Q2, Q3”. At this time, since the bit data “Q3” (= 0) is input to the NOT gate 243, the NOT gate 243 outputs a high level signal to the AND gate 242.

  At this time, “Q0, Q1, Q2” and the high level signal from the NOT gate 243 are input to the AND gate 242, and the level of the output signal of the AND gate 242 changes from the high level to the low level.

  Thereafter, the decimal counter 245 repeats resetting until the end of the transmission period of the oscillation circuit 10B (Tsa in FIG. 15). At this time, since the count number by the decimal counter 245 is less than “7”, the 4-bit data “Q0, Q1, Q2, Q3” ≠ “1, 1, 1, 0”, and the output signal of the AND gate 242 is Maintained at a low level.

  When the operation described above is repeated and the transmission period of the oscillation circuit ends and the final falling timing Tsa of the clock signal comes, the level of the output signal of the AND gate 242 changes from the low level to the high level. That is, the one-shot multi-circuit 240 outputs a high level signal instead of a low level signal.

  After that, when the transmission period of the oscillation circuit starts and the first falling time Ten of the clock signal comes, the level of the output signal of the AND gate 242 changes from the high level to the low level. That is, the one-shot multi-circuit 240 outputs a low level signal instead of a high level signal.

  According to the present embodiment described above, in the wireless transmitter 100, after the connection between a certain oscillation circuit and the digital modulation circuit 20 is completed, a transmission stop period (predetermined period) is opened, and the next oscillation circuit and digital The connection with the modulation circuit 20 is started, and the transmission stop period indicates identification information of a certain oscillation circuit.

  Further, the wireless receiver 200 obtains a physical quantity to be detected based on the oscillation signal transmitted from the wireless transmitter 100. In addition, the radio receiver 200 can determine which oscillation circuit has detected the physical quantity to be detected by measuring the time length of the transmission stop period.

  In the second embodiment described above, after the end of the transmission period of a certain oscillation circuit, the transmission stop period is opened, the transmission period of the next oscillation circuit is started, and the transmission stop period indicates identification information of a certain oscillation circuit. Although such an example has been described, the present invention is not limited thereto, and the transmission stop period may indicate identification information of the oscillation circuit of the next oscillation circuit.

It is an electric circuit diagram which shows the electric circuit structure of the radio transmitter of the telemeter of 1st Embodiment which concerns on this invention. It is an electric circuit diagram which shows the electric circuit structure of the radio | wireless receiver of the telemeter of the above-mentioned 1st Embodiment. It is a circuit diagram for demonstrating the action | operation of an oscillation circuit in the radio transmitter of the telemeter of 1st Embodiment mentioned above. It is a circuit diagram for demonstrating the action | operation of an oscillation circuit in the radio transmitter of the telemeter of 1st Embodiment mentioned above. It is a circuit diagram for demonstrating the action | operation of an oscillation circuit in the radio transmitter of the telemeter of 1st Embodiment mentioned above. It is a timing chart for demonstrating the action | operation of the telemeter of the above-mentioned 1st Embodiment. It is a timing chart for demonstrating the action | operation of the telemeter of the above-mentioned 1st Embodiment. It is an electric circuit diagram which shows the electric circuit structure of the radio transmitter of the telemeter of 2nd Embodiment which concerns on this invention. It is an electric circuit diagram which shows the electric circuit structure of the radio | wireless receiver of the telemeter of 2nd Embodiment mentioned above. It is a timing chart for demonstrating the action | operation of the radio transmitter of the telemeter of the above-mentioned 2nd Embodiment. It is a flowchart which shows the control processing of the encoder of the radio | wireless transmitter of 2nd Embodiment mentioned above. It is a timing chart for demonstrating the action | operation of the radio | wireless receiver of the telemeter of the above-mentioned 2nd Embodiment. It is a flowchart which shows a part of control process of the encoder of the radio | wireless receiver of 2nd Embodiment mentioned above. It is a flowchart which shows the remainder of the control processing of the encoder of the radio | wireless receiver of 2nd Embodiment mentioned above. It is a timing chart for demonstrating the one-shot multi-circuit operation | movement of the radio | wireless receiver of 2nd Embodiment mentioned above.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Oscillator circuit, 20 ... Digital modulation circuit, 30 ... Transmitting antenna,
100: wireless transmitter, 200: wireless receiver.

Claims (3)

A telemeter wireless transmitter having a sensor for detecting a physical quantity of a detection target and transmitting a detection signal indicating the physical quantity detected by the sensor,
An oscillation circuit that outputs an oscillation signal whose period changes with a change in a physical quantity detected by the sensor;
A digital modulation circuit that modulates an oscillation signal output from the oscillation circuit by a digital modulation method,
A radio transmitter of a telemeter, wherein a modulated signal output from the digital modulation circuit is transmitted as the detection signal. A plurality of the oscillation circuits,
Connection / cutoff means for connecting or blocking between the plurality of oscillation circuits and the digital modulation circuit;
Control means for connecting only one oscillation circuit of the plurality of oscillation circuits to the digital modulation circuit and controlling the connection / cutoff means so as to sequentially switch the one oscillation circuit to be connected; The telemeter radio transmitter according to claim 1, further comprising: The control means controls the connection / cutoff means to complete a connection between one oscillation circuit of the plurality of oscillation circuits and the digital modulation circuit, and then opens a predetermined time before the next oscillation circuit. And a connection between the digital modulation circuit and the digital modulation circuit,
3. The telemeter radio transmitter according to claim 2, wherein the predetermined time indicates identification information of one of the one oscillation circuit and the next oscillation circuit.

Images