JP2007107925A - Current detection circuit, light receiver using same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current detection circuit capable of stable current detection. <P>SOLUTION: A first transistor Q1 is provided on a current path of a phototransistor 210. A bias current path 12 includes both a serially connected bias switch SW1 and a first bias resistor Rbias1 is provided in parallel with a main current path 10, which includes a phototransistor 210. A second transistor Q2 constitutes a current mirror circuit with the first transistor Q1 and generates a second current Iq2 acquired by multiplying a first current Iq1, which passes through the first transistor Q1, by a prescribed coefficient. A charge capacitor Cchg is charged with the second current Iq2, and the second current Iq2 is converted into a voltage. The bias current path 12 is turned on prior to the start of light reception by the phototransistor 210 and turned off when a prescribed time has elapsed since the start of light reception by the phototransistor 210. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a current detection circuit that detects a current flowing through a light receiving device.

  In various electronic devices, light incident from the outside is measured, and signal processing according to the measured amount of received light is performed. Examples of this include an illuminance sensor and a light receiving device for an infrared remote controller. Phototransistors, photodiodes, CCDs (Charge Coupled Devices), and the like are widely used as light receiving devices that receive light.

  Phototransistors and photodiodes output a current corresponding to the amount of received light. Therefore, the light receiving device performs signal processing by amplifying or voltage converting the current flowing through these light receiving devices. For example, Patent Document 1 discloses a light receiving device for an infrared remote sensor, and FIG. 3 discloses a configuration of a light receiving circuit. Patent Document 2 discloses a configuration of a light receiving circuit using an operational amplifier.

Japanese Patent Laid-Open No. 6-188835 JP 2005-216984 A

  In such a light receiving device, it may be desired to receive light only at a predetermined timing. As an example, let us consider flash emission control in a camera or camera-equipped mobile phone terminal. The flash emission time is controlled such that light emitted from the flash to the object to be imaged and reflected and returned is detected, and the flash emission is stopped when a predetermined amount of light is reflected. Therefore, if light is detected before the flash is emitted, sunlight and fluorescent light that should not be measured are also measured, which causes a problem that accurate light emission control cannot be performed.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a current detection circuit that can be used in a light receiving device that receives light at a predetermined timing and can stably detect a current.

  One embodiment of the present invention relates to a current detection circuit that detects a current flowing in a light receiving device connected to a detection terminal. The current detection circuit includes a first transistor provided on the current path of the light receiving device, a bias current path provided in parallel with the main current path including the light receiving device and capable of on / off control, and a current together with the first transistor. And a second transistor that constitutes a mirror circuit and multiplies a current flowing through the first transistor by a predetermined coefficient to be output from the current detection circuit. The bias current path is turned on prior to the start of light reception by the light receiving device. The bias current path may include a first bias resistor and a bias switch connected in series.

  According to this aspect, the current flows through the first transistor by turning on the bias current path and causing the current to flow prior to light reception. As a result, the first transistor is biased to the constant current region, the voltage at the detection terminal can be kept at a substantially constant value, and stable current detection becomes possible.

  The bias current path may be turned off after a predetermined time has elapsed since the light receiving device started to receive light. In this case, after the bias current path is turned off, only the current flowing through the light receiving device is detected, so that more accurate current detection can be performed.

  The current detection circuit further includes a latch circuit that latches a control signal whose signal level changes prior to the start of light reception by the light receiving device for a predetermined time, and the output signal of the latch circuit is a signal for controlling on / off of the bias current path It is good.

The current detection circuit may further include a second bias resistor provided between the first transistor and the detection terminal on the main current path. A bypass switch that bypasses the second bias resistor is further provided, and the bypass switch may be turned on prior to the start of light reception by the light receiving device.
By providing the second bias resistor, the impedance of the main current path can be increased during the period before the start of light reception, and the current consumption of the circuit can be reduced.

  The current detection circuit may charge a current flowing through the second transistor to a capacitor, convert the current into a voltage, and output the voltage. In this case, the photocurrent generated by the light receiving device can be integrated and output as a voltage.

  The current detection circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the current detection circuit as one LSI, the circuit area can be reduced and the characteristics of circuit elements such as transistors and resistors can be kept uniform.

  Another aspect of the present invention is a light receiving device. This light receiving device includes the above-described current detection circuit and a light receiving device connected to a detection terminal of the current detection circuit. The light receiving device may be a phototransistor or a photodiode. According to this aspect, the current flowing through the light receiving device can be suitably detected, and the amount of received light can be accurately measured.

  Yet another embodiment of the present invention is an electronic device. The electronic apparatus includes a light emitting device and the above-described light receiving device that detects light reflected by an external object from light emitted from the light emitting device. The light emitting device may stop light emission when the amount of reflected light detected by the light receiving device reaches a predetermined value.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  The current detection circuit according to the present invention enables stable current detection.

  FIG. 1 is a diagram illustrating a configuration of an electronic device 300 according to the present embodiment. Electronic device 300 according to the present embodiment is a mobile phone terminal with a camera, for example, and includes a flash. The electronic device 300 includes a light receiving device that detects light that is reflected and returned after emitting light from the flash, and stops light emission of the flash when a predetermined amount of light is detected.

The electronic apparatus 300 includes a battery 310, a DC / DC converter 320, a light emitting device 330, a light emission control unit 340, a light emission control transistor 350, and a light receiving device 200.
The battery 310 is a Li ion battery or the like, and outputs a battery voltage Vbat of about 3V to 4V. The DC / DC converter 320 boosts the battery voltage Vbat to about 300V in order to drive the light emitting device 330. The drive voltage Vdrv generated by the DC / DC converter 320 is supplied to the light emitting device 330.

  The light emitting device 330 is, for example, a xenon tube lamp, and a drive voltage Vdrv boosted to about 300 V is applied to one end thereof. A light emission control transistor 350 is connected to the other end of the light emitting device 330. As the light emission control transistor 350, a high breakdown voltage IGBT (Insulated Gate Bipolar Transistor) or the like is used. A light emission control signal SIG1 output from the light emission control unit 340 is input to the gate of the light emission control transistor 350.

  When the user turns on the flash, the light emission control unit 340 receives a control signal CNT that becomes high level in synchronization with the shutter timing. As described later, the light emission control unit 340 switches the light emission control signal SIG1 to a high level based on the control signal CNT. When the light emission control signal SIG1 becomes high level, the light emission control transistor 350 is turned on after the delay time τ elapses, and the light emitting device 330 emits light. The delay time τ is determined by the characteristics of the xenon tube lamp.

  Further, the light emission control unit 340 generates the first control signal CNT1 to the third control signal CNT3 based on the control signal CNT, and outputs them to the light receiving device 200. The light receiving device 200 transitions to a standby state for receiving light by the first control signal CNT1 to the third control signal CNT3 output from the light emission control unit 340. Thereafter, the light receiving device 200 detects the light emitted from the light emitting device 330 and reflected back to the external object to be photographed, and outputs the detected voltage Vdet. When the detection voltage Vdet exceeds a predetermined threshold voltage Vth, that is, when the detected reflected light reaches a predetermined light amount, the light emission control unit 340 sets the light emission control signal SIG1 to a low level and causes the light emitting device 330 to emit light. Stop.

  Next, the configuration of the light receiving device 200 according to the present embodiment will be described in detail. FIG. 2 is a circuit diagram showing a configuration of the light receiving device 200 according to the present embodiment. The light receiving device 200 includes a current detection circuit 100, a phototransistor 210, a charging capacitor Cchg, and an adjustment resistor Radj. The current detection circuit 100 is an IC integrated on a single semiconductor substrate. In this embodiment, the current detection circuit 100 is a functional IC 302 together with the light emission control unit 340 of FIG. 1 and the control circuit of the DC / DC converter 320. It is integrated.

  The phototransistor 210 is provided as a light receiving device, and a photocurrent Ip corresponding to incident light flows. The emitter of the phototransistor 210 is grounded, and the collector is connected to the detection terminal 102 of the current detection circuit 100.

  The current detection circuit 100 detects the photocurrent Ip flowing through the phototransistor 210 connected to the detection terminal 102. The current detection circuit 100 includes a first transistor Q1, a second transistor Q2, a first bias resistor Rbias1, a second bias resistor Rbias2, a bias switch SW1, a bypass switch SW2, a first resistor R10, and a second resistor R12. Further, outside the current detection circuit 100, an adjustment resistor Radj is connected between the resistance connection terminal 106 and the resistance connection terminal 108, and a charging capacitor Cchg is connected to the capacitance connection terminal 104.

  The first transistor Q1 is a PNP bipolar transistor (hereinafter simply referred to as a PNP transistor), and is provided on the current path of the phototransistor 210 that is a light receiving device. A first resistor R10 is connected between the emitter of the first transistor Q1 and the power supply line to which the power supply voltage Vdd is applied. The base collector of the first transistor Q1 is connected.

  The second transistor Q2 is a PNP transistor, and the base is commonly connected to the first transistor Q1. A second resistor R12 is provided between the emitter of the second transistor Q2 and the power supply line. Further, an adjustment resistor Radj is connected in parallel with the second resistor R12. The second transistor Q2 forms a current mirror circuit together with the first transistor Q1, the first resistor R10, the second resistor R12, and the adjustment resistor Radj. The second transistor Q2 outputs a second current Iq2 obtained by multiplying the first current Iq1 flowing through the first transistor Q1 by a predetermined coefficient. For example, the size ratio between the first transistor Q1 and the second transistor Q2 is set to about 4: 1.

  A path from the collector of the first transistor Q1 to the ground via the detection terminal 102 and the phototransistor 210 is defined as a main current path 10. A second bias resistor Rbias2 is provided between the first transistor Q1 and the detection terminal 102 in the main current path 10. The resistance value of the second bias resistor Rbias2 is set sufficiently high, for example, in the range of several MΩ to several tens of MΩ. In this embodiment, it is set to 10 MΩ as an example. The main current path 10 further includes a bypass switch SW2 that bypasses the second bias resistor Rbias2. The bypass switch SW2 is controlled to be turned on / off by the first control signal CNT1 output from the light emission control unit 340.

  The bias current path 12 is provided in parallel with the main current path 10. The bias current path 12 includes a first bias resistor Rbias1 and a bias switch SW1 connected in series between the collector of the first transistor Q1 and the ground. The resistance value of the first bias resistor Rbias1 is sufficiently lower than the second bias resistor Rbias2, for example, set to about 1/10. The resistance value of the second bias resistor Rbias2 is, for example, 1 MΩ.

  The bias switch SW1 is controlled to be turned on / off by a third control signal CNT3 generated by the light emission control unit 340. When the bias switch SW1 is turned on, the bias current path 12 is turned on and current flows. Hereinafter, the current flowing through the bias current path 12 is referred to as a bias current Ibias.

  The collector of the second transistor Q2 is connected to the capacitor connection terminal 104 via the mask switch SW3. The current detection circuit 100 charges the charging capacitor Cchg with the second current Iq2 flowing through the second transistor Q2, and converts it into a voltage. On / off of the mask switch SW3 is controlled by a second control signal CNT2 generated by the light emission control unit 340. The mask switch SW3 is turned off when the second control signal CNT2 is at a high level, and turned on when it is at a low level. When the mask switch SW3 is turned off, the path of the second current Iq2 is interrupted, and charging of the charging capacitor Cchg is stopped.

  A discharge switch SW4 is provided between the capacitor connection terminal 104 and the ground. The discharging switch SW4 is an NMOS transistor and is connected in parallel with the charging capacitor Cchg. The discharge switch SW4 has a drain connected to the capacitor connection terminal 104, a source grounded, and a gate to which the second control signal CNT2 generated by the light emission control unit 340 is input. The discharge switch SW4 is turned on when the second control signal CNT2 is at a high level and turned off when it is at a low level. When the discharge switch SW4 is turned on, the capacitor connection terminal 104 is grounded, and the charge stored in the charging capacitor Cchg is discharged. As will be described later, prior to the start of light reception by the phototransistor 210, the discharge switch SW4 is turned on for a predetermined time ΔT1 by the second control signal CNT2. The on / off of the discharge switch SW4 and the mask switch SW3 is controlled by the same second control signal CNT2.

  The current detection circuit 100 according to the present embodiment outputs the voltage appearing at the capacitor connection terminal 104 to the light emission control unit 340 as the detection voltage Vdet.

  Next, the configuration of the light emission control unit 340 will be described. FIG. 3 is a circuit diagram showing a configuration of the light emission control unit 340 according to the present embodiment. The light emission control unit 340 includes a comparator 20, a D latch circuit 22, a one-shot circuit 24, a first inverter 26, a NAND gate 28, a driver circuit 30, a second inverter 32, and a delay circuit 34.

  The light emission control unit 340 generates the first control signal CNT1 to the third control signal CNT3 based on the control signal CNT whose signal level changes prior to the start of light reception of the phototransistor 210 input to the control terminal 342, and detects the current. Output to the circuit 100. Further, the light emission control unit 340 generates the light emission control signal SIG1 based on the control signal CNT and the detection voltage Vdet output from the current detection circuit 100, and controls light emission and light emission stop of the light emitting device 330.

First, the block that generates the first control signal CNT1 to the third control signal CNT3 in the light emission control unit 340 will be described.
The control signal CNT input to the control terminal 342 is output as it is to the current detection circuit 100 as the first control signal CNT1.

  The second control signal CNT2 is generated by delaying the control signal CNT by the resistors R20 and R22, the transistor Q1, the first inverter 26, the second inverter 32, and the delay circuit 34. The transistor Q1 is an NPN-type bipolar transistor, and is grounded at the emitter. A resistor R22 is provided between the collector and the power supply line. A resistor R20 is connected between the base of the transistor Q1 and the control terminal 342.

  The resistors R20 and R22 and the transistor Q1 logically invert the control signal CNT and output it. The first inverter 26 logically inverts the inverted control signal CNT again.

  The output signal SIG10 of the first inverter 26 is input to the second inverter 32. The second inverter 32 logically inverts the output signal SIG10 of the first inverter 26 and outputs it to the delay circuit 34. The delay circuit 34 delays the output signal of the second inverter 32 by a predetermined time ΔT1. The signal output from the delay circuit 34 is output to the current detection circuit 100 as the second control signal CNT2. For example, the delay time ΔT1 by the delay circuit 34 is set to about 5 μs.

  A control signal CNT whose signal level changes prior to the start of light reception by the phototransistor 210 is input to the one-shot circuit 24. The one-shot circuit 24 generates a third control signal CNT3 that becomes high level for a predetermined time ΔT2 after the control signal CNT becomes high level. In other words, the one-shot circuit 24 is a latch circuit that latches the control signal CNT for a predetermined time ΔT2. The third control signal CNT3 is output to the bias switch SW1 and controls its on / off. The predetermined time ΔT2 is longer than the delay time ΔT1, and is set to about 10 μs, for example.

  The light emission control unit 340 configured as described above generates the first control signal CNT1 to the third control signal CNT3 and outputs them to the current detection circuit 100.

  Next, a block for generating the light emission control signal SIG1 for controlling the light emission of the light emitting device 330 in the light emission control unit 340 will be described. This block includes a comparator 20, a D latch circuit 22, a NAND gate 28, and a driver circuit 30.

  The comparator 20 compares the detection voltage Vdet output from the current detection circuit 100 with a predetermined threshold voltage Vth, and outputs a comparison signal SIG12 that is high when Vdet> Vth and low when Vdet <Vth. To do.

  The comparison signal SIG12 output from the comparator 20 is input to the clock terminal of the D latch circuit 22. The data terminal of the D latch circuit 22 is connected to the power supply line and is fixed at a high level. A control signal CNT is input to the reset terminal of the D latch circuit 22. The D latch circuit 22 functions as a latch circuit that is set by the positive edge of the comparison signal SIG12 and reset by the negative edge of the control signal CNT. The inverted output signal SIG14 of the D latch circuit 22 is output to the NAND gate 28.

  The NAND gate 28 outputs a negative logical product of the output signal SIG10 of the first inverter 26 and the inverted output signal SIG14 of the D latch circuit 22. The driver circuit 30 outputs the light emission control signal SIG1 that becomes high level while the output signal of the NAND gate 28 is low level.

  The operation of the current detection circuit 100 of FIG. 2 configured as described above and the light emission control unit 340 of FIG. 3 will be described. FIG. 4 is a time chart showing operation states of the current detection circuit 100 and the electronic device 300 according to the present embodiment.

  Prior to time T0, the power supply voltage Vdd has risen and the current detection circuit 100 is in a standby state. During this time, a very small photocurrent Ip (dark current) flows through the phototransistor 210. The photocurrent Ip flows as the first current Iq1 in the first transistor Q1. Since the first transistor Q1 is connected between the base and collector, the collector-emitter voltage Vce is equal to the base-emitter voltage Vbe. The potential Vptr of the detection terminal 102 is lower than the power supply voltage Vdd by the voltage drop ΔVr between the collector and emitter of the first transistor Q1 (= base-emitter voltage Vbe) and the first resistor R10 (Vdd−Vce−ΔVr). ) Appears. Since the photocurrent Ip flowing through the phototransistor 210 is small, the collector-emitter voltage Vce of the first transistor Q1 is small.

  At time T0, the control signal CNT becomes high level, and the light emission of the light emitting device 330 is instructed. As described above, at the same time as the control signal CNT becomes high level, the first control signal CNT1 becomes high level. Further, the third control signal CNT3 output from the one-shot circuit 24 is at a high level for a predetermined time ΔT2 from time T1.

  When the first control signal CNT1 becomes high level at time T0, the bypass switch SW2 is turned on, and the second bias resistor Rbias2 is bypassed. When the third control signal CNT3 becomes high level, the bias switch SW1 is turned on, and the bias current Ibias flows through the bias current path 12.

  At this time, the current Iq1 flowing through the first transistor Q1 is the sum (Ip + Ibias) of the photocurrent Ip and the bias current Ibias. As described above, since the resistance value of the first bias resistor Rbias1 is set sufficiently lower than the resistance value of the second bias resistor Rbias2, the first current Iq1 flowing through the first transistor Q1 increases. As a result, the collector-emitter voltage Vce of the first transistor Q1 increases compared to the period before time T0, and the potential Vptr of the detection terminal 102 decreases.

  The first current Iq1 is increased by turning on the bypass switch SW2 and causing the bias current Ibias to flow through the bias current path 12 at time T0 prior to the start of light reception by the light emitting device 330. An increase in the first current Iq1 means an increase in the collector current Ice of the first transistor Q1.

  FIG. 5 is a diagram showing current characteristics of the first transistor Q1 which is a bipolar transistor. In the figure, the vertical axis represents the collector current Ice (= Iq1), and the horizontal axis represents the collector-emitter voltage Vce (= base-emitter voltage Vbe). As shown in FIG. 5, when the collector current Ice (= Iq1) is small, the fluctuation width of the collector-emitter voltage Vce with respect to the fluctuation of the collector current Ice is large, and when the collector current Ice is large, the fluctuation width is small.

  Therefore, when the first current Iq1 (collector current Ice) is small as before time T0, the collector voltage of the first transistor Q1, and thus the voltage Vptr of the detection terminal 102, is only changed slightly. It will fluctuate. When the voltage Vptr at the detection terminal 102 changes, the bias state of the phototransistor 210 changes, and the photocurrent Ip may change. Further, when the voltage at the detection terminal 102 fluctuates, the characteristics of the current mirror circuit including the first transistor Q1 and the second transistor Q2 may deteriorate.

  Therefore, in the current detection circuit 100 according to the present embodiment, the bias switch SW1 is turned on at time T0 prior to the start of light reception to increase the first current Iq1. As a result, the first transistor Q1 is biased in the constant current region, the amount of change in the collector-emitter voltage Vce with respect to the amount of change in the collector current Ice is reduced, and the voltage Vptr at the detection terminal 102 can be kept constant. When the voltage Vptr at the detection terminal 102 is kept constant, the characteristics of the phototransistor 210 can be kept constant, and the characteristics of the current mirror circuit including the first transistor Q1 and the second transistor Q2 can be kept good. it can.

  Further, the second control signal CNT2 is latched from time T0 when the control signal CNT transitions from low level to high level until time T1 after the lapse of the predetermined time ΔT1, and maintains the high level. Since the discharge switch SW4 is turned on while the second control signal CNT2 is at a high level, the charge stored in the charge capacitor Cchg is discharged and initialized. Further, since the mask switch SW3 is turned off while the second control signal CNT2 is at the high level, the path of the second current Iq2 is interrupted. As a result, before time T1, even if light enters the light emitting device 330 and the photocurrent Ip flows, the charging capacitor Cchg is not charged and the detection voltage Vdet is fixed to the ground potential. Further, since the circuit current is interrupted, the power consumption can be reduced.

  At time T0, the light emission control signal SIG1 is at a high level, and the light emitting device 330 is ready to emit light. The light emitting device 330 according to the present embodiment emits light with a delay of time τ after the light emission control signal SIG1 becomes high level. Therefore, the above-mentioned predetermined time ΔT1 needs to be set to be shorter than the time τ.

  When the second control signal CNT2 becomes low level at time T1, the mask switch SW3 is turned on, the discharge switch SW4 is turned off, and the current detection circuit 100 enters a standby state.

  The light emitting device 330 emits light at time T2 after the elapse of time τ from time T0 when the light emission control signal SIG1 becomes high level. When the light emitting device 330 emits light, the reflected light enters the phototransistor 210 and the photocurrent Ip flows. Since the bias current path 12 is off at time T2, the first current Iq1 flowing through the first transistor Q1 is equal to the photocurrent Ip. As described above, since the first transistor Q1 is biased in the constant current region, even if the photocurrent Ip starts to flow, the potential Vptr of the detection terminal 102 hardly fluctuates.

  After time T2, the charging capacitor Cchg is charged by the second current Iq2 output from the second transistor Q2, and the detection voltage Vdet gradually increases. When the detection voltage Vdet reaches a predetermined threshold voltage Vth at time T3, the comparison signal SIG12 that is the output of the comparator 20 becomes high level, and the inverted output signal SIG14 of the D latch circuit 22 becomes low level. As a result, the light emission control signal SIG1 output from the driver circuit 30 becomes low level, the light emission control transistor 350 is turned off, and the light emission of the light emitting device 330 is stopped.

  Thereafter, at time T4 after a predetermined time ΔT2 has elapsed from time T0, the third control signal CNT3 becomes low level and the bias switch SW1 is turned off.

  According to the current detection circuit 100 according to the present embodiment, the first transistor Q1 constituting the current mirror circuit is turned on by turning on the bias switch SW1 prior to the start of light emission of the light emitting device 330, that is, the start of light reception by the phototransistor 210. Can be biased to a constant current region. Furthermore, as a result, the collector voltage of the phototransistor 210, that is, the potential Vptr of the detection terminal 102 can be maintained at a substantially constant value regardless of the value of the photocurrent Ip, and stable light detection can be performed.

  Also, by providing the second bias resistor Rbias2, the impedance of the main current path 10 can be increased during the period before the start of light reception, and the current consumption of the circuit can be reduced.

  FIG. 6 is a time chart showing the operating states of the current detection circuit 100 and the electronic device 300 when the amount of light received by the phototransistor 210 is small.

  The waveform before the start of light reception by the phototransistor 210, that is, from time T0 to time T2, is the same as that in FIG. The light emitting device 330 emits light at time T2 after the time τ has elapsed from time T0 when the control signal CNT becomes high level. When the distance from the light emitting device 330 to the reflector is long, the intensity of the reflected light becomes weak, so the amount of received light becomes small. As a result, the photocurrent Ip becomes smaller than in the case of FIG. 4, and the rising speed of the detection voltage Vdet is slow. During the period from time T2 to time T4, the first current Iq1 flowing through the first transistor Q1 is the sum of the photocurrent Ip and the bias current Ibias.

  The third control signal CNT3 becomes low level at time T3 after a predetermined time ΔT2 has elapsed from time T0. When the third control signal CNT3 becomes low level, the bias switch SW1 is turned off and the bias current path 12 is turned off. After time T4, when the bias switch SW1 is turned off, the bias current Ibias does not flow, so the first current Iq1 flowing through the first transistor Q1 becomes equal to the photocurrent Ip. As a result, the charging current for the charging capacitor Chg decreases, and the rising speed of the detection voltage Vdet decreases.

  Thereafter, when the detection voltage Vdet reaches the threshold voltage Vth at time T5, the light emission control signal SIG1 becomes a low level, and the light emission of the light emitting device 330 is stopped.

  The passage of a predetermined time (corresponding to ΔT2−τ in this embodiment) after the phototransistor 210 starts to receive light means that the rising speed of the detection voltage Vdet is slow, and thus the photocurrent Ip Means small. When the photocurrent Ip is equal to or lower than the bias current Ibias, if the charging capacitor Cchg is charged based on the first current Iq1 (= Ip + Ibias), the amount of received light cannot be accurately integrated. .

  Therefore, the light receiving device 200 and the light emission control unit 340 according to the present embodiment set the first current Iq1 equal to the photocurrent Ip by turning off the bias switch SW1 after a predetermined time (ΔT2-τ) has elapsed. Thus, the amount of light received by the phototransistor 210 can be accurately detected, and the time until the light emitting device 330 is turned off can be suitably controlled.

  At time T4, since the photocurrent Ip flows through the first transistor Q1, even if the bias current Ibias is turned off, the bias state of the first transistor Q1 does not fall to the non-constant current region, and is detected. The potential Vptr of the terminal 102 does not fluctuate significantly.

  Furthermore, according to the light receiving device 200 and the light emission control unit 340 according to the present embodiment, the provision of the discharge switch SW4 and the mask switch SW3 has the following effects.

  When a power supply voltage is applied to the current detection circuit 100, the phototransistor 210 is biased, so that a dark current flows or a photocurrent Ip flows due to light that should not be received from the outside and the charging capacitor Cchg is charged. There is a risk. Therefore, by turning on the discharge switch SW4 for a predetermined period prior to the start of light reception by the phototransistor 210, the charging capacitor Cchg is prevented from being charged by an unnecessary current and the charge stored in the charging capacitor Cchg is stored. And the detection voltage Vdet can be set to an initial value. Further, by turning off the mask switch SW3 prior to the start of light reception by the phototransistor 210, the charging capacitor Cchg can be prevented from being charged by the second current Iq2, and the current consumption of the circuit is reduced. can do.

  Further, by latching the comparison signal SIG12 output from the comparator 20 using the D latch circuit 22, when the detection voltage Vdet fluctuates in the vicinity of the threshold voltage Vth, the light emission control signal SIG1 is changed between the high level and the low level. By repeating the level, the light emitting device 330 can be prevented from repeating the light emitting state and the light emission stopped state.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, the bias current path 12 is configured by the first bias resistor Rbias1 and the bias switch SW1 connected in series. However, the present invention is not limited to this, and a constant current source that generates a predetermined current may be used. In this case, the bias state of the first transistor Q1 can be changed by turning on and off the constant current source.

  In the embodiment, the phototransistor 210 is used as the light receiving device, but a photodiode may be used instead.

  In the embodiment, elements composed of MOSFETs and bipolar transistors can be replaced with each other. These selections may be determined according to the semiconductor manufacturing process, cost, and use required for the circuit. Further, a circuit configuration in which the power supply voltage and the ground potential are inverted and the PNP transistor and the NPN transistor or the PMOS transistor and the NMOS transistor are replaced is also effective.

  In the embodiment, the case where the light receiving device 200 and the light emission control unit 340 are integrally integrated has been described, but a part thereof may be configured by discrete components. Which part is integrated may be determined according to cost, occupied area, application, and the like.

  The electronic device 300 using the current detection circuit 100 or the light receiving device 200 according to the present embodiment is not limited to the above-described mobile phone terminal, but includes a photodiode or a phototransistor such as an illuminance sensor or an infrared communication device. It can be widely used in devices that detect light using the above.

It is a circuit diagram which shows the structure of the electronic device which concerns on embodiment. It is a circuit diagram which shows the structure of the light-receiving device of FIG. It is a circuit diagram which shows the structure of the light emission control part of FIG. 2 is a time chart showing an operation state of the electronic apparatus of FIG. 1. It is a figure which shows the electric current characteristic of the 1st transistor which is a bipolar transistor. It is a time chart which shows the operation state of the electric current detection circuit and electronic device when the light reception amount by a phototransistor is small.

Explanation of symbols

  10 main current path, 12 bias current path, 20 comparator, 22 D latch circuit, 24 one-shot circuit, 26 first inverter, 28 NAND gate, 30 driver circuit, 32 second inverter, 34 delay circuit, C20 capacitor, 100 current Detection circuit, 102 detection terminal, 104 capacitance connection terminal, 106 resistance connection terminal, 108 resistance connection terminal, 200 light receiving device, 210 phototransistor, 300 electronic device, 302 functional IC, 310 battery, 320 DC / DC converter, 330 light emitting device 340 light emission control unit, 350 light emission control transistor, R10 first resistor, R12 second resistor, Q1 first transistor, Q2 second transistor, Rbias1 first bias resistor, Rbias2 second bias resistor, SW1 bias switch, SW2 bypass switch, SW3 mask switch, SW4 discharge switch, Radj adjustment resistor, Cchg charge capacitor, CNT1 first control signal, CNT2 second control signal, CNT3 third control signal.

Claims (13)

A current detection circuit for detecting a current flowing in a light receiving device connected to a detection terminal,
A first transistor provided on a current path of the light receiving device;
A bias current path provided in parallel with the main current path including the light receiving device and capable of on / off control;
A second transistor that constitutes a current mirror circuit together with the first transistor, multiplies the current flowing through the first transistor by a predetermined coefficient, and outputs the current detection circuit;
With
The current detection circuit, wherein the bias current path is turned on prior to the start of light reception of the light receiving device.   The current detection circuit according to claim 1, wherein the bias current path is turned off after a predetermined time has elapsed since the light receiving device started to receive light. A latch circuit that latches a control signal whose signal level changes prior to the start of light reception by the light receiving device for a predetermined time;
3. The current detection circuit according to claim 2, wherein the output signal of the latch circuit is a signal for controlling on / off of the bias current path in the previous period.   The current detection circuit according to claim 1, wherein the bias current path includes a first bias resistor and a bias switch connected in series.   5. The current detection circuit according to claim 1, further comprising a second bias resistor provided between the first transistor and the detection terminal on the main current path.   The current detection circuit according to claim 5, further comprising a bypass switch that bypasses the second bias resistor, wherein the bypass switch is turned on before light reception of the light receiving device.   The current detection circuit according to claim 1, wherein the current detection circuit charges a current flowing through the second transistor to a capacitor, converts the current into a voltage, and outputs the voltage.   7. The current detection circuit according to claim 1, wherein the current detection circuit is integrated on a single semiconductor substrate. A current detection circuit according to any one of claims 1 to 8,
A light receiving device connected to the detection terminal of the current detection circuit;
A light receiving device comprising:   The light receiving device according to claim 9, wherein the light receiving device is a phototransistor.   The light receiving device according to claim 9, wherein the light receiving device is a photodiode. A light emitting device;
The light receiving device according to any one of claims 9 to 11, wherein light emitted from the light emitting device detects light reflected by an external object;
An electronic device comprising:   13. The electronic apparatus according to claim 12, wherein the light emitting device stops light emission when the amount of reflected light detected by the light receiving device reaches a predetermined value.

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