JP2007103815A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure which ensures the insulated separation between the switching device regions, while utilizing a flat semiconductor layer. <P>SOLUTION: A semiconductor device 10 incorporates a p-type gallium nitride semiconductor layer 26. Switching device regions 12 and 16 are formed on the semiconductor layer 26 in a scattering manner. On a part of the top surface of the semiconductor layer 26 within the switching device regions 12 and 16, n-type semiconductor regions 32 and 36 are formed to be connected with electrodes 31 and 35, respectively. An inversion constraint structure 40 is provided to prevent any inversion of the conduction type on the top surface of the semiconductor layer 26 located between the switching device regions 12 and 16 lying adjacent to each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a III-V group compound semiconductor.

Development of semiconductor devices using gallium nitride (an example of a III-V group compound semiconductor) is in progress. Gallium nitride has high breakdown electric field strength and high saturation electron mobility, and thus is expected as a semiconductor material for semiconductor devices that achieve high breakdown voltage, high frequency, and high temperature operation.
In general, a plurality of switching elements are built in a semiconductor device. In this specification, a region where a switching element is formed is referred to as a switching element region. The switching element regions are formed dispersed in the semiconductor device. Between the adjacent switching element region and the switching element region, an element isolation region for insulating and separating the two is formed.
Non-Patent Document 1 describes a structure in which a switching element region is formed in a convex three-dimensional structure and the switching element region is spatially separated from adjacent switching element regions. The structure as described in Non-Patent Document 1 has a complicated shape, and there is a problem that the manufacturing difficulty level and the number of steps required for manufacturing increase.
Therefore, it is desired to develop a semiconductor device in which a flat semiconductor layer is used and a plurality of switching elements are formed in the semiconductor layer.

Yoshida Kiyoteru, "AlGaN / GaN Power FET", Furukawa Electric Journey Furukawa Electric Co., Ltd., January 2002, No. 109 TE Cook, jr., CC Fulton, WJ Mecouch, KM Tracy, RF Davis, EH Hurt, G. Lucovsky, and RJ Nemanich, "Measurement of the band offsets of SiO2 on clean n- and p-type GaN (0001)" , Journal of applied physics, volume 93, number 7, p.3995-4004

When a plurality of switching elements are formed in a flat semiconductor layer, the switching element region / element separation region / switching element region are continuously arranged in the horizontal direction in the semiconductor layer. In the case of a semiconductor device using silicon or the like, insulation isolation between the switching element region and the switching element region is ensured by controlling the threshold voltage of the parasitic transistor by a field oxide film thicker than the gate oxide film or ion implantation. .
The inventors of the present invention have found that a leak current flows between the switching element region and the switching element region when a similar structure is examined using gallium nitride. Examining this phenomenon in more detail, it was found that an inversion layer was formed on the surface of the semiconductor layer in the element isolation region, and a leak current was flowing through the inversion layer. We have determined that this physical phenomenon is caused when the conductivity type of the interface of the semiconductor layer in contact with the interlayer insulating film is reversed when a silicon oxide interlayer insulating film is formed on the surface of the gallium nitride semiconductor layer. It was. The above inversion phenomenon is introduced in Non-Patent Document 2. However, Non-Patent Document 2 only describes the general knowledge that inversion occurs, and does not consider the influence of this on the current device. Furthermore, it is not recognized that insulation isolation in the switching element region becomes insufficient because a leak current flows in the element isolation region.
An object of the present invention is to provide a structure that can ensure insulation isolation between a switching element region and a switching element region while using a flat semiconductor layer.

As described above, the present inventors have found that the characteristic peculiar to the III-V group compound semiconductor is a cause of generating a leakage current in the element isolation region of the semiconductor device. The present invention has been created by recognizing a phenomenon that has not been recognized so far and determining its cause.
Here, terms used in this specification will be described.
The “switching element” refers to a basic structure including the minimum components necessary for switching a current conduction state and a non-conduction state with time. For example, a transistor, a diode, etc. are included. Since the diode conducts with respect to a forward current and becomes non-conductive with respect to a reverse current, it can be said to be a switching element. The switching element here should be understood in a broad sense.
The “III-V compound semiconductor” is a semiconductor whose main material is a combination of a group III atom and a group V atom. The present invention is a useful technique for III-V compound semiconductors in which the surface conductivity type is reversed when an interlayer insulating film is formed on the surface. This type of III-V compound semiconductor includes GaN-based and InN-based semiconductors.

One semiconductor device created in the present invention has a plurality of switching elements formed therein. The semiconductor device of the present invention includes a semiconductor layer of a III-V group compound semiconductor containing a first conductivity type impurity. A source region of a III-V group compound semiconductor containing a second conductivity type impurity is formed in a part of the surface portion of the semiconductor layer. A source electrode is electrically connected to the source region. A drain region of a III-V group compound semiconductor containing a second conductivity type impurity is further formed on a part of the surface portion of the semiconductor layer. A drain electrode is electrically connected to the drain region. The source region and the drain region are separated by a semiconductor layer. The semiconductor device of the present invention further includes a gate electrode facing the surface of the semiconductor layer located between the source region and the drain region via a gate insulating film. A semiconductor device according to the present invention is characterized by including an inversion suppression structure that suppresses inversion of the surface of a semiconductor layer located around a switching element region including a source region and a drain region.
As described above, in the semiconductor device using the semiconductor layer of the III-V compound semiconductor, the present inventors have caused the occurrence of the inversion layer due to the leakage current flowing between the adjacent switching element regions. I found out that By forming a structure that suppresses the formation of an inversion layer on the surface of the semiconductor layer between adjacent switching element regions, a leakage current flows between the adjacent switching element regions. It was confirmed that this can be suppressed. Even when a flat semiconductor layer is used, it is possible to suppress the leakage current by suppressing the formation of the inversion layer.

The inversion suppression structure includes an interlayer insulating film formed on the surface of the semiconductor layer located around the switching element region including the source region and the drain region, and an inversion suppression film formed on the surface of the interlayer insulating film. The provided structure can be adopted. In this case, the work function of the inversion suppression film is characterized in that it has a magnitude that suppresses inversion of the conductivity type of the surface of the semiconductor layer.
When an interlayer insulating film is formed on the surface of the semiconductor layer in the element isolation region, it can be insulated and isolated in the vertical direction with respect to the semiconductor layer. Thereby, a multilayer wiring structure can be formed on the interlayer insulating film. However, as described above, when an interlayer insulating film is formed carelessly, there arises a problem that an inversion layer is formed on the surface of the semiconductor layer. Therefore, the present invention employs a structure in which an inversion suppression film having a large work function is provided on the surface of the interlayer insulating film. Thereby, the phenomenon that the surface of the semiconductor layer is inverted can be suppressed. Since the leakage current can be suppressed from flowing between the adjacent switching element regions, the semiconductor layer can be insulated and separated in the lateral direction.
By forming an inversion suppression structure having an interlayer insulating film and an inversion suppression film on the surface of the semiconductor layer between the adjacent switching element regions, the insulating separation between the adjacent switching elements and the switching elements is achieved. A semiconductor device guaranteed in both the vertical direction and the horizontal direction can be obtained.

The combination structure of the interlayer insulating film and the inversion suppression film is selected when the semiconductor layer is made of p-type gallium nitride (GaN), and silicon oxide (SiO ₂ ) is selected as the main material of the interlayer insulating film to suppress the inversion. Preferably, sulfur cadmium (CdS) is selected as the main material of the membrane.
When this combination of materials is selected, the phenomenon that the conductivity type of the surface of the semiconductor layer is reversed is suppressed, and leakage current can be suppressed.

  For the inversion suppressing structure, an insulating wall extending from the surface of the semiconductor layer located around the switching element region including the source region and the drain region toward the deep portion can be adopted. When an insulating wall is formed between the switching element region and the switching element region, it is possible to suppress a leakage current from flowing between the adjacent switching element region and the switching element region.

  In another semiconductor device created by the present invention, a plurality of switching elements are formed in a semiconductor layer of a III-V compound semiconductor containing impurities of the first conductivity type. In the semiconductor device of the present invention, the switching element region in which the switching element is formed is formed dispersed in the semiconductor layer. A semiconductor region of a group III-V compound semiconductor containing a second conductivity type impurity connected to the electrode is formed on a part of the surface portion of the semiconductor layer in the switching element region. An inversion suppression structure that suppresses inversion of the conductivity type of the surface of the semiconductor layer located between adjacent switching element regions is provided.

  According to the present invention, even when a flat III-V compound semiconductor semiconductor layer is used, an inversion layer is prevented from being formed on the surface of the semiconductor layer between adjacent switching element regions. And leakage current can be suppressed.

The features of the present invention are listed.
(First Embodiment) When the semiconductor layer is gallium nitride and the interlayer insulating film is silicon oxide, it is preferable to use a material having a work function of 6.4 eV or more as the material of the inversion suppression film. If this condition is satisfied, the formation of an inversion layer on the surface of the semiconductor layer can be suppressed. Sulfur cadmium (CdS) can be used as a material for this type of inversion suppression film.
(Second Embodiment) When the semiconductor layer is gallium nitride and the interlayer insulating film is silicon nitride, it is preferable to employ a material having a work function of 5.8 eV or more as the material of the inversion suppression film. If this condition is satisfied, the formation of an inversion layer on the surface of the semiconductor layer can be suppressed. Platinum (Pt), selenium (Se), or the like can be used as a material for this type of inversion suppression film.

FIG. 1 schematically shows a cross-sectional view of the main part of the semiconductor device 10.
The semiconductor device 10 includes a plurality of switching element regions 12 and 16. In the switching element regions 12 and 16, a lateral MOSFET (an example of a switching element) having a MOS (Metal Oxide Semiconductor) type gate structure is formed. An element isolation region 14 is provided between the switching element region 12 on the right side of the paper (hereinafter referred to as the right switching element region 12) and the switching element region 16 on the left side of the paper (hereinafter referred to as the left switching element region 16). The insulation separation between the right switching element region 12 and the left switching element region 16 is ensured.
The semiconductor device 10 includes a p-type gallium nitride (GaN) semiconductor layer 26. The semiconductor layer 26 is formed on the sapphire substrate 22 via a gallium nitride buffer layer 24. An n ⁺ -type gallium nitride source region 32 is formed in part of the surface portion of the semiconductor layer 26. A source electrode 31 made of a laminate of titanium (Ti) and aluminum (Al) is electrically connected to the source region 32. An n ⁺ -type gallium nitride drain region 36 is formed in a part of the surface portion of the semiconductor layer 26. A drain electrode 35 made of a laminate of titanium (Ti) and aluminum (Al) is electrically connected to the drain region 36. The source region 32 and the drain region 36 are separated by the semiconductor layer 26. The semiconductor device 10 further includes a gate electrode 34 facing the surface of the semiconductor layer 26 located between the source region 32 and the drain region 36 with a gate insulating film 33 interposed therebetween. Silicon oxide (SiO ₂ ) is used as the main material of the gate insulating film 33, and aluminum (Al) or nickel (Ni) is used as the main material of the gate electrode 34.
The source region 32, the drain region 36, etc. extend long in the direction perpendicular to the plane of the paper, are arranged in stripes when viewed in plan, and are repeatedly formed in the horizontal direction on the plane of the paper.

The semiconductor device 10 includes an interlayer insulating film 42 and an inversion suppressing film 44 formed on the surface of the interlayer insulating film 42 on the surface of the semiconductor layer 26 located in the element isolation region 14. Silicon oxide (SiO ₂ ) is used as the main material of the interlayer insulating film 42, and sulfur cadmium (CdS) is used as the main material of the inversion suppression film 44. A combined structure of the interlayer insulating film 42 and the inversion suppression film 44 is referred to as an inversion suppression structure 40. Note that the interlayer insulating film 42 and the gate insulating film 33 are formed in the same process, as will be described later in the manufacturing method, and have the same material, thickness, and the like.
The inversion suppression structure 40 can suppress inversion of the conductivity type of the semiconductor layer 26 in the surface portion 46 of the semiconductor layer 26 located between the right switching element region 12 and the left switching element region 14.

The work function of the inversion suppression film 44 has a magnitude that suppresses inversion of the surface portion 46 of the semiconductor layer 26. In order to prevent the inversion layer from being formed on the surface 46 of the semiconductor layer 26, the material of the inversion suppression film 44 (that is, the material having a work function required for not inversion) is selected in consideration of at least the following elements. Is desirable.
(1) The conductivity type of the semiconductor layer 26 (including the intrinsic case)
(2) Impurity concentration of the semiconductor layer 26 (3) Material of the interlayer insulating film 42 (4) Thickness of the interlayer insulating film 42 In consideration of the above (1) to (4), on the surface 46 of the semiconductor layer 26 The work function of the inversion suppression film 42 that is necessary because the inversion layer is not formed may be obtained. However, in practice, the work function required by factors other than the above (1) to (4) often varies, and it is desirable to add a correction based on an empirical rule.

FIG. 2 shows an energy band diagram of the surface portion 46 of the semiconductor layer 26 immediately below the inversion suppression structure 40.
FIG. 2A is an energy band diagram of this example. FIG. 2B is an energy band diagram of a comparative example when the inversion suppression film 44 is not formed.
First, as shown in the comparative example of FIG. 2B, when the inversion suppression film 44 is not formed, the energy band is largely curved on the surface 46 of the semiconductor layer 26, so that the surface 46 of the semiconductor layer 26 is curved. The intrinsic Fermi level (Ei) is located below the Fermi level (E _F ). Therefore, a state where electrons can exist is formed on the surface 46 of the semiconductor layer 26. An inversion layer is formed by electrons unevenly distributed on the surface 46 of the semiconductor layer 26. Therefore, since the drain region 36 of the right switching element region 12 and the source region 32 of the left switching element region 16 are conducted through the inversion layer, a leakage current is generated between them.
On the other hand, as shown in FIG. 2A, when the inversion suppression film 44 is formed, the degree of curvature of the energy band is reduced. Therefore, on the surface 46 of the semiconductor layer 26, the intrinsic Fermi level (Ei) of the surface 46 of the semiconductor layer 26 is positioned above the Fermi level (E _F ). As a result, electrons cannot exist on the surface 46 of the semiconductor layer 26, and the inversion layer is not formed. Therefore, insulation between the drain region 36 of the right switching element region 12 and the source region 32 of the left switching element region 16 is ensured.

In the insulating isolation region 14, when the interlayer insulating film 42 is formed on the surface of the semiconductor layer 26, the vertical insulating isolation can be ensured with respect to the semiconductor layer 26. Although not shown in FIG. 1, even if a multilayer wiring structure is formed on the interlayer insulating film 42, the semiconductor layer 26 and the multilayer wiring structure can be insulated and separated by the interlayer insulating film 42. Further, in the semiconductor device 10, since the inversion suppression film 44 having a large work function is employed on the surface of the interlayer insulating film 42, the phenomenon that the surface 46 of the semiconductor layer 26 is inverted can be suppressed. As a result, it is possible to suppress a leakage current from flowing between the right switching element region 12 and the left switching element region 16, so that it is possible to ensure the insulation isolation in the lateral direction of the semiconductor layer 26.
By forming an inversion suppression structure 40 including an interlayer insulating film 42 and an inversion suppression film 44 on the surface of the semiconductor layer 26 between the right switching element region 12 and the left switching element region 16, It is possible to obtain the semiconductor device 10 in which the insulation separation between the switching element regions 16 is ensured also in the vertical direction and the horizontal direction.

(Manufacturing method of the semiconductor device 10)
First, as shown in FIG. 3, a sapphire substrate 22 having sapphire (Al ₂ O ₃ ) as a main material is prepared. Next, a semiconductor layer 26 mainly composed of p-type gallium nitride (GaN) is grown on the sapphire substrate 22 via the buffer layer 24 using a MOCVD (Metal Organic Chemical Vapor Deposition) method. The thickness of the semiconductor layer 26 is about 2 μm, and its carrier concentration is adjusted to 1 × 10 ¹⁸ cm ⁻³ .
Next, as shown in FIG. 4, after the mask film 52 is formed on the entire surface of the semiconductor layer 26, a part of the mask film 52 is removed by etching. As the mask film 52, a USG (Undoped Silicon Glass) film or the like is used. Next, using the etching technique, the semiconductor layer 26 is etched from the exposed surface of the semiconductor layer 26 to a predetermined depth, and a groove 54 is formed in the surface portion of the semiconductor layer 26. The depth of the groove 54 is, for example, 0.5 μm.
Next, the source region 32 and the drain region 36 of n ⁺ -type gallium nitride (GaN) are selectively grown in the trench 54 by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. The carrier concentration of the source region 32 and the drain region 36 is adjusted to 1 × 10 ¹⁸ cm ⁻³ , for example. Next, after removing the mask film 52, a silicon oxide insulating film 30 is formed on the entire surface of the semiconductor layer 26, the source region 42, and the drain region 36 using a CVD (Chemical Vapor Deposition) method. As the insulating film 30, an HTO (High Temperature Oxide) film is used. The insulating film 30 later becomes the gate insulating film 33 or the interlayer insulating film 42. This state is shown in FIG.
Next, as shown in FIG. 6, an inversion suppression film 44 is formed on the surface of the insulating film 30 corresponding to the element isolation region 14 by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. For the inversion suppression film 44, sulfur cadmium (CdS) is used.
Next, after forming a contact hole in the insulating film 30 corresponding to the source region 42 and the drain region 36, titanium / aluminum is vapor-deposited at 10 nm / 100 nm, respectively, to form a source electrode and a drain electrode.
Next, a gate electrode is formed using a lift-off method.
In order to improve the contact property between the source electrode and the drain electrode, a heat treatment (N ₂ atmosphere, 500 ° C., 2 minutes) is performed.
Through these steps, the semiconductor device 10 shown in FIG. 1 can be obtained.

(Modification 1 of the semiconductor device 10)
FIG. 7 schematically shows a cross-sectional view of the main part of the semiconductor device 100.
In the semiconductor device 100, a part of the interlayer insulating film 42 in the element isolation region 14 is removed, and an opening 144 is formed. Therefore, the surface portion of the semiconductor layer 26 corresponding to the opening 144 is not in contact with the interlayer insulating film 42, and no inversion layer is formed on the surface portion of the semiconductor layer 26. Therefore, it is possible to suppress leakage current from flowing between the right switching element region 12 and the left switching element region 16.
Note that when it is desired to ensure the vertical isolation of the element isolation region 14, it is preferable to form an insulating film mainly made of silicon nitride in the opening 144. An inversion layer is less likely to be formed on the bonding surface of silicon nitride and gallium nitride than the bonding surface of silicon oxide and gallium nitride. Therefore, when a silicon nitride insulating film is used, the generation of leakage current can be reduced while ensuring vertical insulation isolation. In order to more reliably prevent the formation of the inversion layer, it is preferable to form an inversion suppression film on the insulating film of silicon nitride.

(Modification 2 of the semiconductor device 10)
FIG. 8 schematically shows a cross-sectional view of a main part of the semiconductor device 200.
In the semiconductor device 200, an insulating wall 244 extending from the surface of the semiconductor layer 26 located in the element isolation region 14 toward the deep portion is formed. The insulating wall 244 can be formed, for example, by filling a trench formed in the semiconductor layer 26 with organic oxirane (TEOS: Si (OC ₂ H ₅ ) ₄ ) and curing it by a thermal decomposition method. Since organic oxirane has a good film property, it can be sufficiently filled even in a deep trench, and a high-quality insulating wall can be formed.
When the insulating wall 244 is formed between the right switching element region 12 and the left switching element region 16, it is possible to suppress the leakage current from flowing between the right switching element region 12 and the left switching element region 16.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part sectional drawing of the semiconductor device of an Example is shown typically. An energy band diagram in an element isolation region is shown. A manufacturing process of a semiconductor device of an example is shown (1). The manufacturing process of the semiconductor device of an Example is shown (2). The manufacturing process of the semiconductor device of an Example is shown (3). A manufacturing process of a semiconductor device of an example is shown (4). The principal part sectional drawing of the modification 1 of the semiconductor device of an Example is typically shown. Sectional drawing of the principal part of the modification 2 of the semiconductor device of an Example is typically shown.

Explanation of symbols

12, 16: switching element region 14: element isolation region 22: sapphire substrate 24: buffer layer 26: semiconductor layer 31: source electrode 32: source region 33: gate insulating film 34: gate electrode 35: drain electrode 36: drain region 40 : Inversion suppression structure 42: Interlayer insulating film 44: Inversion suppression film

Claims (8)

A semiconductor device in which a plurality of switching elements are built,
A semiconductor layer of a III-V compound semiconductor containing an impurity of the first conductivity type;
A source region of a group III-V compound semiconductor that is formed in a part of the surface portion of the semiconductor layer and contains impurities of a second conductivity type;
A source electrode electrically connected to the source region;
A drain region of a III-V group compound semiconductor that is formed on a part of a surface portion of the semiconductor layer, is separated from the source region by the semiconductor layer, and contains a second conductivity type impurity;
A drain electrode electrically connected to the drain region;
A gate electrode facing the surface of the semiconductor layer located between the source region and the drain region via a gate insulating film;
An inversion suppressing structure that suppresses inversion of the conductivity type of the surface of the semiconductor layer located around the switching element region including the source region and the drain region;
A semiconductor device comprising: The inversion suppressing structure includes an interlayer insulating film formed on a surface of the semiconductor layer located around a switching element region including a source region and a drain region, and an inversion suppressing film formed on the surface of the interlayer insulating film. With
2. The semiconductor device according to claim 1, wherein the work function of the inversion suppression film is a magnitude that suppresses inversion of the conductivity type of the surface of the semiconductor layer. The semiconductor layer is mainly made of p-type gallium nitride (GaN),
The interlayer insulation film is mainly made of silicon oxide (SiO ₂ ),
3. The semiconductor device according to claim 2, wherein the inversion suppressing film is made of cadmium sulfide (CdS) as a main material.   The semiconductor device according to claim 1, wherein the inversion suppressing structure is an insulating wall extending from a surface of the semiconductor layer located around a switching element region including a source region and a drain region toward a deep portion. A semiconductor device in which a plurality of switching elements are formed in a semiconductor layer of a group III-V compound semiconductor containing impurities of the first conductivity type,
The switching element region in which the switching element is built is formed dispersed in the semiconductor layer,
A semiconductor region of a III-V group compound semiconductor containing impurities of the second conductivity type connected to the electrode is formed on a part of the surface portion of the semiconductor layer in the switching element region,
A semiconductor device comprising an inversion suppression structure that suppresses inversion of the conductivity type of the surface of the semiconductor layer located between adjacent switching element regions. The inversion suppressing structure includes an interlayer insulating film formed on a surface of the semiconductor layer located between adjacent switching element regions and an inversion suppressing film formed on the surface of the interlayer insulating film. Has
6. The semiconductor device according to claim 5, wherein a work function of the inversion suppressing film is a magnitude that suppresses inversion of the conductivity type of the surface of the semiconductor layer. The semiconductor layer is mainly made of p-type gallium nitride (GaN),
The interlayer insulation film is mainly made of silicon oxide (SiO ₂ ),
7. The semiconductor device according to claim 6, wherein the inversion suppressing film is made of cadmium sulfide (CdS) as a main material.   6. The semiconductor device according to claim 5, wherein the inversion suppressing structure is an insulating wall extending from a surface of the semiconductor layer located between adjacent switching element regions to a deep portion.

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