JP2007102460A - Semiconductor storage device and memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress increase in buffer size even when capacity of a memory increases and even when page size increases. <P>SOLUTION: This semiconductor storage device has: the memory 10 having a data area wherein page data corresponding to one page are divided in each correction range and are stored, and a plurality of redundant areas each wherein management information including an error correction code corresponding to the page data is divided in each the correction range and is stored; a first buffer memory 22 holding the page data corresponding to one correction range read from the data area; a second buffer memory 24 holding the management information corresponding to one page read from the redundant area; and an error correction circuit 21a detecting an error of the page data held in the first buffer memory 22 on the basis of the management information held in the second buffer memory 24, and correcting it. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a memory controller having an error correction circuit, and more particularly to a semiconductor memory device and a memory controller that are suitable when the memory capacity is increased and the page size is increased.

  Flash memory can be freely erased and written in data, and data contents are not lost even when the power is turned off. Therefore, the flash memory is rapidly spreading as a storage medium for digital devices such as digital cameras and portable music players. Further, a USB memory in which a USB connector is attached to a package equipped with a flash memory is expected as a simple data exchange medium for a personal computer.

  In such a flash memory, the memory area is divided into a plurality of blocks. Each block is divided into a plurality of units called “pages” as normal writing units. Each page has a data area in which page data is stored, and a redundant area in which management information such as an error correcting code (ECC) for detecting and correcting an error occurring in the page data and an address is stored. (See Patent Document 1). In the conventional flash memory, one page = 512 bytes, and an error correcting code (ECC) is stored in the redundant area so that the error can be corrected with 512 bytes as one unit.

  A semiconductor memory device using a conventional flash memory will be described with reference to the drawings. FIG. 5 is a block diagram schematically showing a configuration of a conventional semiconductor memory device. FIG. 6 is a schematic diagram schematically showing a data format of a page unit in a memory area of a flash memory in a semiconductor memory device according to a conventional example.

  Referring to FIG. 5, the semiconductor memory device 101 includes a flash memory 110 and a memory controller 120. The flash memory 110 can be read and written in a predetermined unit, and for example, a NAND flash memory can be used. As shown in FIG. 6, the flash memory 110 has a data area and a redundant area in the order of reading in the page unit of the memory area. The data area stores page data (for example, 2048 bytes) corresponding to one page, and is divided into areas D1 to D4 corresponding to a plurality of correctable ranges (for example, 512 bytes; correction range). One page data is divided and stored in areas D1 to D4. In the redundant area, management information such as an error correction code (ECC) and an address for detecting and correcting an error occurring in the page data is stored, and is divided into areas R1 to R4 corresponding to the areas D1 to D4. Management information of the areas D1 to D4 is stored in the areas R1 to R4, respectively. The memory controller 120 controls reading / writing of the flash memory 110.

  The memory controller 120 includes an interface circuit 121, a buffer memory 122, and an external interface circuit 123. The interface circuit 121 is a circuit that performs an interface between the flash memory 110 and the buffer memory 122, and includes an error correction circuit 121a. The error correction circuit 121a is a circuit for finding and correcting an error in the read page data based on the read management information, and a register 121b that temporarily holds management information for one correction range read from the redundant area. Have The buffer memory 122 temporarily holds page data for one page read from the data area (including page data corrected by the error correction circuit 121a). The external interface circuit 123 is a circuit that performs an interface between an external device (for example, a personal computer) and the buffer memory 122.

  Next, the operation of the conventional semiconductor memory device will be described with reference to the drawings. FIG. 7 is a flowchart schematically showing the operation of the conventional semiconductor memory device.

  When trying to read one page of data from the flash memory 110, the interface circuit 121 first reads the page data to be read from the beginning of the data area of the flash memory 110 (see FIG. 6) for one correction range. Read page data (step B1). In parallel with the reading of the page data, the interface circuit 121 holds the read page data for one correction range in the buffer memory 122 (step B2). Next, the interface circuit 121 checks whether or not reading of page data for one page has been completed from the data area (see FIG. 6) of the flash memory 110 (step B3). If reading of page data for one page has not been completed (NO in step B3), the process returns to step B1 to read page data for one correction range until the reading of page data for one page is completed. B3 will be repeated. When the reading for one page is completed (YES in step B3), the process proceeds to step B4.

  When the reading for one page is completed (YES in step B3), or when the entire error correction is not completed (NO in step B6), the interface circuit 121 stores the management information corresponding to the read page data. Management information for one correction range is read from the head of the redundant area (see FIG. 6) of the flash memory 110, and is temporarily stored in the register 121b (step B4). Next, the interface circuit 121 performs error correction on the page data held in the buffer memory 122 based on the management information for one correction range held in the register 121b (step B5). Next, the interface circuit 121 checks whether or not error correction of the entire page data held in the buffer memory 122 has been completed (step B6). If the entire error correction has not been completed (NO in step B6), the process returns to step B4, the management information for the next one correction range is read, and steps B4 to B6 are repeated until the error correction for the entire one page is completed. It will be. When the entire error correction is completed (YES in step B6), the process proceeds to step B7.

  When the entire error correction is completed (YES in step B6), the external interface circuit 123 outputs the page data held in the buffer memory 122 to an external device (for example, a personal computer) (step B7).

JP 2000-20409 A

  By the way, in recent years, with an increase in the capacity of flash memory, products of 1 page = 2K bytes have come to the market, and the page size tends to increase in the future. However, even in such a large-capacity flash memory, at present, a plurality of error correction codes are still stored in the redundant area as management information with 512 bytes as one correction range. Therefore, the error correction circuit needs to hold a plurality of calculation processes. That is, since error detection / correction cannot be performed until the end of reading of the entire page data, not an error correction unit, it is necessary to buffer the entire page data for one page for error correction, resulting in large circuit scale overhead. There is a problem of becoming. If the page size increases in the future, the buffer size will increase further, and the above problem will become more serious. In the conventional example, the buffer size increases at a rate of [error correction unit] × [number of segments].

  The main object of the present invention is to suppress an increase in buffer size even when the memory capacity is increased and the page size is increased.

  In a first aspect of the present invention, in a semiconductor memory device, management information including a data area in which page data for one page is divided and stored for each correction range and an error correction code corresponding to the page data is provided. A memory having a plurality of redundant areas that are divided and stored for each correction range; a first buffer memory that holds page data corresponding to a correction range that is one or less than the number of sections read from the data area; and Based on the second buffer memory holding management information for one page read from the redundant area and the management information held in the second buffer memory, an error in the page data held in the first buffer memory is found. And an error correction circuit for correcting.

  In the semiconductor memory device of the present invention, a first interface circuit that interfaces the memory with the first buffer memory and the second buffer memory, and a second interface that interfaces between an external device and the first buffer memory And a circuit.

  In the semiconductor memory device of the present invention, the first interface circuit reads management information for one page from the redundant area and stores the management information in the second buffer memory, and then the number is one or less than the number of sections from the data area. The page data corresponding to the number of correction ranges is read and held in the first buffer memory, and the second interface circuit receives the corrected page data for one correction range after correction by the error correction circuit. It is preferable to read from the memory and output to the external device.

  In the semiconductor memory device of the present invention, the first buffer memory holds page data for a plurality of correction ranges, and the first interface circuit stores page data for one correction range in the second interface. In parallel with reading from the first buffer memory and outputting to the external device, it is preferable that page data for the next one correction range is read from the data area and held in the first buffer memory.

  In the semiconductor memory device of the present invention, it is preferable that the memory is configured such that the redundant area is arranged at the head of reading and the data area is arranged after the redundant area.

  In the semiconductor memory device of the present invention, it is preferable that the second interface circuit packetizes page data for one correction range read from the first buffer memory based on a predetermined protocol and outputs the packet data to the external device. .

  In the semiconductor memory device of the present invention, the correction range is set to a size that fits into one packet without dividing the page data when the second interface circuit packetizes the page data. Is preferred.

  In the semiconductor memory device of the present invention, it is preferable that the second interface circuit performs transfer with the external device based on the USB standard.

  In a second aspect of the present invention, the memory controller includes a first buffer memory that holds page data for one correction range smaller than the number of ones or sections read from the data area of the memory, and a redundant area of the memory. An error in page data held in the first buffer memory is found and corrected based on the second buffer memory holding the read management information for one page and the management information held in the second buffer memory And an error correction circuit.

  According to the present invention (claims 1-15), since the page data held for correction is one or a correction range smaller than the number of divisions, even if the page size of the memory used increases, the buffer The increase in capacity can be suppressed to a small scale.

(Embodiment 1)
A semiconductor memory device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram schematically showing a configuration of a semiconductor memory device according to Embodiment 1 of the present invention. FIG. 2 is a schematic diagram schematically showing a page-by-page data format of the memory area of the flash memory in the semiconductor memory device according to the first embodiment of the present invention.

  Referring to FIG. 1, the semiconductor memory device 1 includes a flash memory 10 and a memory controller 20.

  The flash memory 10 can be read and written in a predetermined unit, and for example, a NAND flash memory can be used. As shown in FIG. 2, the flash memory 10 includes a redundant area and a data area in order of reading in the page unit of the memory area. The flash memory 10 is not limited to the data format and reading direction as shown in FIG. 2, and can be applied to the conventional data format as shown in FIG. 6 as long as it is performed from the read redundant area to the data area. The data format may be compatible, in which redundant areas and data areas are alternately arranged for each correction range. The data area stores page data (for example, 2048 bytes) corresponding to one page, and is divided into areas D1 to D4 corresponding to a plurality of correctable ranges (for example, 512 bytes; correction range). Page data for pages is divided and stored in areas D1 to D4. In the redundant area, management information such as an error correction code (ECC) and an address for detecting and correcting an error occurring in the page data is stored, and is divided into areas R1 to R4 corresponding to the areas D1 to D4. Management information of the areas D1 to D4 is stored in the areas R1 to R4, respectively. The correction range is set to a size that can be accommodated in one packet without dividing the page data when the external interface circuit 23 packetizes the page data.

  The memory controller 20 controls reading and writing of the flash memory 10. The memory controller 20 includes an interface circuit 21, a first buffer memory 22, an external interface circuit 23, and a second buffer memory 24. The interface circuit 21 is a circuit that interfaces the flash memory 10 with the first buffer memory 22 and the second buffer memory 24, and includes an error correction circuit 21a. The error correction circuit 21 a is a circuit that detects and corrects an error in the page data held in the first buffer memory 22 based on the management information held in the second buffer memory 24. The first buffer memory 22 temporarily holds page data for one correction range read from the data area (including page data corrected by the error correction circuit 21a). The external interface circuit 23 is a circuit that performs an interface between an external device (for example, a personal computer) and the first buffer memory 22, and packetizes the corrected page data for one correction range based on a predetermined protocol. Output to. The external interface circuit 23 is compatible with a USB cable without an additional interface, and performs transfer with an external device based on the USB standard. The second buffer memory 24 temporarily holds management information for one page read from the redundant area.

  For example, when the flash memory 10 uses an error correction code having a data area of one page of 2048 bytes, a redundant area of 64 bytes, and a correction range of 512 bytes, the first buffer memory 22 is 512 bytes, the second buffer memory 24 is 64 bytes in size. In FIG. 1, the first buffer memory 22 and the second buffer memory 24 are separated, but one buffer memory corresponds to the area corresponding to the first buffer memory 22 and the second buffer memory 24. It may be used by dividing into areas to be used.

  Next, the operation of the semiconductor memory device according to the first embodiment will be described with reference to the drawings. FIG. 3 is a flowchart schematically showing the operation of the semiconductor memory device according to the first embodiment of the present invention.

  When data for one page is to be read from the flash memory 10, the interface circuit 21 first sends management information corresponding to the page data to be read to the head of the redundant area (see FIG. 2) of the flash memory 10. The management information for one correction range is read out from (step A1). In parallel with the reading of the management information, the interface circuit 21 holds the read management information for one correction range in the second buffer memory 24 (step A2). Next, the interface circuit 21 checks whether or not the management information for one page has been read from the redundant area (see FIG. 2) of the flash memory 10 (step A3). If the management information for one page has not been read (NO in step A3), the process returns to step A1 to read the management information for the next one correction range until the management information for one page has been read. A1 to A3 are repeated. When reading of management information for one page is completed (YES in step A3), the process proceeds to step A4.

  When the reading of the management information for one page is completed (YES in step A3), or when the entire error correction is not completed (NO in step A8), the interface circuit 21 stores the page data to be read. The page data for one correction range is read from the beginning of the data area (see FIG. 2) of the flash memory 10 (step A4). In parallel with the reading of the page data, the interface circuit 21 holds the read page data for one correction range in the first buffer memory 22 (step A5). Next, the interface circuit 21 performs error correction of page data for one correction range held in the first buffer memory 22 based on the corresponding portion of the management information held in the second buffer memory 24 (step A6). ). Next, the external interface circuit 23 outputs the page data of one correction range held in the first buffer memory 22 to an external device (for example, a personal computer) (step A7). Next, the interface circuit 21 confirms whether or not error correction of the entire page data for one page has been completed (step A8). If the error correction for the entire page data for one page has not been completed (NO in step A8), the process returns to step A4 to read the page data for the next one correction range until the error correction for the entire page is completed. Steps A4 to A8 are repeated. When the error correction of the entire page data for one page is completed (YES in step A8), the process ends.

  Here, the redundancy area is usually very small compared to the data area. For example, in a commonly used NAND flash memory, 1 page = 512 bytes and a redundant area is 16 bytes, or 1 page = 2048 bytes and a redundant area is 64 bytes. In the conventional example (see FIG. 5), when the page size (page capacity) of the flash memory increases, the buffer size of the buffer memory that holds the page data greatly increases. In the first embodiment, the page size of the flash memory increases. Even if it increases, the buffer memory that holds the page data can be fixed in one correction range (for example, 512 bytes). In the first embodiment, when the page size (page capacity) of the flash memory increases, the buffer memory holding the management information increases to one page. However, the management information has a very small data amount compared to the page data. Therefore, an increase in buffer size can be suppressed. For example, when the page size is increased with 1 page = 512 bytes and a redundant area of 16 bytes as a basic unit, the required buffer memory size increases at a rate of 512 × [number of segments] in the conventional example (see FIG. 5). On the other hand, in the first embodiment, it increases only at a rate of 512 + 16 × [number of segments].

  According to the first embodiment, page data to be stored for correction needs only one correction range. Therefore, even if the page size of the memory to be used increases, the increase in buffer capacity can be suppressed to a small scale.

(Embodiment 2)
A semiconductor memory device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram schematically showing the configuration of the semiconductor memory device according to the second embodiment of the present invention.

  In the semiconductor memory device according to the second embodiment, the capacity of the first buffer memory 22 for holding page data is twice that of the first embodiment. Other configurations are the same as those in the first embodiment. The capacity of the first buffer memory 22 is not limited to twice that of the first embodiment, and may be a multiple in a range smaller than the capacity of the entire data area of the flash memory 10. For example, when the page data for one page is divided into four segments, the first buffer memory 22 may have a capacity for one to three segments.

  Next, the operation of the semiconductor memory device according to the second embodiment will be described. The basic operation of the semiconductor memory device according to the second embodiment is the same as that of the first embodiment (see FIG. 3), but the first page data (after error correction within the correction range) is output to the external device. In parallel with the step (step A7), the steps (steps A4 to A6) of reading / holding / error correcting the second page data (for the correction range) are performed. In addition, in parallel with the step of confirming completion after external output of the first page data (step A8), the step of reading / holding / error correcting / externally outputting the second page data (steps A4 to A7) May be performed. Further, in parallel with the step of correcting the error of the first page data (step A6), the step of reading and holding the second page data (steps A4 and A5) may be performed.

  According to the second embodiment, while the capacity of the first buffer memory 22 for holding the page data is set to be twice or more (a multiple of the number smaller than the number of segments), the page data that has been error-corrected is output to the outside. In addition, since the next page data can be read from the flash memory 10 to the first buffer memory 22, the processing waiting time can be reduced.

  Even in the configuration of the second embodiment (FIG. 4), the page size is based on page data (for one correction range) = 512 bytes and management information (for one correction range) = 16 bytes as basic units. The size of the buffer memory required when it increases increases only at a rate of 512 × 2 + 16 × N. On the other hand, if a similar configuration is used in the conventional example (see FIG. 5), it increases at a rate of 512 × 2 × N, so the difference from Embodiment 2 is large.

1 is a block diagram schematically showing the configuration of a semiconductor memory device according to Embodiment 1 of the present invention. FIG. 3 is a schematic diagram schematically showing a page-by-page data format of the memory area of the flash memory in the semiconductor memory device according to the first embodiment of the present invention. 3 is a flowchart schematically showing the operation of the semiconductor memory device according to the first embodiment of the present invention. It is the block diagram which showed typically the structure of the semiconductor memory device concerning Embodiment 2 of this invention. It is the block diagram which showed typically the structure of the semiconductor memory device concerning a prior art example. It is the schematic which showed typically the data format of the page unit of the memory area of the flash memory in the semiconductor memory device concerning a prior art example. 5 is a flowchart schematically showing the operation of a semiconductor memory device according to a conventional example.

Explanation of symbols

1, 101 Semiconductor memory device 10, 110 Flash memory (memory)
20, 120 Memory controller 21, 121 Interface circuit (first interface circuit)
21a, 121a Error correction circuit 22 First buffer memory 23, 123 External interface circuit (second interface circuit)
24 Second buffer memory 121b Register 122 Buffer memory

Claims (15)

A data area in which page data for one page is divided and stored for each correction range; and a plurality of redundant areas in which management information including error correction codes corresponding to the page data is stored for each correction range. A memory having
A first buffer memory that holds page data for a correction range that is less than one or the number of sections read from the data area;
A second buffer memory for holding management information for one page read from the redundant area;
An error correction circuit for finding and correcting an error in the page data held in the first buffer memory based on the management information held in the second buffer memory;
A semiconductor memory device comprising: A first interface circuit for interfacing the memory with the first buffer memory and the second buffer memory;
A second interface circuit for interfacing between an external device and the first buffer memory;
The semiconductor memory device according to claim 1, further comprising: The first interface circuit reads management information for one page from the redundant area and stores it in the second buffer memory, and then stores page data for a correction range that is one or less than the number of sections from the data area. Read and hold in the first buffer memory,
3. The second interface circuit according to claim 2, wherein after the correction by the error correction circuit, the corrected page data for one correction range is read from the first buffer memory and output to the external device. Semiconductor memory device. The first buffer memory holds page data for a plurality of correction ranges,
The first interface circuit reads the page data for one correction range from the first buffer memory and outputs the page data to the external device in parallel with the next 1 from the data area. 4. The semiconductor memory device according to claim 3, wherein page data corresponding to a correction range is read and held in the first buffer memory.   5. The memory according to claim 1, wherein the redundant area is arranged at a head of reading, and the data area is arranged after the redundant area. 6. Semiconductor memory device.   6. The second interface circuit according to claim 2, wherein the page data for one correction range read from the first buffer memory is packetized based on a predetermined protocol and output to the external device. A semiconductor memory device according to claim 1.   7. The correction range according to claim 6, wherein when the page data is packetized by the second interface circuit, the correction range is set to a size that fits in one packet without dividing the page data. Semiconductor memory device.   8. The semiconductor memory device according to claim 6, wherein the second interface circuit performs transfer with the external device based on a USB standard. A first buffer memory that holds page data for a correction range that is less than one or the number of sections read from the data area of the memory;
A second buffer memory for holding management information for one page read from the redundant area of the memory;
An error correction circuit for detecting and correcting an error in the page data held in the first buffer memory based on the management information held in the second buffer memory;
A memory controller comprising: A first interface circuit for interfacing the memory with the first buffer memory and the second buffer memory;
A second interface circuit for interfacing between an external device and the first buffer memory;
The memory controller according to claim 9, further comprising: The first interface circuit reads management information for one page from the redundant area and stores it in the second buffer memory, and then stores page data for a correction range that is one or less than the number of sections from the data area. Read and hold in the first buffer memory,
11. The second interface circuit according to claim 10, wherein after the correction by the error correction circuit, the corrected page data for one correction range is read from the first buffer memory and output to the external device. Memory controller. The first buffer memory holds page data for a plurality of correction ranges,
The first interface circuit reads the page data for one correction range from the first buffer memory and outputs the page data to the external device in parallel with the next 1 from the data area. 12. The memory controller according to claim 11, wherein page data corresponding to a correction range is read and held in the first buffer memory.   The said 2nd interface circuit packetizes the page data for 1 correction | amendment range read from the said 1st buffer memory based on a predetermined protocol, and outputs it to the said external device. The memory controller according to one.   14. The correction range according to claim 13, wherein when the page data is packetized by the second interface circuit, the correction range is set to a size that fits in one packet without dividing the page data. Memory controller.   15. The memory controller according to claim 13, wherein the second interface circuit performs transfer with the external device based on a USB standard.

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