JP2007097088A - Data error correcting apparatus, and data error correcting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data error correcting apparatus or the like which ensures reliability and improves performance by ensuring control continuity by eliminating delay caused by path switching at the time of error detection in a transmission line duplexed system. <P>SOLUTION: A data error correcting apparatus includes: data reception error detecting parts 201, 211 for separating data transmitted from transmission lines of respective systems for each predetermined unit and detecting an error of the relevant data; a double system synchronizing part 220 for synchronizing the data; and an error correcting part 230 for discarding data containing the error, between the data separated for each unit of one system and selecting normal data of the other system, thereby correcting the error of the data transmitted in a transmission line duplexed system. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data error correction apparatus used in a transmission line duplex system in which a plurality of LSIs (Large Scale Integration) are connected by duplex transmission paths.

  High-performance LSIs have been developed in order to meet the increasing demands for calculation performance in the field of scientific and engineering calculations. On the other hand, the interface between LSIs is increasing because of realizing such high performance. For this reason, the input / output interface of the LSI is serialized. However, compared with the conventional delivery of parallel data between LSIs, the delivery of serial data tends to have a higher error rate. For this reason, it is necessary to perform error correction with a small amount of hardware resources and continue operation.

  In such a case, the first problem is that the duplexed one system is in a semi-standby state, so a delay due to switching occurs when an error in the normal system is detected, continuity of control cannot be maintained, and performance degradation occurs. Was.

  As a second problem, since a system once switched due to a failure cannot be recovered again, if the failure occurs twice, maintenance must be performed due to a planned stop or the interface must be blocked.

  As a third problem, there is a retransmission method as this kind of reliability securing means. However, when a failure occurs, retransmission is involved, and as in the above, control continuity cannot be maintained and performance degradation occurs. Was.

  A specific situation regarding the above problem will be described with reference to FIG. FIG. 5 is a block diagram illustrating the configuration of a data error correction apparatus used in a conventional redundant transmission line system. Referring to FIG. 5, the first LSI 100 that is the starting point of the data transfer, the two data transfer paths from the first LSI 100, the second LSI 200 that is the end point of the data transferred from the data transfer path, and Consists of.

  The first LSI 100 includes an internal logic unit 101 for instructing processing contents of one data, and a data duplexing transmission unit 102 for duplexing one data according to an instruction from the internal logic unit 101 and transmitting the data to two data transfer paths. It consists of.

  The second LSI 200 performs reception processing of each data transferred from the data duplex transmission unit 102, detects an error of each received data, and sends data to the first arrival determination unit 250 together with the error information. Error detection units 201 and 211, first arrival determination unit 250 that handles first arrival data among data transmitted from data reception error detection units 201 and 211, reception data register 260 that receives first arrival data, and reception data An error determination path switching unit 270 that performs error determination of data transmitted from the register 260 and switches a path according to the determination result, and an internal logic unit that instructs the processing content of the data transmitted from the error determination path switching unit 270 280.

  In the conventional redundant transmission line system, as shown in FIG. 5, the duplexed one system is in a standby state, and when a failure occurs in the operational system, the error determination path switching unit 270 performs a switching operation. When the route is the last arrival, it is necessary to use the first standby side data. Therefore, a buffer for securing first-arrival data is required in the first-arrival determination unit 250, and there is a problem that the circuit scale becomes large.

  Further, the error determination path switching unit 270 has a time due to the switching operation, a delay occurs, the continuity of control cannot be maintained, and the performance is deteriorated. Also, since a path once switched cannot be automatically recovered, when switching occurs in a configuration in which two LSIs are connected by a duplex transmission path, it is not possible to maintain only the system in which the fault has occurred. For this reason, after the switching occurs, there is a problem that the duplexing function is stopped and the reliability is lowered. In addition, there is a problem that a request delay due to retransmission occurs even when the retransmission method is used in order to eliminate a decrease in reliability due to a function stop.

  Patent Document 1 “Uninterruptible Path Switching System and Control Method” stores a transmission frame in a buffer memory during a path switching process from when a path alarm is detected until the path switching selector operates properly. is doing. For this reason, a delay of a certain time occurs, but it is difficult to maintain the “continuity of control”.

The “digital signal transmission apparatus” of Patent Document 2 uses the BIP-8 method, and detects a code error in comparison with the next frame in order to perform error determination of a target frame. Therefore, the error determination cannot be performed until the next frame is transmitted. In addition, since it is necessary to temporarily store data in the frame memory for path switching, a delay of one frame is generated in addition to the delay of performing phase synchronization, and the above “continuity of control” is maintained. Have difficulty.
JP 2000-327771 A JP 07-177116 A

  In view of the above circumstances, the present invention provides a data error correction apparatus capable of eliminating delay caused by path switching at the time of error detection, ensuring control continuity, ensuring reliability, and improving performance in a redundant transmission line system. The purpose is to provide.

  An aspect of the present invention that achieves the above object is to provide data reception error detection means for detecting data errors by dividing data transmitted from transmission lines of each system into predetermined units, and synchronizing the data. Duplex transmission line system having error correction means for discarding data containing errors among the two system synchronization means to be performed and the data classified for each unit of one system, and selecting normal data of the other system, The present invention relates to a data error correction apparatus that corrects errors in data transmitted by the mobile phone.

  If the special code that is the starting point of the synchronization is an error in the data, the data transmission path is blocked until a normal special code is detected.

  The data reception error detection means may perform CRC detection. Moreover, it is good to connect to the transmission path of each said system via a crossbar switch.

  Another aspect of the present invention is a data reception error detection step of detecting data errors by dividing data transmitted from transmission lines of each system into predetermined units, and two systems for performing synchronization between the data It has a synchronization process and an error correction process that discards data that contains errors among the data divided into units of one system and selects normal data of the other system, and transmits it in a redundant transmission line system. The present invention relates to a data error correction method for correcting an error in data to be processed.

  If the data reception error detection step detects an error in the special code that is the starting point of the synchronization among the data, the data until the normal special code is detected in the two-system synchronization step. Block the transmission line.

  CRC detection is preferably performed in the data reception error detection step.

  Since the data error correction device of the present invention detects an error before performing synchronization in each system, error determination is determined at the time of synchronization waiting, and the transmission path can be switched immediately after synchronization. It becomes. Therefore, the delay that occurs is only a waiting time due to synchronization, and in a redundant transmission line system, the delay due to path switching at the time of error detection is eliminated, ensuring control continuity, ensuring reliability, and improving performance. be able to.

  The best mode for carrying out the data error correction apparatus of the present invention will be described below. In the description, the drawings submitted at the same time as this specification will be taken into consideration as appropriate.

<Constitution>
FIG. 1 is a block diagram illustrating the configuration of a redundant transmission line system equipped with a data error correction apparatus of this embodiment. Referring to FIG. 1, data is transferred from the first LSI 100 that is the starting point of data transfer, two data transfer paths A and B that are data transfer paths from the first LSI 100, and the data transfer paths A and B. The second LSI 200 is the end point of the data. A system in which data is transferred through the data transfer path A is referred to as “A system”, and a system in which data is transferred through the data transfer path B is referred to as “B system”.

  The first LSI 100 has an internal logic unit 101 for instructing the processing content of one data, and data duplication in which one data is duplexed according to an instruction from the internal logic unit 101 and the data is transmitted to two data transfer paths A and B. The transmission unit 102 is configured.

  The second LSI 200 performs reception processing of each of the data of the A system and the B system transferred from the data duplex transmission unit 102, detects an error of each received data, and a two-system synchronization unit together with the error information Data reception error detection units 201 and 211 that send data to 220, and two systems that receive error information and data detected by the respective data reception error detection units 201 and 211, and synchronize the duplexed A system and B system Synchronizing unit 220 receives synchronized data of system A and system B and error information, and performs error determination on the data of system A and system B based on the error information and correction of data from the error determination. And an error correction unit 230 for sending normal data to the internal logic unit 240 and an internal logic unit 240 for instructing the processing content of the sent data. That.

  The two-system synchronization unit 220 that synchronizes the A-system and the B-system receives the data and error information from the data reception error detection units 201 and 211, and performs synchronization in accordance with an instruction from the two-system synchronization control unit 221. Two-system synchronization control unit for detecting serial transfer special code in units 202 and 212 and A-system and B-system synchronization units 202 and 212 and issuing a wait instruction for synchronization using the special code as a starting point 221.

  The data waiting performed by the synchronization units 202 and 212 means that when the error information detected by the data reception error detection units 201 and 211 is a special code for serial transfer, the data is waited until the synchronization time expires and the synchronization is performed. When the time has expired, data waiting is temporarily stopped, error information is continuously sent to the error correction unit 230, the synchronization function is blocked, and a normal special code is again received from the data reception error detection units 201 and 211. It is to meet again when it arrives. The synchronization units 202 and 212 have such a recovery function.

  An error correction unit 230 that performs error correction from the data of the A system and the B system synchronized by the two-system synchronization unit 220 receives data from the synchronization units 202 and 212 and compares the data with other system data. The data reception registers 203 and 213, error registers 204 and 214 for storing the error information of the data, and error data are determined from the error information. If the error information is lit in either the A system or the B system If there is, an error determination / correction control unit 231 that selectively outputs data of a system in which no error is lit to the internal logic unit 240 is configured. In the error correction unit 230, even in the case where there is no error information in the error registers 204 and 214 in preparation for a failure in which the data reception error detection units 201 and 211 cannot detect an error, the data reception registers 203 and 213 The stored data are compared, and if they match, the A-system data is output to the internal logic unit 240. If they do not match, the data transfer is blocked as an uncorrectable error, thereby causing an error to the internal logic unit 240. It also has a function to prevent data transmission.

<Operation>
Next, the operation of the data error correction apparatus of this embodiment will be described with reference to FIGS. FIGS. 2 and 3 are diagrams illustrating a flow in which the transmission data duplexed by the data duplexing transmission unit 102 of the first LSI 100 detects a failure during transfer in the second LSI 200 and corrects the error. The error detection in the data reception error detection units 201 and 211 includes error detection when converting from serial transfer to parallel transfer. Here, a case where CRC (Cyclic Redundancy Check) detection is employed will be described as an example.

  When data transfer as shown in the figure is performed from the data duplex transmission unit 102 of the first LSI 100, the data reception error detection units 201 and 211 of the second LSI 200 have the respective systems. Independently detects errors in received data. Although CRC detection is also performed here, the unit of CRC detection is related to the detection time of the two-system synchronization unit 220 and the error correction unit 230, so here the interface specification is to add CRC in units of 5 words. In CRC detection, the data duplex transmission unit 102 of the first LSI 100 uses a CRC code (hereinafter referred to as “K code”), which is a special code on serial data, as a starting point for every 5 words. CR is equivalent). Then, the data reception error detection units 201 and 211 of the second LSI 200 perform a CRC check in units of 5 words after receiving the K code. If an error is detected by the data reception error detectors 201 and 211, as shown in “(1) Error detection” in FIG. The data is sent to the system synchronization unit 200. Note that the code marked “D?” In FIG. 2 is an error target detected by error detection.

  Next, the error flag and the received data added by the data reception error detection units 201 and 211 are synchronized between the data of the A system and the B system by the two-system synchronization unit 220. The data sent from the data reception error detection units 201 and 211 is sent to the synchronization units 202 and 212 together with the error flag, and the synchronization units 202 and 212 are connected to the other system data according to an instruction from the two-system synchronization control unit 220. Wait for The two-system synchronization control unit 220 identifies the K code from the data sent from the data reception error detection units 201 and 211, and performs alignment determination of the K code in the A system and the B system. If the K codes are aligned, the synchronized data of the A system and the B system is sent to the error correction unit 230 as shown in “(2) Synchronization” of FIG.

  In this two-system synchronization control unit 220, for example, the K code that is the starting point of synchronization detects an error in one system and cannot be recognized as a normal K code (in the code marked “K?” In FIG. 3). Equivalent)), a certain synchronization time is provided. If the K code cannot be recognized after waiting for the synchronization time, the synchronization wait is canceled and data is sent to the error correction unit 230. At this time, the system in which the synchronization has failed is always determined to be in an error state, an error flag “x” is added to all data, and the data is transmitted to the error correction unit 230. The two-system synchronization control unit 221 temporarily closes the paths of the synchronization units 202 and 212 in the system in which synchronization has failed. When the synchronization units 202 and 212 are closed once and then receive a normal K code, the synchronization units 202 and 212 perform automatic recovery of the synchronization path and start synchronization again ("(2) synchronization" in FIG. 3). Refer to "

  The data synchronized from the two-system synchronization unit 220 is stored in the data reception registers 203 and 213 of the error correction unit 230, and the error flag added to the data is stored in the error flag registers 204 and 214. The error information stored in the error flag registers 204 and 214 is transferred to the error determination / correction control unit 231. The error determination / correction control unit 231 performs error determination on the data of each system. At this time, the unit for performing the error determination is the CRC detection defined in the interface specification in units of 5 words. Therefore, the error determination is performed in units of 6 words including the CRC code (data code 5 words + CRC code 1 word). The

  If the error flag is lit on any of the 6-word data, the 6-word data is determined to be error data. At this time, since the error data is determined by 6 words, the data reception registers 203 and 213 and the error flag registers 204 and 214 for storing data sent from the synchronization units 202 and 212 become registers for 6 words. Data in the system determined as error data in the error determination / correction control unit 231 is invalidated and discarded in the error determination / correction control unit 231. As shown in “(3) Correction” in FIG. (B system data here) is selected and error correction is performed. Then, as shown in “Selected output of (4)”, normal data is output to the internal logic unit 240.

  By performing the above operation, the following effects can be obtained. That is, since error determination is performed before synchronization in each system, error determination is established at the time of synchronization waiting, and path switching immediately after synchronization is possible. Therefore, the delay that occurs is only the waiting time for synchronization. In addition, by detecting a failure that occurred in each data transfer path and correcting the error in a pipelined manner based on the failure information, it is possible to eliminate the request delay due to retransmission as in the retransmission method after error detection. . In addition, since the switching operation that is necessary when a failure occurs, such as dual path switching, can be eliminated, continuity of control can be ensured, reliability can be ensured, and performance can be improved.

  In addition, although the form mentioned above is the best thing for implementing this invention, it is not the meaning limited to this. Therefore, various modifications can be made to the implementation form without changing the gist of the present invention.

  One example will be described with reference to FIG. FIG. 4 is a block diagram illustrating the configuration of a redundant transmission line system equipped with a data error correction device of another form. The difference from that shown in FIG. 1 is that the first LSI 100 and the second LSI 200 are connected to the A system and the B system via the crossbars SW (switches) 300 and 310, respectively. In the configuration via the crossbar SW 300, 310, the synchronization waiting time controlled by the synchronization unit 220 of the second LSI 200 is set in consideration of the time difference between the A system and the B system by the crossbar SW 300, 310. Error correction is possible.

It is the block diagram which illustrated the structure of the transmission-line duplex system which mounts the data error correction apparatus of this form. FIG. 5 is a diagram illustrating a flow in which transmission data duplexed by the data duplexing transmission unit 102 of the first LSI 100 detects a failure during transfer and corrects an error in the second LSI 200. FIG. 5 is a diagram illustrating a flow in which transmission data duplexed by the data duplexing transmission unit 102 of the first LSI 100 detects a failure during transfer and corrects an error in the second LSI 200. It is the block diagram which illustrated the structure of the transmission-line duplex system which mounts the data error correction apparatus of another form. It is the block diagram which illustrated the structure of the data error correction apparatus used for the conventional redundant transmission line system.

Explanation of symbols

100 First LSI
101 Internal logic unit 102 Data duplex transmission unit 200 Second LSI
201, 211 Data reception error detection unit 220 Two-line synchronization unit 202, 212 Synchronization unit 221 Two-line synchronization control unit 230 Error correction unit 203, 213 Data reception register 204, 214 Error register 231 Error determination / correction control unit 240 Internal logic part

Claims (7)

Data reception error detecting means for detecting data errors by dividing data transmitted from the transmission path of each system into predetermined units;
Two-system synchronization means for performing synchronization between the data;
An error correction means for discarding data including errors among the data divided for each unit of one system and selecting normal data of the other system,
A data error correction device for correcting errors in data transmitted in a redundant transmission line system.   2. The data error correction according to claim 1, wherein when a special code serving as a starting point of synchronization is an error in the data, the data transmission path is blocked until a normal special code is detected. apparatus.   The data error correction apparatus according to claim 1 or 2, wherein the data reception error detection means performs CRC detection.   4. The data error correction device according to claim 1, wherein the data error correction device is connected to a transmission path of each system via a crossbar switch. A data reception error detection step of dividing data transmitted from the transmission path of each system into predetermined units and detecting an error in the data;
A two-system synchronization step for synchronizing the data;
An error correction step of discarding data including errors among the data divided for each unit of one system and selecting normal data of the other system,
A data error correction method for correcting errors in data transmitted in a redundant transmission line system.   In the data reception error detection step, when an error of the special code serving as the starting point of the synchronization is detected in the data, the data is transmitted until a normal special code is detected in the two-system synchronization step. 6. The data error correction method according to claim 5, wherein the path is blocked.   7. The data error correction method according to claim 5, wherein CRC detection is performed in the data reception error detection step.

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