JP2007096006A - Method of manufacturing guard ring and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily change the designing conditions of a guard ring, such as the width of guard ring, depth of guard ring, density profile of guard ring and the like, through a simple method. <P>SOLUTION: At least two sets of apertures for forming the guard rings 6-1, 6-2, ..., 6-8 are formed in an oxide film 6 on the upper surface of an n<SP>-</SP>-epitaxial layer 5 so as to be partitioned; then, p-type impurities introduced through the aperture 6-1 for forming guard ring, and the p-type impurities introduced through the aperture 6-2 for forming guard ring, are diffused so as to form a second conduction type diffused region as one set of guard ring 7. In the guard ring, the p-type impurities introduced through the aperture 6-1 for forming guard ring, and the p-type impurities introduced through the aperture 6-2 for forming guard ring, are integrated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a manufacturing method of a guard ring and a semiconductor device including the guard ring manufactured by the manufacturing method, and in particular, a guard such as a guard ring width, depth, curvature, and guard ring concentration profile. The present invention relates to a guard ring manufacturing method and a semiconductor device in which the design conditions of the ring can be easily changed by a simple method.

  Furthermore, the present invention relates to a semiconductor device in which a guard ring is formed. In particular, the reverse voltage blocking characteristic can be improved, and the possibility that the electric field strength locally increases in the semiconductor device when a reverse bias is applied is reduced. The present invention relates to a semiconductor device that can be used.

  Specifically, the present invention relates to a semiconductor device such as a diode including a guard ring that can reduce a forward voltage drop, improve a reverse voltage blocking characteristic, and shorten a reverse recovery time.

  Conventionally, it is known to form a guard ring in a semiconductor device in order to relieve an electric field around an active area (active region) when a reverse bias is applied. For example, in a conventional semiconductor device described in Japanese Patent Laid-Open No. 9-237905, an annular guard ring forming opening is formed in an oxide film mask in order to form a guard ring by implanting boron as an impurity. Has been.

8 to 10 are views for explaining a manufacturing process of a conventional semiconductor device. Specifically, FIG. 8 is a diagram corresponding to FIG. 12 of Japanese Patent Laid-Open No. 9-237905, FIG. 9 is a diagram corresponding to FIG. 14 of Japanese Patent Laid-Open No. 9-237905, and FIG. 10 is Japanese Patent Laid-Open No. 9-237905. FIG. 16 is a diagram corresponding to FIG. 15. 8 to 10, 4 indicates an N ⁺ semiconductor substrate containing a high concentration impurity, and 5 indicates an N ⁻ epitaxial layer containing a low concentration impurity. Reference numeral 6 denotes an oxide film functioning as a mask, 6 'denotes a guard ring forming opening formed in the oxide film 6, and 7 denotes a guard ring.

In manufacturing a conventional semiconductor device described in Japanese Patent Laid-Open No. 9-237905, first, as shown in FIG. 8, an N ⁻ epitaxial layer 5 is grown on an N ⁺ semiconductor substrate 4. Next, the oxide film 6 is formed on the upper surface of the N ⁻ epitaxial layer 5 by heating in an oxidation furnace. Next, as shown in FIG. 9, a portion of the oxide film 6 where the guard ring 7 is to be formed is removed by selective etching using a photolithography technique to form a guard ring forming opening 6 ′. The Next, as shown in FIG. 10, deposition (deposition) and drive-in (push-in diffusion) of boron as a P-type impurity are performed through the guard ring forming opening 6 ', thereby reducing the breakdown voltage of the semiconductor device. A guard ring 7 for securing is formed.

FIG. 11 is a plan view of N ^- epitaxial layer 5 and guard ring 7 of the conventional semiconductor device shown in FIG. 10 viewed through oxide film 6 from above. As shown in FIG. 11, the guard ring 7 has a predetermined width W2 and is formed in an annular shape. That is, the width of the guard ring 7 at the same height as the surface (upper surface) of the N ⁻ epitaxial layer 5 is W2.

  FIG. 12 is an enlarged view of the guard ring 7 and the like of the conventional semiconductor device shown in FIG. As shown in FIG. 12, when the P-type impurity as a dopant introduced through the guard ring forming opening 6 ′ is diffused by 1 downward from the guard ring forming opening 6 ′, the guard ring forming opening 6 ′. 0.8 diffusing from the outer peripheral edge to the outer peripheral side (right side in FIG. 12) and from the inner peripheral side edge of the guard ring forming opening 6 ′ to the inner peripheral side (left side in FIG. 12), This is known as the diffusion theory of dopants.

That is, in a conventional semiconductor device as described in Japanese Patent Application Laid-Open No. 9-237905, boron of P-type impurity is deposited on the guard ring forming opening 6 ′ or the guard ring forming opening 6 Then, ions are implanted into the N ⁻ epitaxial layer 5 via “,” and then P-type impurity boron is pushed and diffused. As a result, the guard ring 7 is formed.

  Further, as described in, for example, paragraphs [0017] and [0025] of Japanese Patent Application Laid-Open No. 2005-183605, in manufacturing a conventional semiconductor device, a guard ring is formed by using one oxide film as a mask. And a P-type region in the active area (active region) are formed simultaneously.

Therefore, when manufacturing a conventional semiconductor device, not only based on the design condition of the guard ring, but also based on the design condition of the P-type region in the active area (active region), the guard ring is formed with the P-type impurity. The conditions for depositing on the opening for use, the conditions for ion-implanting P-type impurities into the N ⁻ epitaxial layer, and the conditions for injecting and diffusing the P-type impurities introduced into the N ⁻ epitaxial layer are determined.

In other words, in manufacturing a conventional semiconductor device, in order to change the design condition of the guard ring, the condition for depositing the P-type impurity on the guard ring forming opening, or the P-type impurity is added to the N ⁻ epitaxial layer. When the conditions for ion implantation into the semiconductor layer or the conditions for injecting and diffusing the P-type impurity introduced into the N ⁻ epitaxial layer are changed, the design conditions for the P-type region in the active area (active region) change accordingly. Resulting in.

  On the other hand, if the design condition of the guard ring is changed without changing the design condition of the P-type region in the active area (active region), the process of introducing the P-type impurity for the guard ring or the P-type for the guard ring The impurity diffusion process must be added and changed separately.

  For this reason, the design conditions of the guard ring cannot be easily changed during the manufacture of the conventional semiconductor device.

By the way, when the guard ring depth D is shallower than the optimum design guard ring depth, the outer and lower portions of the boundary surface between the guard ring 7 and the N ^- epitaxial layer 5 around it. The curvature of (the broken line portion in FIG. 13) becomes too large. FIG. 13 is a cross-sectional view of the semiconductor device showing a state where the depth D of the guard ring 7 is shallower than the depth of the guard ring under the optimum design conditions.

As shown in FIG. 13, when the depth D of the guard ring 7 is shallower than the depth of the guard ring under the optimum design condition, as described above, the boundary between the guard ring 7 and the surrounding N ^- epitaxial layer 5 is obtained. Of the surface, the curvature of the outer peripheral side and the lower part (broken line part in FIG. 13) becomes too large. As a result, when reverse bias is applied, the guard ring 7 and the surrounding N ⁻ epitaxial layer 5 In the boundary surface, the electric field strength locally increases at the outer peripheral side and the lower part (broken line part in FIG. 13), and the reverse voltage blocking characteristic is deteriorated.

  However, as described above, when a conventional semiconductor device is manufactured, if the guard ring 7 is optimized and the depth D of the guard ring 7 is increased, a P-type region (see FIG. Design conditions will change. For this reason, the depth D of the guard ring 7 cannot be easily increased at the time of manufacturing a conventional semiconductor device.

On the other hand, when the depth D of the guard ring 7 is deeper than the depth of the guard ring under the optimum design condition, the thickness t (see FIG. 14) of the N ⁻ epitaxial layer 5 below the guard ring 7 is reduced. Therefore, the depletion layer hits the N ⁺ semiconductor substrate 4 due to a low reverse voltage, and the electric field strength increases. FIG. 14 is a cross-sectional view of the semiconductor device showing a state where the depth D of the guard ring 7 is deeper than the depth of the guard ring under the optimum design conditions.

As shown in FIG. 14, when the depth D of the guard ring 7 is deeper than the depth of the guard ring under the optimum design condition, the thickness of the N ⁻ epitaxial layer 5 below the guard ring 7 as described above. Since t becomes thin, the depletion layer collides with the N ⁺ semiconductor substrate 4 by a low reverse voltage. When the applied voltage is further increased, the electric field strength exceeds the critical electric field and avalanche breakdown occurs, thereby hindering the high breakdown voltage of the semiconductor device.

In order to reduce the depth D of the guard ring 7 in order to reduce the curvature of the outer peripheral side and the lower side of the guard ring 7, the width of the guard ring forming opening of the mask must be increased. In this case, the total amount of P-type impurities diffused into the N ⁻ epitaxial layer 5 increases. As a result, carriers (holes) moving to the N ⁻ epitaxial layer 5 in the forward bias high current region increase, and the reverse recovery time becomes long.

  However, as described above, when a conventional semiconductor device is manufactured, if the guard ring 7 is optimized and the depth D of the guard ring 7 is reduced, a P-type region (see FIG. Design conditions will change. For this reason, the depth D of the guard ring 7 cannot be easily reduced at the time of manufacturing a conventional semiconductor device.

  That is, when manufacturing a conventional semiconductor device, for example, the width, depth, curvature, and guard ring concentration profile of the guard ring without adding or changing the P-type impurity introduction process or the P-type impurity diffusion process. The design conditions of the guard ring such as can not be easily changed.

Further, in the conventional semiconductor device as described in JP-A-9-237905, as shown in FIGS. 9 and 10, as a P-type impurity through one annular guard ring forming opening 6 ′. By injecting boron into the N ⁻ epitaxial layer 5, a guard ring 7 is formed. Therefore, as shown in FIG. 13, there is a portion having a large curvature in the outer peripheral side and the lower portion (broken line portion in FIG. 13) of the boundary surface between the guard ring 7 and the surrounding N ⁻ epitaxial layer 5. It always happens.

As a result, in the conventional semiconductor device in which the guard ring 7 is formed by one annular guard ring forming opening 6 ′, the boundary surface between the guard ring 7 and the surrounding N ⁻ epitaxial layer 5 is applied when a reverse bias is applied. Among them, the electric field strength locally increases at the outer peripheral side and the lower part (broken line part in FIG. 13), and the reverse voltage blocking characteristic is deteriorated. That is, carrier generation occurs locally, and the current density of the hole current flowing through the P-type region of the guard ring 7 increases, so that the semiconductor device may be destroyed.

JP-A-9-237905 JP-A-2005-183605

  In view of the above problems, the present invention provides a guard ring that can easily change guard ring design conditions such as guard ring width, depth, curvature, and guard ring concentration profile by a simple method. An object is to provide a manufacturing method and a semiconductor device.

  Furthermore, an object of the present invention is to provide a semiconductor device that can improve reverse voltage blocking characteristics and can reduce the possibility that the electric field strength locally increases in the semiconductor device when a reverse bias is applied. To do.

  According to the first aspect of the present invention, the first conductivity type semiconductor layer including the low concentration impurity is formed on the first conductivity type semiconductor substrate including the high concentration impurity, and the upper surface of the first conductivity type semiconductor layer is formed. A mask is formed, a guard ring formation opening is formed in the mask, a second conductivity type impurity is introduced into the first conductivity type semiconductor layer through the guard ring formation opening, and the second conductivity type is introduced. In a method for manufacturing a guard ring in which a second conductivity type diffusion region as a guard ring is formed by diffusing impurities in the first conductivity type semiconductor layer, at least two guard ring formation openings are divided in the mask. And a second conductivity type impurity introduced through one guard ring forming opening and a second introduced through another guard ring forming opening adjacent to the one guard ring forming opening. A second conductivity type impurity introduced through the one guard ring forming opening so as to form a second conductivity type diffusion region as one guard ring integrated with a conductivity type impurity; There is provided a method for manufacturing a guard ring, characterized by diffusing the second conductivity type impurity introduced through the opening for forming the guard ring.

  According to the invention described in claim 2, by using the mask, the guard ring and the second conductivity type diffusion region in the active region on the inner peripheral side of the guard ring are simultaneously formed. A method for manufacturing a guard ring according to claim 1 is provided.

  According to the third aspect of the present invention, the width of the guard ring forming opening on the guard ring outer peripheral side among the plurality of guard ring forming openings formed in a divided manner is used for guard ring forming on the guard ring inner peripheral side. The guard ring manufacturing method according to claim 1 or 2, wherein the width is narrower than the width of the opening.

  According to the fourth aspect of the present invention, the width of the mask portion between two adjacent guard ring forming openings on the outer periphery side of the guard ring among the at least three guard ring forming openings formed by division is set. The method for manufacturing a guard ring according to any one of claims 1 to 3, wherein the width of the mask portion between two adjacent guard ring forming openings on the inner side of the guard ring is wider. Provided.

  According to invention of Claim 5, the semiconductor device which comprises the guard ring manufactured by the manufacturing method of the guard ring as described in any one of Claims 1-4 is provided.

  According to a sixth aspect of the present invention, a first conductive type semiconductor layer containing a low concentration impurity is formed on a first conductive type semiconductor substrate containing a high concentration impurity, and the first conductive type semiconductor layer is formed in the first conductive type semiconductor layer. In the semiconductor device in which the guard ring is formed, the curvature of the guard ring outer peripheral side and the guard ring lower portion of the boundary surface between the guard ring and the first conductive type semiconductor layer around the guard ring is defined as the guard ring inner peripheral side. And the semiconductor device characterized by making it smaller than the curvature of the part below a guard ring is provided.

  In the guard ring manufacturing method according to the first and second aspects, at least two guard ring forming openings are divided and formed in the mask. That is, in the guard ring manufacturing method according to claim 1 and 2, at least two guard ring forming openings are formed in the mask in a divided manner, and one guard ring forming opening and the one guard ring forming opening are formed. A mask portion is left between another opening for forming a guard ring adjacent to the opening. As a result, the total area of the guard ring forming opening is reduced as compared with the case where only one guard ring forming opening is formed in the mask.

  Furthermore, in the guard ring manufacturing method according to claim 1 and 2, the second conductivity type impurity introduced into the first conductivity type semiconductor layer through one guard ring formation opening and the other guard ring formation. For forming one guard ring so as to form a second conductivity type diffusion region as one guard ring integrated with the second conductivity type impurity introduced into the first conductivity type semiconductor layer through the opening for use. The second conductivity type impurity introduced through the opening and the second conductivity type impurity introduced through the other guard ring forming opening are diffused.

  Preferably, in the method for manufacturing the guard ring according to claim 1 and 2, the guard ring and the second conductivity type diffusion region in the active region on the inner peripheral side of the guard ring are simultaneously formed by using one mask. It is formed.

  Therefore, according to the manufacturing method of the guard ring of Claim 1 and 2, the width | variety of a guard ring is made narrower than the case where one guard ring is formed with one guard ring formation opening formed in the mask. In addition, the depth of the guard ring can be reduced, the concentration of the guard ring can be reduced, and the total amount of the second conductivity type impurities can be reduced.

  That is, according to the method for manufacturing a guard ring according to claims 1 and 2, the guard formed on the mask without adding or changing the step of introducing the second conductivity type impurity or the step of diffusing the second conductivity type impurity. By a very simple method of changing the ring forming opening, it is possible to easily change the guard ring design conditions such as the guard ring width, depth, and guard ring concentration profile.

Specifically, for example, a conventional method for manufacturing a guard ring in which an opening for forming a guard ring is not divided and formed in a mask for an N ^- epitaxial layer as the first conductive type semiconductor layer having the same thickness and the same specific resistance. And a guard ring forming method according to claim 1 and 2, wherein the P-type guard ring region as the second conductivity type diffusion region is diffused and the guard ring forming opening is divided into masks. The case where the P-type guard ring region as the conductive diffusion region is diffused is compared.

In the case of the guard ring manufacturing method according to the first and second aspects, the depth of the guard ring is shallower than in the case of the conventional guard ring manufacturing method. Therefore, for the same reverse bias voltage, the distance until the depletion layer extending from the PN junction of the guard ring into the N ⁻ epitaxial layer hits the N ⁺ semiconductor substrate as the first conductivity type semiconductor substrate is increased. (The thickness t in FIG. 13 is thicker than the thickness t in FIG. 14.) Further, in the case of the guard ring manufacturing method according to claim 1 and 2, compared to the case of the conventional guard ring manufacturing method. The P-type concentration of the guard ring is lowered. For this reason, the distance extending from the PN junction of the guard ring into the P-type region of the guard ring becomes longer. Therefore, in the case of the guard ring manufacturing method according to the first and second aspects of the invention, the electric field can be relaxed with respect to the same reverse bias voltage as compared with the case of the conventional guard ring manufacturing method. The reverse voltage blocking characteristic can be improved.

More specifically, according to the method for manufacturing a guard ring according to claims 1 and 2, as described above, the guard ring can be reduced in depth. For example, the guard ring is reduced in depth. In addition to this, by reducing the thickness of the N ⁻ epitaxial layer as the first conductive type semiconductor layer, the forward voltage drop is reduced by reducing the drift resistance of the N ⁻ epitaxial layer while maintaining the reverse voltage blocking characteristic. Can be made.

More specifically, according to the method for manufacturing a guard ring according to claim 1 or 2, wherein the opening for forming the guard ring is divided into masks, the P-type impurity as the second conductivity type impurity of the guard ring. The total amount of can be reduced. Therefore, by reducing the total amount of P-type impurities, the injection of minority carriers (holes) into the N ⁻ epitaxial layer is reduced particularly in the forward bias high current region, and the reverse recovery time can be shortened.

  The guard ring manufacturing method according to claim 3, wherein among the plurality of guard ring forming openings formed in a divided manner, the width of the guard ring forming opening on the outer periphery side of the guard ring is the guard ring on the inner peripheral side of the guard ring. It is narrower than the width of the forming opening. Therefore, when the width of the guard ring forming opening on the outer peripheral side of the guard ring is made equal to the width of the guard ring forming opening on the inner peripheral side of the guard ring, or only one guard ring forming opening is formed in the mask. The curvature of the outer peripheral side of the guard ring and the lower side of the guard ring in the boundary surface between the second conductive type diffusion region as the guard ring and the surrounding first conductive type semiconductor layer is made smaller than the case where Can do.

  That is, according to the method for manufacturing a guard ring according to claim 3, the second conductivity type as the guard ring can be obtained by a very simple method of making the widths of the plurality of guard ring forming openings formed differently. The curvature of the boundary surface between the diffusion region and the surrounding first conductive type semiconductor layer can be easily changed.

  In the guard ring manufacturing method according to claim 4, the mask portion between the two adjacent guard ring forming openings on the outer periphery side of the guard ring among at least three guard ring forming openings formed by division. The width is made wider than the width of the mask portion between two adjacent guard ring forming openings on the guard ring inner peripheral side. Therefore, the width of the mask portion between two adjacent guard ring forming openings on the outer periphery side of the guard ring is made equal to the width of the mask portion between two adjacent guard ring forming openings on the inner periphery side of the guard ring. Or a boundary surface between the second conductive type diffusion region as a guard ring and the surrounding first conductive type semiconductor layer, rather than when only one guard ring forming opening is formed in the mask. The curvature of the guard ring outer peripheral side and the guard ring lower part can be reduced.

  That is, according to the method for manufacturing a guard ring according to claim 4, the width of the mask portion between two adjacent guard ring forming openings among at least three guard ring forming openings formed separately. The curvature of the boundary surface between the second conductivity type diffusion region as the guard ring and the surrounding first conductivity type semiconductor layer can be easily made by a very simple method of making the difference between the outer periphery side of the guard ring and the inner periphery side of the guard ring. Can be changed.

  According to the semiconductor device of the fifth aspect, the guard ring forming opening formed in the mask is changed without adding or changing the second conductivity type impurity introduction step or the second conductivity type impurity diffusion step. By such an extremely simple method, for example, the guard ring conditions such as the guard ring width, depth, curvature, and guard ring concentration profile can be easily changed.

  In the semiconductor device according to claim 6, the curvature of the guard ring outer peripheral side and the guard ring lower portion of the boundary surface between the guard ring and the surrounding first conductive type semiconductor layer is the guard ring inner peripheral side and It is smaller than the curvature of the lower part of the guard ring. Therefore, the reverse voltage blocking characteristics should be improved compared to the case where the curvature of the guard ring outer peripheral side and guard ring lower part is substantially equal to the curvature of the guard ring inner peripheral side and guard ring lower part. Can do.

  Specifically, according to the semiconductor device of the sixth aspect, the curvature of the guard ring outer peripheral side and the guard ring lower portion is substantially equal to the curvature of the guard ring inner peripheral side and the guard ring lower portion. As in the case where the reverse bias is applied, the possibility that the electric field strength locally increases in the semiconductor device when the reverse bias is applied can be reduced.

  Hereinafter, a first embodiment of a semiconductor device of the present invention will be described. FIG. 1 is a view showing an MPS (Merged pin / Schottky) as a semiconductor device of the first embodiment. More specifically, FIG. 1A shows a guard ring forming opening 6 ′ for forming a guard ring and a P type region forming opening 6 ″ for forming a P type region in an active area (active region). FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A, and FIG.

As shown in FIG. 1B, in the semiconductor device of the first embodiment, a low concentration impurity is formed on the N ⁺ semiconductor substrate 4 containing a high concentration impurity such as phosphorus P, arsenic As, or antimony Sb. An N ⁻ epitaxial layer 5 is formed. An oxide film 6 functioning as a mask is formed on the upper surface of the N ⁻ epitaxial layer 5. A guard ring forming opening 6 ′ for forming a guard ring 7 and a guard ring 7 are formed in the oxide film 6. A P-type region forming opening 6 ″ for forming a P-type region 7 ′ in the active area (active region) on the inner peripheral side (the left side in FIG. 1B) is formed.

Further, in the semiconductor device of the first embodiment, as shown in FIGS. 1A and 1B, the guard ring forming opening 6 ′ has, for example, eight annular guard ring forming openings 6-. It is divided into 1,6-2,6-3,6-4,6-5,6-6,6-7,6-8. Further, for example, a P-type impurity such as boron B opens the guard ring forming openings 6-1, 6-2, 6-3, 6-4, 6-5, 6-6, 6-7, 6-8. is introduced into the epitaxial layer 5, N ^{- -} N through is allowed diffused in the epitaxial layer within 5, as a result, one of the annular guard ring 7 is formed.

In the semiconductor device of the first embodiment, for example, P-type impurities are introduced into the N ⁻ epitaxial layer 5 by ion implantation, and then the P-type impurities are diffused in the N ⁻ epitaxial layer 5 by indentation diffusion. In the modification of the semiconductor device of the first embodiment, instead, the P-type impurity is introduced into the N ⁻ epitaxial layer 5 by another method, for example, by depositing the P-type impurity on the guard ring forming opening 6 ′. Then, it is also possible to diffuse P-type impurities in the N ⁻ epitaxial layer 5 by indentation diffusion.

Specifically, in the semiconductor device of the first embodiment, as shown in FIG. 1B, the P-type impurity introduced from the guard ring formation opening 6-1 and the guard ring formation opening 6-2 are used. The introduced P-type impurity is diffused and integrated in the N ⁻ epitaxial layer 5 to form a part of the guard ring 7. Further, the P-type impurity introduced from the guard ring formation opening 6-2 and the P-type impurity introduced from the guard ring formation opening 6-3 are diffused and integrated in the N ⁻ epitaxial layer 5. Thus, a part of the guard ring 7 is formed. Further, the P-type impurity introduced from the guard ring formation opening 6-3 and the P-type impurity introduced from the guard ring formation opening 6-4 are diffused and integrated in the N ⁻ epitaxial layer 5. Thus, a part of the guard ring 7 is formed.

Similarly, as shown in FIG. 1B, the P-type impurity introduced from the guard ring forming opening 6-4 and the P type impurity introduced from the guard ring forming opening 6-5 are N ⁻ A part of the guard ring 7 is formed by being diffused and integrated in the epitaxial layer 5. Further, the P-type impurity introduced from the guard ring formation opening 6-5 and the P-type impurity introduced from the guard ring formation opening 6-6 are diffused and integrated in the N ⁻ epitaxial layer 5. Thus, a part of the guard ring 7 is formed. Further, the P-type impurity introduced from the guard ring formation opening 6-6 and the P-type impurity introduced from the guard ring formation opening 6-7 are diffused and integrated in the N ⁻ epitaxial layer 5. Thus, a part of the guard ring 7 is formed. Further, the P-type impurity introduced from the guard ring formation opening 6-7 and the P-type impurity introduced from the guard ring formation opening 6-8 are diffused and integrated in the N ⁻ epitaxial layer 5. Thus, a part of the guard ring 7 is formed.

Further, as shown in FIG. 1B, the P-type impurity introduced from the P-type region forming opening 6 ″ is diffused in the N ⁻ epitaxial layer 5 to form the P-type in the active area (active region). Region 7 'is formed.

More specifically, in the semiconductor device of the first embodiment, the guard ring 7 and the active area (active region) are formed by introducing a P-type impurity into the N ⁻ epitaxial layer 5 and diffusing it in the N ⁻ epitaxial layer 5. An inner P-type region 7 'is formed at the same time. More specifically, ion implantation conditions for introducing a P-type impurity into the N ⁻ epitaxial layer 5 are set to, for example, a dose of 1 × 10 ¹⁴ to 10 ¹⁵ ions / cm ² and an acceleration voltage of several tens keV. Further, as shown in FIG. 1B, guard ring forming openings 6-1, 6-2, 6-3, 6-4, 6-5, 6-6, 6-7, 6-8 are provided, for example. They are arranged at a pitch of about 1 to 2 μm.

  In the semiconductor device of the first embodiment, as shown in FIG. 1A, P-type region formation for forming a P-type region 7 ′ (see FIG. 1B) in an active area (active region) is performed. The opening 6 ″ for forming the stripe is formed in a stripe shape, but in another modification of the semiconductor device of the first embodiment, the opening 6 ″ for forming the P-type region is replaced with another arbitrary shape such as a dot shape instead. It is also possible to form in the shape.

FIG. 2 is a diagram for explaining a state in which P-type impurities are introduced into the N ⁻ epitaxial layer 5, and FIG. 3 is a diagram for explaining a state in which P-type impurities are diffused in the N ⁻ epitaxial layer 5. is there. Specifically, FIGS. 2A and 3A show a plurality of guard ring forming openings 6 ′ (6-1, 6-2, and the like as in the semiconductor device of the first embodiment shown in FIG. 6-3, 6-4) shows a case where one guard ring 7 is formed by P-type impurities introduced from FIG. 6, and FIG. 2B and FIG. 3B show the prior art shown in FIG. This shows a case where one guard ring 7 is formed by P-type impurities introduced from one guard ring forming opening 6 'as in a semiconductor device.

When the ion implantation conditions such as implantation energy and dose are set to be the same in the semiconductor device shown in FIG. 2A and the semiconductor device shown in FIG. As described above, in the semiconductor device in which the guard ring forming opening 6 ′ (6-1, 6-2, 6-3, 6-4) is divided into a plurality of parts, the ion-implanted boron B, for example, Such dopant atoms 7 ″ are spaced apart from each other and distributed in the N ⁻ epitaxial layer 5. On the other hand, as shown in FIG. 2B, in the semiconductor device in which the guard ring forming opening 6 ′ is not divided, The ion-implanted dopant atoms 7 ″ such as boron B are distributed in the N ⁻ epitaxial layer 5 continuously in the horizontal direction.

  Next, in the semiconductor device shown in FIG. 2A and FIG. 3A, a part of the dopant atoms 7 ″ introduced from the guard ring forming opening 6-1 and the guard ring forming opening 6-2 are introduced. A part of the dopant atom 7 ″ is horizontally applied to the lower side of the mask portion between the guard ring forming opening 6-1 and the guard ring forming opening 6-2 (left and right direction in FIG. 2A). To spread. Therefore, the dopant atoms 7 "introduced from the guard ring formation opening 6-1 and the dopant atoms 7" introduced from the guard ring formation opening 6-2 are diffused downward (lower side in FIG. 2A). The speed of performing is lower than when the mask portion is not disposed between the guard ring forming opening 6-1 and the guard ring forming opening 6-2.

  Further, as shown in FIGS. 2A and 3A, a part of the dopant atoms 7 ″ introduced from the guard ring forming opening 6-2 and the guard ring forming opening 6-3 were introduced. A part of the dopant atom 7 ″ diffuses in the horizontal direction (left and right direction in FIG. 2A) below the mask portion between the guard ring formation opening 6-2 and the guard ring formation opening 6-3. To do. Therefore, the dopant atoms 7 ″ introduced from the guard ring formation opening 6-2 and the dopant atoms 7 ″ introduced from the guard ring formation opening 6-3 are diffused downward (lower side in FIG. 2A). The speed of performing is lower than when no mask portion is disposed between the guard ring forming opening 6-2 and the guard ring forming opening 6-3.

  Further, as shown in FIGS. 2A and 3A, a part of the dopant atoms 7 ″ introduced from the guard ring forming opening 6-3 and the guard ring forming opening 6-4 were introduced. A part of the dopant atom 7 ″ diffuses in the horizontal direction (left and right direction in FIG. 2A) below the mask portion between the guard ring formation opening 6-3 and the guard ring formation opening 6-4. To do. Therefore, the dopant atoms 7 "introduced from the guard ring formation opening 6-3 and the dopant atoms 7" introduced from the guard ring formation opening 6-4 are diffused downward (lower side in FIG. 2A). The speed is lower than when the mask portion is not disposed between the guard ring forming opening 6-3 and the guard ring forming opening 6-4.

  As a result, the width W of the guard ring forming opening 6 ′ of the semiconductor device shown in FIGS. 2A and 3A and the guard ring forming of the semiconductor device shown in FIGS. 2B and 3B are obtained. Even when the width W of the opening 6 ′ is equal, the width W1 of the guard ring 7 of the semiconductor device shown in FIG. 3A is larger than the width W2 of the guard ring 7 of the semiconductor device shown in FIG. Narrow. Further, the depth D1 of the guard ring 7 of the semiconductor device shown in FIG. 3A is shallower than the depth D2 of the guard ring 7 of the semiconductor device shown in FIG.

  In the semiconductor device shown in FIGS. 2A and 3A, the guard ring forming opening 6-2 and the guard ring are formed between the guard ring forming opening 6-1 and the guard ring forming opening 6-2. Since the mask portions remain between the ring forming opening 6-3 and between the guard ring forming opening 6-3 and the guard ring forming opening 6-4, FIG. The total area of the guard ring forming opening 6 ′ of the semiconductor device shown in A) is smaller than the total area of the guard ring forming opening 6 ′ of the semiconductor device shown in FIGS. 2B and 3B. As a result, the total amount of P-type impurities introduced from the guard ring formation opening 6 ′ of the semiconductor device shown in FIGS. 2A and 3A is shown in FIGS. 2B and 3B. This is less than the total amount of P-type impurities introduced from the guard ring forming opening 6 ′ of the semiconductor device. Therefore, the P-type impurity indentation diffusion condition in the semiconductor device shown in FIGS. 2A and 3A and the P-type impurity indentation diffusion in the semiconductor device shown in FIGS. 2B and 3B are shown. When the conditions are set to be the same, the P-type impurity concentration of the guard ring 7 of the semiconductor device shown in FIGS. 2A and 3A is the same as that shown in FIGS. 2B and 3B. It becomes lower than the P-type impurity concentration of the guard ring 7 of the apparatus.

  In other words, in the semiconductor device of the first embodiment shown in FIG. 1, for example, eight guard ring forming openings 6 ′ (6-1, 6-2, 6-3) are formed in the oxide film 6 as a mask. 6-4, 6-5, 6-6, 6-7, 6-8), and the guard ring is formed between the guard ring forming opening 6-1 and the guard ring forming opening 6-2. Between the formation opening 6-2 and the guard ring formation opening 6-3, between the guard ring formation opening 6-3 and the guard ring formation opening 6-4, and between the guard ring formation opening 6-4 and the guard. Between the ring forming opening 6-5, between the guard ring forming opening 6-5 and the guard ring forming opening 6-6, and between the guard ring forming opening 6-6 and the guard ring forming opening 6-7. And the guard ring forming opening 6-7 and the guard ring forming opening 6-8. Mask portion is left between.

  Therefore, the total area of the guard ring forming opening 6 ′ is larger than that in the case where only one guard ring forming opening 6 ′ is formed in the oxide film 6 as a mask as in the conventional semiconductor device shown in FIG. Is reduced. Therefore, according to the semiconductor device of the first embodiment, the width of the guard ring 7 is made narrower than when only one guard ring forming opening 6 ′ is formed in the oxide film 6 as a mask. The depth of the guard ring 7 can be reduced, the concentration of the guard ring 7 can be lowered, and the total amount of P-type impurities can be reduced.

Further, in the semiconductor device of the first embodiment shown in FIG. 1, the P-type impurity introduced into the N ⁻ epitaxial layer 5 through the guard ring formation opening 6-1 and the guard ring formation opening 6−. P-type impurities introduced into the N ⁻ epitaxial layer 5 through 2, P-type impurities introduced into the N ⁻ epitaxial layer 5 through the guard ring forming opening 6-3, and guard ring forming openings P-type impurities introduced into the N ⁻ epitaxial layer 5 through 6-4, P-type impurities introduced into the N ⁻ epitaxial layer 5 through the guard ring formation opening 6-5, and guard ring formation P-type impurities introduced into the N ⁻ epitaxial layer 5 through the openings 6-6 for use, P-type impurities introduced into the N ⁻ epitaxial layer 5 through the openings 6-7 for forming the guard ring, P-type impurities introduced into the N ⁻ epitaxial layer 5 through the trench forming openings 6-8 are diffused so as to form one integrated guard ring 7.

  That is, according to the semiconductor device of the first embodiment shown in FIG. 1, for example, P-type impurity ion implantation conditions such as implantation energy and dose, or P such as heat treatment temperature and heat treatment time. For example, the width of the guard ring 7 and the width of the guard ring 7 are changed by a very simple method of changing the guard ring forming opening 6 ′ formed in the oxide film 6 as a mask without changing the indentation diffusion condition of the type impurity. Guard ring design conditions such as depth and guard ring 7 concentration profile can be easily changed.

  Hereinafter, a second embodiment of the semiconductor device of the present invention will be described. The semiconductor device of the second embodiment is configured in the same manner as the semiconductor device of the first embodiment described above, except for the points described below. Therefore, according to the semiconductor device of the second embodiment, the same effects as those of the semiconductor device of the first embodiment described above can be obtained except for the points described later.

FIG. 4 is an enlarged view of a part of the MPS as the semiconductor device of the second embodiment. Specifically, FIG. 4 is a view showing the upper surface of oxide film 6 as a mask and the cross sections of oxide film 6, guard ring 7 and N ⁻ epitaxial layer 5. FIG. 5 is a cross-sectional view of an MPS as a semiconductor device of the second embodiment.

  In the semiconductor device of the first embodiment, as shown in FIG. 1B, eight annular guard ring forming openings 6-1, 6-2, 6-3, 6-4, and 6 having the same width. −5, 6-6, 6-7, 6-8 are arranged at equal intervals. In the semiconductor device of the second embodiment, as shown in FIG. The width W6-1 of 6-1 is made wider than the width W6-2 of the second guard ring forming opening 6-2 from the inner peripheral side. Further, the width W6-2 of the second guard ring forming opening 6-2 from the inner peripheral side is made wider than the width W6-3 of the third guard ring forming opening 6-3 from the inner peripheral side. Furthermore, the width W6-3 of the third guard ring forming opening 6-3 from the inner peripheral side is made wider than the width W6-4 of the guard ring forming opening 6-4 on the outermost peripheral side.

  Furthermore, in the semiconductor device of the second embodiment, as shown in FIG. 4, the innermost guard ring forming opening 6-1 and the second guard ring forming opening 6-2 from the inner peripheral side are provided. The width W12 of the mask portion between them is from the width W23 of the mask portion between the second guard ring forming opening 6-2 from the inner peripheral side and the third guard ring forming opening 6-3 from the inner peripheral side. Narrowed. Further, the width W23 of the mask portion between the second guard ring forming opening 6-2 from the inner peripheral side and the third guard ring forming opening 6-3 from the inner peripheral side is the third from the inner peripheral side. The width W34 of the mask portion between the guard ring forming opening 6-3 and the outermost guard ring forming opening 6-4 is made narrower.

As a result, in the semiconductor device of the second embodiment, as shown in FIGS. 4 and 5, the outer peripheral side and lower part of the PN junction surface between the guard ring 7 and the N ⁻ epitaxial layer 5 around the guard ring 7. The guard ring 7 is formed so that the curvature of is smaller than the curvature of the inner peripheral side and the lower part, that is, linear. That is, the depth of the inner ring side portion of the guard ring 7 becomes sharply shallower toward the inner ring side, whereas the depth of the outer ring side portion of the guard ring 7 is gradually decreased toward the outer ring side. The guard ring 7 is formed so as to be shallow.

Therefore, according to the semiconductor device of the second embodiment, the curvature of the outer peripheral side and the lower portion of the PN junction surface between the guard ring 7 and the surrounding N ⁻ epitaxial layer 5, the inner peripheral side and the lower The reverse voltage blocking characteristic can be improved as compared with the case where the curvature of the side portion is substantially equal.

Specifically, according to the semiconductor device of the second embodiment, the curvature of the outer peripheral side and the lower part of the PN junction surface between the guard ring 7 and the surrounding N ⁻ epitaxial layer 5, and the inner peripheral side In addition, as in the case where the curvature of the lower portion is substantially equal, the possibility that the electric field strength locally increases in the semiconductor device when the reverse bias is applied can be reduced.

In the semiconductor device of the second embodiment shown in FIGS. 4 and 5, the curvature of the inner peripheral side and the lower part of the PN junction surface between the guard ring 7 and the N ⁻ epitaxial layer 5 around the guard ring 7 is low. Although relatively large, a depletion layer extending from the PN junction of the guard ring 7 (the PN junction surface between the guard ring 7 and the surrounding N ⁻ epitaxial layer 5) into the N ⁻ epitaxial layer 5, and an active area (active region) The depletion layer extending into the N ⁻ epitaxial layer 5 from the PN junction of the P type region 7 ′ (the PN junction surface between the P type region 7 ′ and the surrounding N ⁻ epitaxial layer 5) is pinched off, and the electric field Therefore, the electric field strength does not increase.

  Further, in the semiconductor device of the second embodiment shown in FIGS. 4 and 5, for example, four guard ring forming openings 6 ′ (6-1, 6-2, 6-3, etc.) are formed in the oxide film 6 as a mask. 6-4) is divided and formed between the guard ring forming opening 6-1 and the guard ring forming opening 6-2, and between the guard ring forming opening 6-2 and the guard ring forming opening 6-3. And between the guard ring forming opening 6-3 and the guard ring forming opening 6-4.

  Therefore, as compared with the case where only one guard ring forming opening 6 ′ is formed in the oxide film 6 as a mask as in the conventional semiconductor device shown in FIG. 10, the guard ring forming opening 6 ′ (6- 1,6-2,6-3,6-4) is reduced. Therefore, according to the semiconductor device of the second embodiment, the width of the guard ring 7 is made narrower than when only one guard ring forming opening 6 ′ is formed in the oxide film 6 as a mask, The depth of the guard ring 7 can be reduced, the concentration of the guard ring 7 can be lowered, and the total amount of P-type impurities can be reduced.

In the semiconductor device of the second embodiment shown in FIGS. 4 and 5, the P-type impurity introduced into the N ⁻ epitaxial layer 5 through the guard ring formation opening 6-1 and the guard ring formation opening are provided. P-type impurities introduced into the N ⁻ epitaxial layer 5 through 6-2, P-type impurities introduced into the N ⁻ epitaxial layer 5 through the guard ring formation opening 6-3, and guard ring formation The P-type impurity introduced into the N ⁻ epitaxial layer 5 through the opening 6-4 is diffused so as to form one integrated guard ring 7.

  That is, according to the semiconductor device of the second embodiment shown in FIGS. 4 and 5, for example, ion implantation conditions of a P-type impurity such as a dose amount and an acceleration voltage, or a heat treatment temperature, a heat treatment time, etc. The guard ring forming opening 6 '(6-1, 6-2, 6-3, 6-4) formed in the oxide film 6 as a mask is changed without changing the conditions for indentation diffusion of a p-type impurity. The design conditions of the guard ring such as, for example, the width, depth, curvature, and concentration profile of the guard ring 7 can be easily changed.

  Hereinafter, a third embodiment of the semiconductor device of the present invention will be described. The semiconductor device of the third embodiment is configured in the same manner as the semiconductor device of the second embodiment described above, except for the points described below. Therefore, according to the semiconductor device of the third embodiment, the same effects as those of the semiconductor device of the second embodiment described above can be obtained except for the points described later.

FIG. 6 is an enlarged view of a part of the MPS as the semiconductor device of the third embodiment. Specifically, FIG. 6 is a diagram showing the upper surface of oxide film 6 as a mask and the cross sections of oxide film 6, guard ring 7 and N ⁻ epitaxial layer 5. The cross-sectional view of the MPS as the semiconductor device of the third embodiment is substantially the same as the cross-sectional view of the MPS as the semiconductor device of the second embodiment shown in FIG.

  In the semiconductor device of the second embodiment, as shown in FIG. 4, the third guard ring forming opening 6-3 from the inner peripheral side is formed annularly and continuously, and the outermost guard ring forming opening is formed. Although the opening 6-4 is annularly and continuously formed, in the semiconductor device of the third embodiment, as shown in FIG. 6, the third guard ring forming opening 6-3 from the inner peripheral side is For example, a plurality of holes having an arbitrary shape such as a rectangular shape, a polygonal shape, a circular shape, etc. arranged in an annular shape are formed intermittently, and the outermost guard ring forming openings 6-4 are arranged in an annular shape, for example, a rectangular shape. It is constituted intermittently by a plurality of holes having an arbitrary shape such as a polygon or a circle.

  In the semiconductor device of the third embodiment, as shown in FIG. 6, the width W6-1 of the guard ring forming opening 6-1 on the innermost side is the second guard ring forming opening 6 from the inner peripheral side. -2 width W6-2. Further, the width W6-2 of the second guard ring forming opening 6-2 from the inner peripheral side is made wider than the width W6-3 of the third guard ring forming opening 6-3 from the inner peripheral side. Furthermore, the width W6-3 of the third guard ring forming opening 6-3 from the inner peripheral side is made wider than the width W6-4 of the guard ring forming opening 6-4 on the outermost peripheral side.

  Further, in the semiconductor device of the third embodiment, as shown in FIG. 6, the innermost guard ring forming opening 6-1 and the second guard ring forming opening 6-2 from the inner peripheral side are provided. The width W12 of the mask portion between them is from the width W23 of the mask portion between the second guard ring forming opening 6-2 from the inner peripheral side and the third guard ring forming opening 6-3 from the inner peripheral side. Narrowed. Further, the width W23 of the mask portion between the second guard ring forming opening 6-2 from the inner peripheral side and the third guard ring forming opening 6-3 from the inner peripheral side is the third from the inner peripheral side. The width W34 of the mask portion between the guard ring forming opening 6-3 and the outermost guard ring forming opening 6-4 is made narrower.

As a result, in the semiconductor device of the third embodiment, as shown in FIG. 6, the curvature of the outer peripheral side and the lower part of the PN junction surface between the guard ring 7 and the N ⁻ epitaxial layer 5 around it is as follows. The guard ring 7 is formed so as to be smaller than the curvature of the inner peripheral side and the lower part. That is, the depth of the inner ring side portion of the guard ring 7 becomes sharply shallower toward the inner ring side, whereas the depth of the outer ring side portion of the guard ring 7 is gradually decreased toward the outer ring side. The guard ring 7 is formed so as to be shallow.

  Therefore, according to the semiconductor device of 3rd Embodiment, there can exist an effect similar to the semiconductor device of 2nd Embodiment.

  Hereinafter, a fourth embodiment of the semiconductor device of the present invention will be described. The semiconductor device of the fourth embodiment is configured in the same manner as the semiconductor device of the second or third embodiment described above, except for points described below. Therefore, according to the semiconductor device of 4th Embodiment, there can exist an effect similar to the semiconductor device of 2nd or 3rd embodiment mentioned above.

  FIG. 7 is a cross-sectional view of a diode as a semiconductor device of the fourth embodiment. The guard ring 7 of the semiconductor device of the fourth embodiment is similar to the guard ring forming openings 6 '(6-1, 6-2, 6-3, and the like of the semiconductor device of the second embodiment shown in FIG. 6-4) or a guard ring forming opening 6 '(6-1, 6-2, 6-3, 6- 6) similar to that of the semiconductor device of the fourth embodiment shown in FIG. 4).

  In the semiconductor devices of the first to fourth embodiments described above, the mask for forming the guard ring 7 and the P-type region 7 ′ in the active area (active region) is constituted by the oxide film 6. In the modification of the semiconductor device of the first to fourth embodiments, the mask for forming the guard ring 7 and the P-type region 7 ′ in the active area (active region) can be made of photoresist.

It is the figure which showed MPS (Merged pin / Schottky) as a semiconductor device of 1st Embodiment. FIG. 6 is a diagram for explaining a state where P-type impurities are introduced into N ⁻ epitaxial layer 5. FIG. 6 is a diagram for explaining a state where P-type impurities are diffused in N ⁻ epitaxial layer 5. It is the figure which expanded and showed a part of MPS as a semiconductor device of 2nd Embodiment. It is sectional drawing of MPS as a semiconductor device of 2nd Embodiment. It is the figure which expanded and showed a part of MPS as a semiconductor device of 3rd Embodiment. It is sectional drawing of the diode as a semiconductor device of 4th Embodiment. It is a figure for demonstrating the manufacturing process of the conventional semiconductor device. It is a figure for demonstrating the manufacturing process of the conventional semiconductor device. It is a figure for demonstrating the manufacturing process of the conventional semiconductor device. FIG. 11 is a plan view of the N ⁻ epitaxial layer 5 and the guard ring 7 of the conventional semiconductor device shown in FIG. 10 as seen through the oxide film 6 from above. It is an enlarged view of the guard ring 7 etc. of the conventional semiconductor device shown in FIG. It is sectional drawing of the semiconductor device which showed the state where the depth D of the guard ring 7 is shallower than the depth of the guard ring of the optimal design conditions. It is sectional drawing of the semiconductor device which showed the state where the depth D of the guard ring 7 is deeper than the depth of the guard ring of the optimal design conditions.

Explanation of symbols

4 N ⁺ semiconductor substrate 5 N ^- epitaxial layer 6 oxide film 6 'guard ring forming openings 6-1, 6-2, 6-3 and 6-4 guard ring formed opening 6-5,6-6,6- 7, 6-8 Guard ring forming opening 6 "P type region forming opening 7 Guard ring 7 'P type region in active area (active region)

Claims (6)

A first conductivity type semiconductor layer containing a low concentration impurity is formed on a first conductivity type semiconductor substrate containing a high concentration impurity, a mask is formed on the upper surface of the first conductivity type semiconductor layer, and a guard ring is formed on the mask. A formation opening is formed, a second conductivity type impurity is introduced into the first conductivity type semiconductor layer through the guard ring formation opening, and the second conductivity type impurity is introduced into the first conductivity type semiconductor layer. In the manufacturing method of the guard ring that forms the second conductivity type diffusion region as the guard ring by diffusing,
The mask is formed by dividing at least two guard ring forming openings, the second conductivity type impurity introduced through one guard ring forming opening, and the other adjacent to the one guard ring forming opening. Through the one guard ring forming opening so as to form a second conductivity type diffusion region as one guard ring integrated with the second conductivity type impurity introduced through the guard ring forming opening. A method of manufacturing a guard ring, comprising: diffusing the second conductivity type impurity introduced in this step and the second conductivity type impurity introduced through the other guard ring formation opening.   2. The guard ring according to claim 1, wherein the guard ring and the second conductivity type diffusion region in the active region on the inner peripheral side of the guard ring are simultaneously formed by using the mask. Method.   Of the plurality of guard ring forming openings formed in a divided manner, the width of the guard ring forming opening on the outer peripheral side of the guard ring is narrower than the width of the guard ring forming opening on the inner peripheral side of the guard ring. The manufacturing method of the guard ring of Claim 1 or 2.   Of the at least three guard ring forming openings formed in a divided manner, the width of the mask portion between the two adjacent guard ring forming openings on the outer periphery side of the guard ring is set to the two adjacent openings on the inner peripheral side of the guard ring. The method for manufacturing a guard ring according to any one of claims 1 to 3, wherein the width is larger than a width of a mask portion between openings for forming the guard ring.   The semiconductor device which comprises the guard ring manufactured by the manufacturing method of the guard ring as described in any one of Claims 1-4.   In a semiconductor device in which a first conductivity type semiconductor layer containing a low concentration impurity is formed on a first conductivity type semiconductor substrate containing a high concentration impurity, and a guard ring is formed in the first conductivity type semiconductor layer, the guard Of the boundary surface between the ring and the surrounding first conductive type semiconductor layer, the curvature of the guard ring outer peripheral side and the guard ring lower part is smaller than the curvature of the guard ring inner peripheral side and the guard ring lower part. A semiconductor device characterized by that.

Images