JP2007087574A - ビット線漏れ電流の低減 - Google Patents
ビット線漏れ電流の低減 Download PDFInfo
- Publication number
- JP2007087574A JP2007087574A JP2006256618A JP2006256618A JP2007087574A JP 2007087574 A JP2007087574 A JP 2007087574A JP 2006256618 A JP2006256618 A JP 2006256618A JP 2006256618 A JP2006256618 A JP 2006256618A JP 2007087574 A JP2007087574 A JP 2007087574A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- sram
- node
- power
- vdd1
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 12
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 19
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 19
- 238000010586 diagram Methods 0.000 description 18
- 230000015654 memory Effects 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- VHMVRYCSSMWIIU-UHFFFAOYSA-N 1H-benzimidazole naphthalene Chemical compound C1=CC=C2NC=NC2=C1.C1=CC=CC2=CC=CC=C21.C1=CC=CC2=CC=CC=C21.C1=CC=CC2=CC=CC=C21.C1=CC=CC2=CC=CC=C21 VHMVRYCSSMWIIU-UHFFFAOYSA-N 0.000 description 1
- 102100022804 BTB/POZ domain-containing protein KCTD12 Human genes 0.000 description 1
- 108091006146 Channels Proteins 0.000 description 1
- 101000974804 Homo sapiens BTB/POZ domain-containing protein KCTD12 Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
【解決手段】SRAMの電力を低減するための方法は、SRAMの待機動作中の部分の全てのビット線に第1の電圧を印加し、SRAMの通常動作中の部分の全てのビット線に第2の電圧を印加することにより達成される。第1の電圧は、第2の電圧以下である。
【選択図】図5
Description
S1A〜S1Z、S2 スイッチ
1000 コンピュータシステム
1002、1006 SRAM
1004 プロセッサ
Claims (10)
- SRAMの電力を低減するための方法であって、
a)前記SRAMの待機動作中の部分の全てのビット線(509)に第1の電圧(VDD2)を印加し、
b)前記SRAMの通常動作中の部分の全ての前記ビット線(509)に第2の電圧(VDD1)を印加すること
を含み、
c)前記第1の電圧(VDD2)が、前記第2の電圧(VDD1)以下である、SRAMの電力を低減するための方法。 - 前記第1の電圧(VDD2)が、第1の電圧基準に切り替えること(S2)によって印加される、請求項1に記載のSRAMの電力を低減するための方法。
- 前記第2の電圧(VDD1)が、第2の電圧基準に切り替えること(S1A〜S1Z)によって印加される、請求項1に記載のSRAMの電力を低減するための方法。
- 前記切り替えること(S2)が、1つ又は複数のトランジスタによって実行される、請求項2に記載のSRAMの電力を低減するための方法。
- 前記切り替えること(S1A〜S1Z)が、1つ又は複数のトランジスタによって実行される、請求項3に記載のSRAMの電力を低減するための方法。
- SRAM用の電力低減システムであって、
a)第1のスイッチ(S2)と、
b)第2のスイッチ(S1A〜S1Z)と
を備え、
c)前記第1のスイッチ(S2)が閉じる場合に、前記SRAMの待機動作中の部分の全てのビット線(509)に第1の電圧基準(VDD2)が印加されようになっており、
d)前記第2のスイッチ(S1A〜S1Z)が閉じる場合に、前記SRAMの通常動作中の部分の全てのビット線(509)に第2の電圧基準(VDD1)が印加されるようになっており、
e)前記第1の電圧(VDD2)が、前記第2の電圧(VDD1)以下である、SRAM用の電力低減システム。 - 前記第1のスイッチ(S2)が1つ又は複数のトランジスタからなる、請求項6に記載のSRAM用の電力低減システム。
- 前記第2のスイッチ(S1A〜S1Z)が、1つ又は複数のトランジスタからなる、請求項6に記載のSRAM用の電力低減システム。
- コンピュータシステム(1000)であって、
a)少なくとも1つのプロセッサ(1004)と、
b)少なくとも1つのSRAM(1002)と
を備え、
c)前記少なくとも1つのSRAMが、SRAM用の電力低減システムを含み、
d)前記SRAM用の電力低減システムが、前記SRAMの待機動作中の部分の全てのビット線(509)に第1の電圧(VDD2)を印加し、
e)前記SRAM用の電力低減システムが、前記SRAMの通常動作中の部分の全てのビット線(509)に第2の電圧(VDD1)を印加し、
f)前記第1の電圧(VDD2)が前記第2の電圧(VDD1)以下である、コンピュータシステム。 - 前記第1の電圧が、第1の電圧基準に切り替えること(S2)によって印加される、請求項9に記載のコンピュータシステム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/234,480 US20070081409A1 (en) | 2005-09-23 | 2005-09-23 | Reduced bitline leakage current |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007087574A true JP2007087574A (ja) | 2007-04-05 |
Family
ID=37910971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006256618A Pending JP2007087574A (ja) | 2005-09-23 | 2006-09-22 | ビット線漏れ電流の低減 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20070081409A1 (ja) |
JP (1) | JP2007087574A (ja) |
CN (1) | CN1937076A (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7668035B2 (en) | 2008-04-07 | 2010-02-23 | International Business Machines Corporation | Memory circuits with reduced leakage power and design structures for same |
US8947968B2 (en) * | 2013-07-08 | 2015-02-03 | Arm Limited | Memory having power saving mode |
DE102013012234B4 (de) * | 2013-07-23 | 2018-05-30 | Infineon Technologies Ag | Speichervorrichtung und Verfahren zum Versetzen einer Speicherzelle in einen Zustand mit einer reduzierten Leckstromaufnahme |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5323353A (en) * | 1993-04-08 | 1994-06-21 | Sharp Microelectronics Technology Inc. | Method and apparatus for repair of memory by redundancy |
US5430683A (en) * | 1994-03-15 | 1995-07-04 | Intel Corporation | Method and apparatus for reducing power in on-chip tag SRAM |
US5901103A (en) * | 1997-04-07 | 1999-05-04 | Motorola, Inc. | Integrated circuit having standby control for memory and method thereof |
US6141259A (en) * | 1998-02-18 | 2000-10-31 | Texas Instruments Incorporated | Dynamic random access memory having reduced array voltage |
US6563746B2 (en) * | 1999-11-09 | 2003-05-13 | Fujitsu Limited | Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode |
JP2002032990A (ja) * | 2000-07-17 | 2002-01-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
US7027346B2 (en) * | 2003-01-06 | 2006-04-11 | Texas Instruments Incorporated | Bit line control for low power in standby |
US7184341B2 (en) * | 2004-07-26 | 2007-02-27 | Etron Technology, Inc. | Method of data flow control for a high speed memory |
US7272061B2 (en) * | 2005-01-24 | 2007-09-18 | Intel Corporation | Dynamic pre-charge level control in semiconductor devices |
-
2005
- 2005-09-23 US US11/234,480 patent/US20070081409A1/en not_active Abandoned
-
2006
- 2006-09-21 CN CNA2006101595306A patent/CN1937076A/zh active Pending
- 2006-09-22 JP JP2006256618A patent/JP2007087574A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US20070081409A1 (en) | 2007-04-12 |
CN1937076A (zh) | 2007-03-28 |
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