JP2007087118A - Controller and portable terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller for surely preventing the loss of data even when power supply is cut during data processing. <P>SOLUTION: This controller is provided with a CPU 10 for controlling a controller 100; a DRAM 14 for temporarily storing data to be used by the controller 100; an FeRAM 16 for storing a portion of data of the DRAM 14; and an address detection part 18 for detecting whether or not data are written in the prescribed address space of the DRAM 14. When it is detected that the data are written in the prescribed address space of the DRAM 14 by an address detecting part 18, the data same as that written in the DRAM 14 are written in the FeRAM 16. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a control device, and more particularly, to a control device and a portable terminal having a data backup function when power is lost.

  Control devices that perform data processing are required to back up work memory data that is being processed to prevent data loss even if the power is cut off during data processing. As a work memory used in the control device, a volatile memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) is used from the viewpoint of the operation speed and the number of rewritable times. However, the volatile memory has a property that the stored data is lost when the power is turned off.

On the other hand, in Patent Document 1, when a drop in the power supply voltage is detected by the voltage detection circuit, the data in the cache memory configured by the volatile memory is written into the flash memory that is a nonvolatile memory, and the data is retained. A method is disclosed in which data held in the flash memory at the next power-on is written back to the hard disk device to return to the data state when the power is lost. That is, in this method, data is backed up to the flash memory when the power is turned off.
JP 2001-34535 A

  However, the time required for writing to the flash memory is usually as long as several μsec or more, and the power is turned off before all data in the cache memory is written to the flash memory, so that data cannot be written normally. was there.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a control device that can reliably prevent the loss of data even if the power is lost during data processing.

  One embodiment of the present invention relates to a control device. The device includes a control unit that controls a part or the whole of the device, a volatile memory that temporarily stores data used in the device, and a non-volatile memory that holds data of the volatile memory, When data is written to the volatile memory, the same data as the data written to the volatile memory is written to the nonvolatile memory.

  According to this aspect, every time data is written to the volatile memory, the same data as the data is controlled to be written to the nonvolatile memory. Thus, it is possible to avoid the problem that the power is turned off before the data writing operation to the nonvolatile memory is completed, which is a problem when data is written from the memory to the nonvolatile memory. Therefore, even if the power source is lost during data processing, it is possible to reliably prevent the loss of data.

  In this aspect, an address detection unit that detects whether or not data is written to a predetermined address space of the volatile memory is further provided, and the address detection unit writes data to the predetermined address space of the volatile memory. When it is detected, the same data as the data written in the volatile memory may be written in the nonvolatile memory. According to this, when it is detected that data is written in an address space in which data necessary for data processing is stored in the volatile memory, the same data can be stored in the nonvolatile memory. . Therefore, since only data necessary for data processing after power-on can be stored in the nonvolatile memory, cost and power consumption can be suppressed.

  The address detection unit may detect whether or not data writing is performed in an address space for temporarily storing data used by the control unit. Thus, after the power is turned off, the data can be restored by being used by the control unit at the next power-on, so that the data processing before the power is turned off can be continuously performed.

  In this aspect, the nonvolatile memory may be characterized in that the speed required for writing is equal to or higher than the speed required for writing in the volatile memory. The nonvolatile memory may be composed of a ferroelectric memory or a magnetoresistive memory. Here, the speed required for writing is “equivalent” means that the time required for writing is on the same order, and the speed required for writing in the nonvolatile memory is approximately 1/10 of the speed required for writing in the volatile memory. That is all you need. According to this, since the data writing to the nonvolatile memory is completed immediately, it is possible to avoid the problem that the power is turned off while the data written to the volatile memory is being written to the nonvolatile memory. .

  In this embodiment, the data held in the nonvolatile memory may be written back to the volatile memory when the apparatus is turned on. Thereby, even if the data stored in the volatile memory is lost when the device is turned off, the data held in the nonvolatile memory is written back to the volatile memory when the power is turned on again. It is possible to restore at least a part of the data in the volatile memory to the state before the power is turned off. Therefore, it is possible to continue the data processing before the power is turned off after the power is turned on again.

  Another aspect of the present invention also relates to a control device. This apparatus is used by a storage unit that stores a first program for controlling the system and a second program for updating the first program, a control unit that executes the program, and a control unit. A volatile memory that temporarily stores data and a non-volatile memory that retains data in the volatile memory are provided, and when the first program is updated, the second program is transferred to the volatile memory. It is stored temporarily and also stored in a non-volatile memory. When updating the program, after the second program, which is an update program, is stored in the volatile memory, the second program is once erased from the storage unit together with the first program. For example, the second program is also stored in the nonvolatile memory. As a result, when the power is turned off during the update of the first program, the second program stored in the volatile memory disappears, but is retained in the nonvolatile memory when the power is turned on next time. By storing the second program in the volatile memory again, it is possible to reliably prevent the second program from being lost when the power is lost, and to update the program again.

  Yet another embodiment of the present invention relates to a mobile terminal. The terminal includes an antenna that receives a radio signal, a conversion unit that converts the frequency of the received radio signal into a baseband signal, a processing unit that demodulates the baseband signal, and a device based on the demodulated baseband signal. A control unit that controls part or all of the memory, a volatile memory that temporarily stores data used in the device, and a non-volatile memory that holds data of the volatile memory. When writing to the volatile memory occurs, the same data as that written to the volatile memory is also written to the nonvolatile memory. Mobile terminals are often driven by batteries, and power consumption often drops during processing due to battery consumption. According to this aspect, even if power is lost during terminal processing, data loss is guaranteed. Therefore, when the power is turned on again, the processing immediately before the power is turned off can be continued.

  It should be noted that any combination of the above-described constituent elements and the expression of the present invention converted between a method, an apparatus, a system, a computer program, a data structure, a recording medium, etc. are also effective as an aspect of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, even if a power supply loses | disappears during data processing, the control apparatus which can prevent loss of data reliably can be obtained.

(Embodiment 1)
FIG. 1 is a diagram showing a block configuration of a control device 100 according to Embodiment 1 of the present invention. The control device 100 includes a CPU (Central Processing Unit) 10, a hard disk 12, a DRAM (Dynamic Random Access Memory) 14, a FeRAM (Ferroelectric Random Access Memory) 16, and an address detection unit 18. ing. Each block is connected to the bus 20 and exchanges data between the blocks via the bus 20.

  CPU10 performs control and calculation of the whole control apparatus 100 according to a program. The CPU 10 also has a function of monitoring the power supply voltage and detecting that the power supply has been lost during data processing. When the CPU 10 detects that the power is lost during data processing, the CPU 10 notifies the address detection unit 18 (described later) that the power has been lost when the power is turned on next time.

  The hard disk 12 stores a program for operating the CPU 10 and data used for the program. Note that a flash memory may be used instead of the hard disk.

  The DRAM 14 is a volatile memory that is used as a work memory that temporarily holds data used by the control device 100. Among these, the predetermined address space of the DRAM 14 is used as a work memory of the CPU 10, and data necessary for the calculation of the CPU 10 and the result of the calculation are written into the predetermined address space of the DRAM 14. The address space used as the work memory of the CPU 10 may be fixed at all times or may be changeable by a program.

  The FeRAM 16 is a non-volatile memory that functions as a backup memory for holding data stored in a predetermined address space used as a work memory of the CPU 10 among the data stored in the DRAM 14 together with the DRAM 16. is there. When the power is turned off and the data in the DRAM 14 is lost, the data processing before the power is turned off can be continued if the data used by the CPU 10 at the next power-on can be restored. The FeRAM 16 is used as a backup memory for data restoration.

  In FIG. 1, the DRAM 14 is used as a work memory of the control device 100, but a volatile memory may be used from the viewpoint of the operation speed and the number of rewritable times. Good. In FIG. 1, the FeRAM 16 is used as a backup memory for the DRAM 14 which is a volatile memory. However, any non-volatile memory capable of reading and writing at a speed equivalent to or higher than that of the volatile memory may be used. access memory: magnetoresistive memory).

  The address detection unit 18 monitors writing to the DRAM 14. When writing occurs in a predetermined address space used as a work memory of the CPU 10, control is performed so that the same data as the data written in the address space is written into the FeRAM 16.

  Specifically, a control signal, an address signal, and a data signal of the DRAM 14 are connected to the address detection unit 18 and the presence or absence of writing to the DRAM 14 is monitored from the control signal of the DRAM 14. When the writing to the DRAM 14 is detected, it is determined from the value of the address signal of the DRAM 14 whether the writing to the DRAM 14 is to a predetermined address space used as a work memory of the CPU 10. Information on the address space used as the work memory of the CPU 10 is transmitted from the CPU 10 to the address detection unit 18.

  When the writing to the DRAM 14 is a writing to a predetermined address space, the address detection unit 18 combines the same data as the data written to the DRAM 14 with the address value of the DRAM 14 to which the data is written, and the FeRAM 16 The control signal, address signal, and data signal of the FeRAM 16 are generated so as to be written to The FeRAM 16 holds the same data as the data written in the DRAM 14 and the address of the DRAM 14 where the data has been written in accordance with the control signal generated by the address detection unit 18.

  Further, when the information indicating that the power supply is lost during data processing is transmitted from the CPU 10, the address detection unit 18 reads the data written in the DRAM 14 from the FeRAM 16 and the address of the DRAM 14 in which the data was written. Then, control is performed to restore the data in the DRAM 14. That is, the read data is written in the address space of the DRAM 14 read from the FeRAM 16. Thereby, the data stored before the power is lost is restored to the address space used as the work memory of the CPU 10 of the DRAM 14.

  Based on such a configuration, the operation of the control circuit 100 of FIG. 1 will be described. The CPU 10 appropriately downloads a program stored in the hard disk 12, and executes control of the entire control device 100 and various calculations according to this program. At this time, data used by the CPU 10 is read from the hard disk 12 and written in a predetermined address space of the DRAM 14 used as the work memory of the CPU 10. The calculation result of the CPU 10 is also written and held in a predetermined address space of the DRAM 14. Various data used by the control device 100 are temporarily stored in the DRAM 14.

  When data writing to the DRAM 14 occurs, the address detection unit 18 detects a writing operation to the DRAM 14 and determines whether or not the data writing is to a predetermined address space used as a work memory of the CPU 10. To do. When it is determined that the data is written in a predetermined address space, the same data as the data written in the address space is written to the FeRAM 16 together with the written address value by the control of the address detector 18. .

  If the power is turned off during data processing, all data written to the DRAM 14 is lost, but the data written to the FeRAM 16 is retained even if the power is turned off. When the power is turned on next time, the CPU 10 detects that the power has been lost during the data processing, and transmits the fact to the address detection unit 18. Based on this transmission signal, the address detection unit 18 performs control to write back data from the FeRAM 16 to a predetermined address space of the DRAM 14 used as a work memory of the CPU 10. Thereby, data necessary for the operation of the CPU 10 among the data lost in the DRAM 14 can be restored to the state before the power is turned off.

  As described above, according to the control device 100 according to the first embodiment of the present invention, when data is written in a predetermined address space of the DRAM 14 that is a volatile memory, the same data is also transferred to the FeRAM 16 that is a nonvolatile memory. Write it down. Thereby, the following effects can be enjoyed.

  (1) Every time data is written to a predetermined address space of the DRAM 14, the same data is controlled to be written to the FeRAM 16. Therefore, when the conventional power supply voltage is lowered, the volatile memory is switched to the nonvolatile memory. It is possible to avoid the problem that the power is turned off before the write operation is completed, which is a problem when data writing is performed. Therefore, even if the power source is lost during data processing, it is possible to reliably prevent the loss of data.

  (2) Since a non-volatile memory capable of reading and writing at a speed equivalent to or faster than that of a volatile memory is used as a backup memory, writing to the non-volatile memory is completed immediately. Therefore, it is possible to avoid the problem that the power is turned off while the data written in the volatile memory is being written to the nonvolatile memory. Therefore, even if the power source is lost during data processing, it is possible to reliably prevent the loss of data.

  (3) Of the data written in the DRAM 14, data written in the address space used as the work memory of the CPU 10 is written in the FeRAM 16, so that the data processing is continued at the next power-on after the power is turned off. It can be carried out. As described above, since data necessary for continuing data processing is stored in the FeRAM 16 and data unnecessary for backup is not written to the FeRAM 16, it is not necessary to prepare a large-capacity nonvolatile memory, and cost and power consumption can be reduced. Can be suppressed.

(Embodiment 2)
FIG. 2 is a diagram illustrating a configuration of a mobile terminal 200 according to Embodiment 2, which is a system to which the control device of the present invention is applied. The mobile terminal 200 includes an antenna 210, an RF interface unit 220, a baseband processing unit 230, and a control device 240.

  The antenna 210 receives a signal from a transmission device (not shown) via a wireless section. The RF interface unit 220 converts a radio frequency signal received by the antenna 210 into a baseband signal. The baseband processing unit 230 demodulates the baseband signal.

  The control device 240 implements various applications by controlling the mobile terminal 200 using the demodulated baseband signal and the built-in program (built-in program). The control device 240 is the same as that of the first embodiment. The control device 100 is adapted. However, the hard disk 12 of the control device 100 is replaced with a flash memory 22, and the DRAM 14 is replaced with an SRAM 24. The other blocks of the control device 240 are the same as those of the control device 100 of the first embodiment, and are given the same reference numerals.

  The built-in program is stored in the flash memory 22 of the control device 240. The portable terminal 200 can update the built-in program for the purpose of eliminating system problems and adding functions. Therefore, an update program for updating the system program is written in the flash memory 22 separately from the normal built-in program (system program).

  During normal operation of the mobile terminal 200, the CPU 10 controls the mobile terminal 200 according to the system program. At this time, the control device 240 of the mobile terminal 200 backs up the data used by the CPU 10 to the FeRAM 16 by the same method as in the first embodiment. That is, when a write operation to the SRAM 24 occurs, if it is a write to a predetermined address space used as a work memory of the CPU 10, the same data as the data written at that address is written to the FeRAM 16. . By doing so, when the power is turned off during data processing in the portable terminal 200, the contents of the FeRAM 16 can be written back to the predetermined address space of the SRAM 24 at the next power-on.

  On the other hand, when updating the system program, the CPU 10 rewrites the data of the system program according to the update program. The procedure for updating the system program will be described below.

  First, a signal indicating the presence of the updated system program is transmitted from a transmission device (not shown), and the mobile terminal 200 receives the signal through the antenna 210, and the control device via the RF interface unit 220 and the baseband processing unit 230 It is transmitted to 240 CPU 10. When the CPU 10 receives the signal, the CPU 10 reads the update program in the flash memory 22 and writes the update program in a predetermined address space used as a work memory of the CPU 10 in the SRAM 24. At this time, the address detector 18 detects that data has been written in a predetermined address space of the SRAM 24 and controls to write the same data to the FeRAM 16. Therefore, the update program is also written in the FeRAM 16.

  Next, when all the update programs are written in the SRAM 24, the CPU 10 performs an update operation of the system program according to the update program. First, the CPU 10 erases data in the flash memory 22 at once. At this time, the update program in the flash memory 22 is also erased. Next, the CPU 10 sends a transmission request for the updated system program to a transmission device (not shown). Then, the updated system program is received, and the system program demodulated by the baseband processing unit 230 is written into the flash memory 22. When all the system programs are written to the flash memory 22, the update program stored in the SRAM 24 is written back to the flash memory 22, and the update operation is completed.

  When the power is turned off during the update operation, the CPU 10 detects that the power is turned off during the update operation when the power is turned on next time. Then, the CPU 10 transmits this information to the address detection unit 18. When the address detection unit 18 obtains information from the CPU 10, it writes the update program stored in the FeRAM 16 back into the SRAM 22. Then, according to the update program in the SRAM 22, the CPU 10 again performs the update operation of the system program.

  As described above, according to the portable terminal 200 according to the second embodiment, when data is written in the predetermined address space of the SRAM 24, the same data is written in the FeRAM 16 as well. 1 can be obtained. In particular, the mobile terminal 200 is often driven by a battery, and the power is frequently reduced during processing due to battery consumption. However, even if the power is lost during processing of the terminal, the mobile terminal 200 causes data loss. Can be reliably prevented. Therefore, when the power is turned on again, the process immediately before the power is turned off can be continuously performed.

  Further, when the power is turned off during the updating operation of the system program, the updating program stored in the SRAM 24 disappears and no updating program exists in the flash memory 22 as described above, but the updating operation starts in the portable terminal 200. Since the update program is sometimes stored in the FeRAM 16, it is possible to reliably prevent the update program from being lost when the power is lost.

  The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .

  For example, in the present embodiment, the CPU 10 detects that the power supply has been lost, but a power supply loss detection unit may be provided separately. In this case, the address detection unit 18 may receive information indicating that the power supply has been lost from the power supply loss detection unit.

  Further, in this embodiment, when it is detected that the power supply is lost during data processing, the data stored in the FeRAM 16 is written back to the DRAM 14 at the next power supply startup. The data stored in the FeRAM 16 may always be written back to the DRAM 14. In this case, data is written back from the FeRAM 16 to the DRAM 14 even when the power is turned on after the power is normally turned off, but it is not necessary to detect the loss of the power during the data processing. The control circuit of the invention can be realized with a simple configuration.

  In this embodiment, the address of the DRAM 14 corresponding to the data is stored in the FeRAM 16 together with the data. However, only a base address in a predetermined address space of the DRAM 14 used as a work memory of the CPU 10 is separately stored in a nonvolatile memory. The FeRAM 16 may be configured to store only data. In this case, the address relationship between the DRAM 14 and the FeRAM 16 may be obtained by calculation based on the base address. As a result, an arithmetic circuit for calculating an address is required. However, since only the data needs to be stored in the FeRAM 16, the capacity of the nonvolatile memory can be reduced.

  In the second embodiment, the portable terminal 200 has been described. However, the present invention is not limited to this. For example, the present invention can be applied to any system such as a digital television or a personal computer in which a system program is updated. In this case, the example of updating the system program via the wireless line has been described in the portable device 2, but the system program may be updated via a wired line. Alternatively, the system program may be updated by inserting a recording medium such as an optical disk or a memory card storing the updated system program into the system.

2 is a configuration diagram of a control device 100 according to Embodiment 1. FIG. 6 is a configuration diagram of a mobile terminal 200 according to Embodiment 2. FIG.

Explanation of symbols

10 CPU
12 Hard disk 14 DRAM
16 FeRAM
18 Address detection control circuit 20 Bus 22 Flash memory 24 SRAM
DESCRIPTION OF SYMBOLS 100 Control apparatus 200 Portable terminal 210 Antenna 220 RF interface part 230 Baseband process part 240 Control apparatus

Claims (7)

A control unit for controlling a part or the whole of the device;
Volatile memory for temporarily storing data used in the device;
A non-volatile memory that holds data of the volatile memory,
A control device, wherein when data is written to the volatile memory, the same data as the data written to the volatile memory is written to the nonvolatile memory. An address detector for detecting whether or not data is written to a predetermined address space of the volatile memory;
When the address detection unit detects that data is written to a predetermined address space of the volatile memory, the same data as the data written to the volatile memory is written to the nonvolatile memory. The control device according to claim 1, wherein 3. The control according to claim 2, wherein the address detection unit detects whether or not data is written in an address space for temporarily storing data used by the control unit. apparatus. The control device according to claim 1, wherein the nonvolatile memory has a speed required for writing equal to or higher than a speed required for writing to the volatile memory. 5. The control device according to claim 1, wherein the data held in the nonvolatile memory is written back to the volatile memory when the power of the device is turned on. A storage unit storing a first program for controlling the system and a second program for updating the first program;
A control unit for executing the program;
A volatile memory for temporarily storing data used by the control unit;
A non-volatile memory that holds data of the volatile memory,
The control device, wherein when updating the first program, the second program is temporarily stored in the volatile memory and also stored in the nonvolatile memory. An antenna for receiving radio signals;
A conversion unit that converts the frequency of the received radio signal into a baseband signal;
A processing unit for demodulating the baseband signal;
Based on the demodulated baseband signal, a control unit that controls part or all of the device;
Volatile memory for temporarily storing data used in the device;
A non-volatile memory that holds data of the volatile memory,
A portable terminal, wherein when data is written to the volatile memory, the same data as the data written to the volatile memory is written to the nonvolatile memory.

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