JP2001312891A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which write-in is made not to be biased to a specific memory block and disappearance of data can be prevented even if processing is interrupted during write-in of data. SOLUTION: This device is a block erasing type flash memory 1, has data write-in area 3A-3E and control status write-in area 4A-4E in memory blocks 2A-2E, write-in data specific data ID, an erasion counter indicating the number of times of erasions of a data write-in memory block and a write-in status indicating a time sequential order of write-in data with the same ID are written in the area 4A-4E. When new data is written by a processor 10, after a memory block in which write-in status indicates possibility of write-in and the erasion counter indicates the minimum is erased, new data and control status are written, and the control status including the same data ID in the other memory block is updated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for writing and reading data in a block erase flash memory for erasing and writing data in block units.

[0002]

2. Description of the Related Art A semiconductor memory is generally used in an adjustment data processing device for a scan converter in a built-in device such as a liquid crystal projector because processed data must be stored. Since a semiconductor memory does not have a drive system as compared with a magnetic disk device represented by a hard disk or the like, it is extremely advantageous in terms of miniaturization, low power consumption, high operating speed and reliability.
However, conventionally used DRAM and SRA
A semiconductor memory such as M always requires a refresh operation or backup by a battery or the like, and has many problems such as a need to constantly supply power or maintain the battery. There is an EEPROM that does not require a battery as a semiconductor memory that solves these problems, but there are problems in terms of capacity and cost.

[0003] In recent years, flash memories have been receiving attention as a solution to these problems of semiconductor memories. A flash memory is a semiconductor memory that can electrically rewrite data similarly to an EEPROM, does not require an electrical backup means such as a battery to retain data, and has a lower cost and a larger capacity than an EEPROM. is there.

Due to the nature of the flash memory, prior to writing data, it is necessary that the entire memory block formed of a continuous memory space including an area to which data is written be erased. Since the flash memory deteriorates with erasure, an upper limit is currently defined for the number of erasures, and if erasing is performed beyond that limit, it is not guaranteed that data writing will be performed normally.

[0005] The erasing process of the flash memory usually takes several tens of ms or more. Therefore, when writing to the flash memory, after erasing the memory block, special processing is required to maintain the reliability of the data when the processing is interrupted due to the power-off or the like during the writing processing since the data must be written. Needless to say, it is necessary. Japanese Patent Application Laid-Open No. H10-124403 discloses a method related to this type of writing method.

[0006]

According to such a conventional writing method in a block erase flash memory, the data to be written and the memory block to which the data is to be written are fixed uniquely, and a specific data Is frequently updated, the corresponding write destination memory block is frequently erased and written, and the memory block reaches the usage limit earlier than other memory blocks. This means that the flash memory will need to be replaced even though other memory blocks are still available.

Since the flash memory erases data in units of memory blocks at a time, old data before rewriting and new data after rewriting are stored in the block erase flash memory until a series of writing operations is completed. Are not present, and it takes time to erase the data.If the data write operation is interrupted due to the power being turned off during such a series of write operations, the block erase type There is a problem that a part of data does not exist on the flash memory.

[0008] When data is read from the block erase flash memory in such a state, the obtained data becomes an abnormal data with a part of the data erased, which confuses the operation of the system. On the other hand, when writing old data before writing to a save block uniquely assigned to a block erase flash memory prior to writing new data, it is necessary to erase two blocks, the save block and the corresponding write block. There is a problem that a series of writing processes becomes long.

An object of the present invention is to provide a semiconductor memory device capable of preventing writing from being biased to a specific memory block and preventing data loss even if processing is interrupted during data writing. .

[0010]

According to the present invention, there are provided a plurality of memory blocks of an erasing unit, each memory block having a management status writing area in addition to a data writing area, and the management status writing area having the management status writing area. The management status includes a data ID for specifying data to be written in the write area, an erasure counter indicating the number of erasures of the memory block to which the data is to be written, and a write status indicating the chronological order of data written in the same data ID. And a memory block in which, when writing new data, among the plurality of memory blocks, the management status indicates that the write status is writable and the erase counter indicates a minimum value. After erasing, new data is And writing management status, a semiconductor memory device characterized by comprising a processor for updating the management status containing the same data ID of the other memory blocks.

Further, the present invention is the semiconductor memory device, wherein the write status indicates one of an initial state, a write disable state, and a write enable state.

Further, according to the present invention, when the processor writes new data, the write status of the memory block to be written is updated to a write-disabled state, and the write status of the memory block indicating the same data ID to be written is updated. The write status is updated to a writable state in the semiconductor memory device.

Further, the present invention provides a semiconductor memory device according to the present invention, wherein the update of the write status is performed first on a memory block to which data is to be written, and then on a memory block having the same data ID. is there.

Further, according to the present invention, the write status is such that a state in which a memory block is erased is an initial state,
When the state is a bit 1 state, a write disable state is indicated by a state in which at least one or more bits are 0,
Writable state is one or more bits 0
When the erased state is the state of bit 0, the non-writable state is indicated by the state where at least one bit is 1, and the writable state is one or more bits in the non-writable state. 1 is a semiconductor memory device characterized by being shown with 1 added.

Further, the present invention is a semiconductor memory device characterized in that the update of the write status indicating the same data ID performed when performing a new write is performed without erasing the corresponding memory block. .

Further, the present invention is a semiconductor memory device wherein when the processor writes new data, after the corresponding memory block is erased, actual data is written before writing the management status.

Further, the present invention is the semiconductor memory device, wherein the update of the management status is performed last in the update of the write status.

Further, the present invention is the semiconductor memory device, wherein the erase counter is incremented by a constant when the processor writes data.

In the present invention, when the processor reads data, the processor reads the data from a memory block whose data ID matches and whose write status is in a write-disabled state. Reading is performed from a memory block whose ID matches and whose write status indicates a writable state, and when there are a plurality of memory blocks indicating a writable state, reading is performed from the memory block having the largest erase counter. It is a semiconductor memory device.

Further, the present invention is the semiconductor memory device, wherein the write status is defined to indicate that data writing to the corresponding memory block has been completed normally.

[0021]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention. In FIG.
1 is a block erase flash memory, 2A to 2E are memory blocks, 3A to 3E are data write areas, 4A
4E are management status writing areas, and 10 is a processor (processor). The block erase flash memory 1 is configured by memory blocks 2A to 2E divided by the minimum erase unit. The memory blocks 2A to 2E have data write areas 3A to 3E, respectively.
E and management status writing areas 4A to 4E. The processor 10 includes the memory blocks 2A to
The processor writes and reads data and management status in the data write areas 3A to 3E and the management status write areas 4A to 4E of the 2E, respectively.

FIG. 2 is a diagram showing the contents of the management status writing areas 4A to 4E of FIG. 5A to 5E are data ID write areas, 6A to 6E are erase counter write areas, and 7A to 7E are write status write areas. The management status writing areas 4A to 4E are respectively
It is composed of data ID write areas 5A to 5E, erase counter write areas 6A to 6E, and write status write areas 7A to 7E.

All data to be written to the block erase flash memory is divided into groups having the maximum capacity of the data write area, and each is managed by a unique data ID for specifying the data. In the data ID writing areas 5A to 5E, data IDs for specifying the data written in the data writing areas 3A to 3E are written.

The erasure counters 6A to 6E are data unique to the memory blocks 2A to 2E, and the number of times of erasure of the memory block is written in each of them.

In the write status write area 7, the data written in the data write area 3
As shown in FIG. 3, the write status indicating the chronological order of the write status between the same data IDs written on the block erase flash memory 1 is changed to the initial state 8-- 1 and a write-disabled state 8-2 indicating that the data is the latest data and cannot be lost.
And writable state 8 which is old data and may be lost
-3 is written in one of three states.

FIG. 4 is a diagram showing a flowchart of writing data and management status by the processor 10 into the block erase flash memory 1 in FIG.

First, a write destination memory block to which data is to be written is searched (step 401). The search for the write destination memory block will be described with reference to FIG.

In FIG. 5, a search for a write destination memory block is performed by first checking the memory block number (M-
CNT) and write destination candidate memory block (W-BLK)
Is initialized, and the comparison erase count (E-CMP) is set to the maximum erase count (E-MAX) in the block erase flash memory 1 (step 501). Then, the write statuses 7A to 7E of the memory block indicated by the check memory block number (M-CNT) are checked (step 502). It is determined whether the write statuses 7A to 7E are not in a write-disabled state (step 50).
3) If not in a write-disabled state, the erase counter is checked (step 504).

The check value is the comparison erase count (E-CMP)
It is determined whether the value indicates a smaller value (step 50).
5) If the value indicates a value smaller than the number of times of comparison and erasure (E-CMP), the number of times of comparison and erasure (E-CMP) is used as a check value;
Also, the write destination candidate memory block (W-BLK) is rewritten to the check memory block number (M-CNT) (step 506). Then, it is determined whether or not all memory blocks have been checked (step 50).
7). If not checked, the check memory block number (M-CNT) is updated (step 508), the process returns to step 502, and steps 502 to 507 are repeated for all the memory blocks. At this point, when all memory blocks have been checked,
In the write destination candidate memory block (W-BLK), a data block that is not referred to or a memory block to which no data has been written and that has been erased the least number of times is registered. In addition, the number of comparison erase operations (E-
CMP) is a write destination candidate memory block (W-BL
K) shows the number of erases. Thereafter, the comparison erase count (E-CMP) is compared with the maximum erase count (E-MAX) to determine whether the comparative erase count (E-CMP) has reached the maximum erase count (E-MAX). (Step 509), and if so, it is determined that there is no new memory block to be written, and error processing is performed (step 51).
0).

Next, returning to FIG. 4, an erasing process of the memory block indicated by the write destination candidate memory block (W-BLK) is performed (step 402). This processing will be described with reference to FIG.

In FIG. 6, in the erasing process of the memory block, prior to the erasing process, the number of erasures of the corresponding memory block is read out from the erasure counter value registered in the memory block, and saved as the number of saved erasures (E-CNT) ( Step 601), and then execute an erasing process (step 6)
02).

As described above, since erasure and data writing are performed on a memory block including data that is not always referred to and having a small number of erasures, a memory block to be written dynamically changes, and writing occurs. Memory blocks to be used are not biased.

Next, returning to FIG. 4, data is written to the memory block erased in step 402 prior to writing the management status (step 40).
3). Thereafter, the data ID which is the management status is written (step 404). Further, writing of an erasure counter indicating the number of erasures, which is the management status, is performed (step 405).

FIG. 7 shows the writing of the erase counter.
This will be described with reference to FIG. First, the number of save / erase times (E-CNT) obtained in step 601 of FIG. 6 is checked (step 701). Then, it is determined whether the check value is an illegal value that cannot be originally taken (step 702). If the value is an invalid value, it is considered that the writing process is interrupted and the normal erasure counter value cannot be written, and the number of erasures of the corresponding memory block is estimated. First, the number of save erasures (E-CNT) is set to the minimum value (E-MIN), and the check memory block number (M-CNT) is initialized (step 703).

The erase counter of each memory block is checked (step 704), and it is determined whether or not the check value is greater than the number of save / erase times (E-CNT) (step 705). CNT)
Is rewritten to the check value (step 706). And
It is determined whether all the memory blocks have been checked (step 707). If not checked, the check memory block number (M-CNT) is updated (step 708), the process returns to step 704, and steps 704 to 708 are repeated for all the memory blocks, and the maximum check value is saved to the save / erase counter. (E-CNT). When the save / erase counter is normal or the analogy ends, the save / erase counter (E
-CNT) plus a specified number (step 709), and write the save erase counter (E-CNT) into the erase counter (step 710). If the erase counter has an incorrect value, the maximum value of the erase counters registered in each memory block can be used to minimize the erase failure due to the difference between the original erase count and the erase counter. Becomes

Next, returning to FIG. 4, after writing the erasure counter, the write status is updated from the initial state to the non-writable state (step 406). The write status indicates a time-series order between the same data IDs, and has a role of a flag indicating that a series of data writing to the corresponding memory block has been normally completed.

Next, the write status of the memory block containing the same data ID is updated (step 407).
Referring to FIG. 8, first, a memory block number (M-CNT) to be checked is initialized (step 80).
1) It is determined whether the write destination memory block is not a block to be checked (step 802). If not, the registered data ID is checked (step 803). It is determined whether or not the check value matches the data ID for which data has been written (step 80).
4) If they match, the write status is written, and the write status is updated from the non-writable state to the writable state (steps 805, 806, 8).
07). Then, it is determined whether or not all the memory blocks have been checked (step 808). If not checked, check memory block number (M
-CNT) (step 809), and step 80
2, the steps 802 to 809 are repeated for all the memory blocks.

As a result, the write status indicates a non-writable state when the latest data is written to the memory block, and indicates a writable state when old data is written to the memory block.

Here, the writing steps 805, 806 and 807 of the writing status will be described with reference to FIG.

First, in step 805, a write status read is written to the register F of the processor, and when the memory block is erased, all bits in the memory block become "1". Are all bits "1". After erasing, the flash memory can only be operated for writing in the direction of setting the bit to 0, and when rewriting the bit from 0 to 1, it is necessary to erase the memory block.

Next, in step 806, the bit is set to 0 in the write disable state indicating the latest data, and the write disable state 8-2 in FIG. 3 is set. By increasing a certain number of bits and setting the write disabled state 8-3 in FIG. 3, the write status can be updated without erasing the memory block.

As described above, even if the erasing process is performed on the block erasure type flash memory, the latest data or the data immediately before the latest data always exists, and the data is not lost.

Further, since the erasure associated with the update of the write status does not need to be performed, a series of data write time can be shortened.

FIG. 9 is a view showing a flowchart of reading data and management status from the block erase flash memory 1 by the processor 10 in FIG.

First, a memory block number to be checked, a read memory block, and a comparison value are initialized (step 901). Next, the data ID of the memory block
Is checked (step 902). Then, it is determined whether the data ID of each memory block matches the data ID to be read (step 903). If they match, the write status of the memory block is checked (step 904), and it is determined whether the memory block is in a write-disabled state (step 905).

If the write status is not in the write-disabled state, it means that the data write has not been completed normally, so it is determined whether or not the data can be written (step 906). The erase counter is checked (step 907), and it is determined whether the check value is greater than the number of comparisons (step 90).
8) If it is larger, the read block number is rewritten to the check block number, the number of comparisons is set as the erasure check value (step 909), and it is determined whether or not all the memory blocks have been checked (step 910). If not checked, the check memory block number is updated (step 911), and step 902 is performed.
And the steps 902 to 911 are repeated for all the memory blocks.

If it is determined in step 905 that the write status is in a write-disabled state, it is considered that the data ID is the latest data and that the write has been completed normally, and the read block number is rewritten to the check block number. (Step 912).

As a result, data is read from the memory block indicated by the read block number where the write status is the data immediately before writing indicated in the writable state.

According to the present embodiment, in writing data to a block erase flash memory, the data write destination dynamically changes to a memory block having a relatively small number of erases, and the latest data is written in any write operation state. This data or the immediately preceding data always exists in the block erase flash memory. Further, the time required for a series of data writing can be reduced. Therefore, as in the conventional writing method of the block erasing type flash memory, the bias of the writing destination memory block or the power supply OF
It is possible to solve the problem that data is lost when the write operation is interrupted by F or the like, and the write time is lengthened to ensure that.

[0050]

According to the present invention, there is provided a semiconductor memory device capable of preventing writing from being biased to a specific memory block and preventing data loss even if processing is interrupted during data writing. be able to.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing contents of a management status writing area of FIG. 1;

FIG. 3 is a diagram showing transition of a write status.

FIG. 4 is a diagram showing a flowchart of writing in FIG. 1;

FIG. 5 is a diagram showing a flowchart of a write destination memory block search in the write of FIG. 1;

FIG. 6 is a diagram showing a flowchart of an erase process of a write destination memory block in the write of FIG. 1;

7 is a diagram showing a flowchart of writing of an erase counter of a write destination memory block in the writing of FIG. 1;

8 is a diagram showing a flowchart of updating the write status of a destination memory block including the same data ID in the write of FIG. 1;

FIG. 9 is a diagram showing a flowchart of reading in FIG. 1;

[Explanation of symbols]

1. Block erase flash memory, 2A to 2E ... memory block, 3A to 3E ... data write area, 4A
４4E: management status writing area, 5A to 5E: data ID writing area, 6A to 6E: erase counter writing area, 7A to 7E: writing status writing area, 8-1: initial writing status, 8-2 ...
Write status write disable state, 8-3 write status write enable state, 10 processor.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) G11C 17/00 601P F term (reference) 5B018 GA04 HA23 KA15 KA18 MA40 NA06 PA10 QA15 5B025 AD04 AD08 AE01 AE05 AE08 5B060 AA02 AA14 CA11 MM14

Claims (11)

[Claims] 1. A memory block having a plurality of erasing units, each memory block having a management status writing area in addition to a data writing area, and specifying data to be written to the data writing area in each management status writing area. Block erase flash in which a data ID to be written, an erase counter indicating the number of erases of a memory block to which data is written, and a write status indicating a chronological order of data written with the same data ID are written as management statuses. A memory, when writing new data, after erasing a memory block of the plurality of memory blocks in which the write status in the management status indicates a writable state and the erase counter indicates a minimum, Write new data and management status to block See
A semiconductor memory device comprising: a processor that updates a management status including the same data ID in another memory block. 2. The semiconductor memory device according to claim 1, wherein said write status indicates one of an initial state, a write disable state, and a write enable state. 3. When the processor writes new data, the write status of a memory block to be written is updated to a write disabled state, and the write status of a memory block indicating the same data ID to be written is set to write. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is updated to an enabled state. 4. The semiconductor memory device according to claim 1, wherein the update of the write status is performed first on a memory block to be written, and then on a memory block indicating the same data ID. . 5. The write status is a state in which a memory block is erased as an initial state, and when the state is a bit, a write disable state is indicated by a state in which at least one or more bits are 0. The writable state is indicated by adding one or more bits 0 to the non-writable state. When the erased state is the bit 0 state, at least one bit is set to one or more bits.
State, and the writable state is changed to the non-writable state.
3. The semiconductor memory device according to claim 2, wherein one or more bits 1 are added. 6. The semiconductor memory device according to claim 3, wherein the update of the write status indicating the same data ID performed when performing a new write is performed without erasing the corresponding memory block. . 7. The semiconductor memory device according to claim 1, wherein when writing new data, the processor writes actual data prior to writing a management status after erasing a corresponding memory block. 8. The semiconductor memory device according to claim 7, wherein the update of the management status is performed last in the update of the write status. 9. The data processing system according to claim 1, wherein the processor increments the erase counter by a constant when writing data.
The semiconductor memory device according to claim 1. 10. When the processor reads data,
Read from the memory block whose data ID matches and the write status is in a write-disabled state. If there is no corresponding memory block, read from the memory block whose data ID matches and the write status is in a writable state. 2. The semiconductor memory device according to claim 1, wherein when there are a plurality of memory blocks indicating a writable state, reading is performed from a memory block having the largest erase counter. 11. The semiconductor memory device according to claim 1, wherein said write status is defined to indicate that data writing to said memory block has been completed normally.