JP2007086369A - Display device and display timing regulation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device for suppressing disturbance of an image caused by displaying image signals having different formats on each screen in a multi-view display device. <P>SOLUTION: The display device has an image output part 70 for outputting the image signals on a display panel, and a TV receiving circuit 340 for being output to the image output part 70 by receiving a second image signal. The TV receiving circuit 340 has a format conversion circuit 343 for converting the signal format of a DTV signal as the second image signal into an EGA type format, and outputting to regulate a cycle of a vertical synchronous signal regulating writing start timing to an image memory 80. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display device capable of visually recognizing images from different directions on a common display panel.

As a multi-view display device capable of visually recognizing images from different directions on a common display screen, for example, a parallax barrier is provided in front of the liquid crystal panel, and the traveling direction of light from the backlight is distributed for each pixel. One that can display different information (images) on the left and right is known (see, for example, Patent Document 1). By mounting such a display device on the vehicle, the passenger in the passenger seat can watch other images such as a television while the driver is watching the navigation image.
JP 2005-78080 A

By the way, in the multi-view display device as described above, signals having different formats such as composite video signals of NTSC system, EGA (Enhanced Graphics Adapter) standard image signals, WVGA (Wide Video Graphics Array) standard image signals, etc. In order to display an image on the driver side screen and the passenger side screen, it is necessary to convert the resolution of the image signal to the resolution of the display panel and to match the output timing of the two image signals to the display panel.
In order to synchronize the output timing of two image signals to the display panel, for example, one image signal is temporarily held in the image memory, and one image is output from the image memory in accordance with the output timing of the other image signal. Read and output the signal.
At this time, the write timing (write address) to the image memory is determined by the difference between the period of the vertical synchronization signal of the image signal written to the image memory and the period of the vertical synchronization signal of the image signal output to the display panel. However, the overtaking process that overtakes the read timing (read address) periodically occurs. When this overtaking process occurs, the displayed image may be disturbed. For example, the vertical synchronization cycle of a DTV (digital television) signal is 16.636 ms, and when this signal is output with a vertical synchronization cycle of 16.683 ms in the NTSC system or the like, a period of about 6.05 seconds is obtained due to a difference of 0.046 ms. May cause image distortion.

  The present invention has been made in view of the above problems, and an object of the present invention is to prevent image disturbance caused by displaying image signals of different formats on each screen in a so-called multi-view display device. An object of the present invention is to provide a display device that can be suppressed.

The display device according to the present invention outputs the first and second image signals and displays the first and second images on a display panel having first and second screens that can be viewed from different visual fields. An image memory that temporarily stores an image signal and an image output that writes the image signal to the image memory and reads the image signal from the image memory in accordance with a predetermined output timing and outputs the image signal to the display panel The circuit includes a circuit and a timing adjustment unit that adjusts and outputs the period of the vertical synchronization signal that defines the timing of starting writing of the image signal to the image memory.
According to this configuration, the write start timing to the image memory is adjusted, and the occurrence of the overtaking process is suppressed.

  In the above structure, the second image signal is an image signal output from the receiving circuit, the second image signal is input to the image output circuit, and the image output circuit matches the output timing of the first image signal. Thus, a configuration in which the second image signal is output to the display panel can be employed.

  In the above configuration, the timing adjustment unit may adopt a configuration in which vertical synchronization signals with different periods are alternately output.

  In the above configuration, the timing adjustment unit can adjust the cycle of the vertical synchronization signal so as to cancel out the time difference between the first image signal and the vertical synchronization signal over a plurality of cycles of the vertical synchronization signal. .

  In the above configuration, the timing adjustment means may employ a configuration provided in the receiving circuit.

  The display timing adjustment circuit according to the present invention outputs first and second image signals to a display panel having first and second screens that can be viewed from different fields of view, and displays the first and second images, respectively. The display timing adjustment circuit in the display device is characterized in that the period of the vertical synchronization signal of the second image signal is adjusted in accordance with the period of the vertical synchronization signal of the first image signal.

  ADVANTAGE OF THE INVENTION According to this invention, in what is called a multi view display apparatus, the disorder of the image resulting from displaying the image signal from which a format differs on each screen can be suppressed.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, exemplary embodiments of the invention will be described with reference to the accompanying drawings.
FIG. 1 is a diagram for explaining a basic configuration of an in-vehicle dual view display device according to an embodiment of the present invention.
As shown in FIG. 1, the in-vehicle dual view display device includes a display control unit 10, a display unit 100 as a display panel, image sources 300A and 300B, and the like.
The display control unit 10 is supplied with the image data (image signal) DT1 from the first image source 300A and the image data (image signal) DT2 from the second image source 300B. The image data (image signal) ADT composed of the image data DT 1 and DT 2 is output to the common display unit 100. A specific configuration of the display control unit 10 will be described later.
The first and second image sources 300A and 300B are composed of a plurality of sources such as a camera, a TV receiving unit, a DVD playback unit, an HD playback unit, and a navigation unit, which will be described later.

  As will be described later, the display unit 100 includes a liquid crystal panel, a backlight, a parallax barrier, and the like, and the first image IM1 based on the first image data DT1 can be viewed from the right by the observer OBR. The second image IM2 based on the second image data DT2 is displayed on the common display screen so that the observer OBL can visually recognize from the left direction. A specific configuration of the display unit 100 will be described later.

  FIG. 2 is an external perspective view of a display device according to an embodiment of the present invention, and FIG. 3 is a perspective view showing an example of mounting on a vehicle according to an embodiment of the present invention.

The apparatus main body 100A of the display device shown in FIG. 2 is built in the dashboard portion of the vehicle, and the display unit 100 is disposed between the driver seat DS and the passenger seat AS as shown in FIG. The display unit 100 is provided with an operation unit 150 for manually operating the display device.
In the case shown in FIG. 3, the occupant seated in the driver seat DS is the observer OBR, and the occupant seated in the passenger seat AS is the observer OBL. These passengers can simultaneously view different first images IM1 and second images IM2 displayed on the display unit 100 from the driver seat DS side or the passenger seat AS side, respectively.

  4 to 8 are diagrams showing a specific configuration of the display device according to the embodiment of the present invention. FIG. 4 is a functional block diagram of the display device, and FIG. 5 is a cross-sectional structure and operation of the liquid crystal panel. FIG. 6 is a front view of the liquid crystal panel, FIG. 7 is a circuit diagram of the TFT substrate, and FIG. 8 is a functional block diagram of the image output unit.

  As shown in FIG. 4, the display device includes a display unit 100, a control unit 20, a distribution circuit 30, first and second image quality adjustment circuits 50A and 50B, an image output unit 70 as an image output circuit, and the like. It is configured. The display control unit 10 includes a control unit 20, a distribution circuit 30, first and second image quality adjustment circuits 50A and 50B, an image output unit 70, and the like.

The control unit 20 includes a processor (CPU), an interface circuit, a ROM, a RAM, and the like, and comprehensively controls the display device according to a program stored in the ROM.
Further, as shown in FIG. 4, the control unit 20 is equipped with a camera 310 that images the surroundings of the vehicle as a supply source that is mounted on the vehicle and supplies images and sounds, and an MD (mini disc) that reproduces music and images. ) Playback unit 320, radio reception unit 330 that receives radio broadcast waves from an antenna, TV reception unit 340 that receives TV broadcast waves from an antenna via a selector 341, CD (compact disc) and DVD (digital versatile disc) CD / DVD playback unit 350 for playing back music information and images from HD, HD playback unit 360 for playing back images and music information recorded on HD (hard disk), road information and GPS information receiving unit received by VICS information receiving unit 371 372 is connected to a navigation unit 370 that outputs a map or a route guidance image based on the received geographic information. , Control these as well as exchange data between these.
Further, the control unit 20 includes a memory 140 for storing various data, an operation unit 150 for operating the display device, and a remote controller for transmitting and receiving infrared signals and radio signals to and from the remote control 171 for operating the display device by remote control. The transmission / reception unit 170, a brightness detection sensor 190 configured to detect the brightness in the vehicle by being configured with a light switch or a light sensor provided in the vehicle, a pressure-sensitive sensor provided in a driver seat or a passenger seat, and the like, An occupant detection sensor 200 to be detected is connected, and the control unit 20 can perform various controls based on various data obtained from these.

As shown in FIG. 4, the distribution circuit 30 is supplied from the camera 310, the MD playback unit 320, the radio reception unit 330, the TV reception unit 340, the CD / DVD playback unit 350, the HD playback unit 360, the navigation unit 370, and the like. Audio data and image data to be input are input. The navigation image data from the navigation unit 370 is output to the first image quality adjustment circuit 50A, and the other image data is output to the second image quality adjustment circuit 50B in response to a control command from the control unit 20. The The audio data is output to the audio adjustment circuit 60.
As shown in FIG. 4, the audio adjustment circuit 60 adjusts the audio data supplied from the distribution circuit 30 and outputs it to the speaker 61.

  The first and second image quality adjustment circuits 50A and 50B are each composed of a contrast adjustment unit, a luminance adjustment unit, a color tone adjustment unit, a gamma value adjustment unit, and the like, and according to a control command from the control unit 20, the first and second image quality adjustment circuits 50A and 50B. The image quality (contrast, brightness, color tone, gamma value) of the second image data is adjusted.

  As shown in FIG. 4, the display unit 100 includes a liquid crystal panel 110, a backlight 120 that illuminates illumination light from the back side of the liquid crystal panel 110, a touch panel 130 for inputting a signal for operating the display device, and the like. . Although not shown, the touch panel 130 is formed in a transparent sheet shape and attached to the front surface of the liquid crystal panel 110.

As shown in FIG. 5, the liquid crystal panel 110 includes a polarizing plate 111, a TFT (Thin Film Transistor) substrate 112, a liquid crystal layer 113, and a color filter substrate having pixels of three primary colors RGB arranged in order from the backlight 120 side. 114, a parallax barrier 115, a glass plate 116, a polarizing plate 117, and the like.
As shown in FIGS. 5 and 6, the liquid crystal panel 110 has a display screen in which, for example, 800 pixels in the horizontal direction and 480 pixels in the vertical direction are arranged. Pixels 118 (hereinafter also referred to as passenger seat side display pixels 118) and right side display pixels 119 (hereinafter also referred to as driver seat side display pixels 119) are alternately arranged.
Therefore, each of the driver's seat side display screen and the passenger seat side display screen has a resolution of 400 × 480 pixels.

As shown in FIGS. 5 and 6, the parallax barrier 115 is formed in a stripe shape and includes a shielding part and a light-transmitting part. The shielding part is formed by the adjacent left display pixel 118 and right display pixel 119. Arranged between. By disposing the parallax barrier 115 on the front surface of the color filter substrate 114, the illumination light transmitted through the left display pixel 118 selectively passes through the light-transmitting part of the parallax barrier 115 selectively toward the left side, and is displayed on the right side. Of the illumination light transmitted through the pixel 119, only the illumination light directed toward the right side selectively passes through the light transmitting portion of the parallax barrier 115. As a result, as shown in FIG. 5, the first image IM1 can be viewed from the right side (driver's seat side) of the liquid crystal panel 110, and the second image IM2 can be viewed from the left side (passenger seat side). ing.
The parallax barrier 115 can be the same as those disclosed in JP-A-10-123461 and JP-A-11-84131.

As shown in FIG. 7, the TFT substrate 112 includes a data line driving circuit DR1, a scanning line driving circuit DR2, scanning lines SCL arranged in the vertical direction, data lines DTL arranged in the horizontal direction, scanning lines SCL and data lines. A pixel electrode EP formed corresponding to the TFT element EL formed in each region intersecting with the DTL is provided, and each region surrounded by the scanning line SCL and the data line DTL constitutes a subpixel SBP. The subpixels SBP in each column along the data line DTL are alternately assigned to the left display pixel 118 and the right display pixel 119.
The data line driving circuit DR1 is controlled in its driving timing by the liquid crystal panel driving unit 74, and controls the voltage applied to the pixel electrode EP.
The scanning line driving circuit DR2 selectively scans the TFT element EL by controlling the driving timing by the liquid crystal panel driving unit 74.

  The memory 140 is configured by, for example, an electrically rewritable nonvolatile memory such as a flash memory or a battery-backed volatile memory, and stores data necessary for control by the control unit 20.

  As shown in FIG. 8, the image output unit 70 includes a plurality of AD (analog / digital) converters AD1 to AD7, a YC separation circuit 71, an RGB decoder 72, a switching circuit 73, and a resolution conversion as a second resolution changing circuit. Circuit 74, writing circuit 75, reading circuit 76, pixel interpolation circuit 77 as a first resolution changing circuit, output timing control circuit 78, memory IF 79, VRAM 80, C / B adjustment circuit 81, RGB rearrangement circuit 82, gamma The image output unit 70 includes a table 83, a gamma correction circuit 84, a TFT timing control circuit 85, and the like, and is formed by, for example, an ASIC (Application Specific Integrated Circuit).

The AD converter AD1 synchronizes the YC signal (luminance signal and color signal) of the CV (composite video) signal composed of the analog signal input from the second image quality adjustment circuit 50B in synchronization with the clock signal CLK1 (for example, 13 MHz). By sampling, it is converted into a digital signal, which is output to the YC separation circuit 71.
The CV signal has a resolution of 720 × 240 (dots) and is composed of a YC signal and a composite synchronization signal CSYNC1, and the composite synchronization signal CSYNC1 is also input to the image output unit 70. The composite synchronization signal CSYNC1 is a signal including a vertical synchronization signal component and a horizontal synchronization signal component. The CV signal is composed of an analog television signal from the TV receiver 340 and a signal obtained from the CD / DVD reproducing unit 350. Further, the clock signal CLK1 is supplied from a voltage controlled oscillator VCO1 provided outside the image output unit 70.

The AD converters AD2 to AD4 convert the R, G, and B signals of the EGA signal composed of analog signals input from the second image quality adjustment circuit 50B into digital signals by sampling in synchronization with the clock signal CLK1. This is output to the switching circuit 73.
The EGA signal has a resolution of 400 × 240 (dots) and is composed of R, G, B signals and a composite synchronization signal CSYNC2, and the composite synchronization signal CSYNC2 is also input to the image output unit 70. The composite synchronization signal CSYNC2 is a signal including a vertical synchronization signal component and a horizontal synchronization signal component. The EGA signal is a signal formed by resizing a DTV (digital television) signal obtained from the TV receiver 340, for example.

The AD converters AD5 to AD7 sample the R, G, and B signals of the WVGA signal that is an analog signal input from the first image quality adjustment circuit 50A in synchronization with the clock signal CLK2 (for example, 33.231 MHz). Convert to digital signal.
The WVGA signal has a resolution of 800 × 480 (dots) and is obtained from the navigation unit 370. The clock signal CLK2 is supplied from a voltage controlled oscillator VCO2 provided outside the image output unit 70.

The YC separation circuit 71 separates the YC signal of the CV signal into a Y (luminance) signal and a C (color) signal and outputs them to the RGB decoder 72.
The RGB decoder 72 converts the Y signal and C signal into R, G, B signals and outputs them to the switching circuit 73.
The switching circuit 73 selectively selects one of the R, G, B signals of the CV signal and the R, G, B signals of the EGA signal to the resolution conversion circuit 74 in accordance with the switching signal SEL input from the control unit 20. Output.

  The resolution conversion circuit 74 calculates the resolution of the R, G, and B signals of the CV signal or EGA signal so as to be the resolution (400 × 480) of the liquid crystal panel 110 and outputs it to the writing circuit 75. That is, the resolution conversion circuit 74 is formed to be able to change the resolution of the input image signal in accordance with each signal format.

  The VRAM 80 is a memory for temporarily holding R, G, B signals of CV signals or EGA signals, and for example, SDRAM (Synchronous DRAM) is used. The VRAM 80 has an area M1 and an area M2, and image signals are alternately written into the areas M1 and M2, and image signals are read from areas of the areas M1 and M2 where no image signals are being written. And output to the display panel 110.

  The write circuit 75 latches data (R, G, B signals) to be written to the VRAM 80 in synchronization with the composite sync signal CSYNC1 or CSYNC2 of the CV signal or EGA signal. Specifically, the writing circuit 75 starts writing to the VRAM 80 in synchronization with the vertical synchronizing signal of the composite synchronizing signal, and alternately writes image signals to the areas M1 and M2 of the VRAM 80 for each screen.

  The read circuit 76 latches data read from the VRAM 80 at the output timing of the WVGA signal. Specifically, the reading circuit 76 starts reading from the areas M1 and M2 of the VRAM 80 in synchronization with the vertical synchronizing signal of the WVGA signal (vertical synchronizing signal of the display panel 100) and alternately outputs an image signal for each screen. read out. In addition, when reading of the image signal for one screen is completed by the writing circuit 75 during reading of the image signal, the reading circuit 76 stops reading the current area and starts reading the other area. To do.

  The pixel interpolation circuit 77 performs pixel interpolation on the WVGA signal (R, G, B signal) having a resolution of 800 × 480, resizes the resolution to 400 × 480, and outputs it to the RGB rearrangement circuit 82.

The output timing control circuit 78 is a circuit that generates timing for outputting an image to the display unit 100 (liquid crystal panel 110) based on the clock signal CLK2.
The memory IF 79 is a circuit that controls access to the VRAM 80 and writes the data latched in the write circuit 75 to the VRAM 80 in synchronization with the input timing of the CV signal or EGA signal, and in synchronization with the output timing of the WVGA signal. The data is read from the VRAM 80 and output to the C / B adjustment circuit 81.

  The C / B adjustment circuit 81 adjusts the image quality of the image composed of the R, G, and B signals of the CV signal or EGA signal temporarily held and read by the VRAM 80 and outputs the adjusted image quality to the RGB rearrangement circuit 82.

The RGB rearrangement circuit 82 rearranges the pixel data from the pixel interpolation circuit 77 and the C / B adjustment circuit 81 for two-screen display and outputs the rearranged pixel data to the gamma correction circuit 84.
The gamma correction circuit 84 is a circuit that linearly performs gamma correction in units of R, G, and B in accordance with the characteristics of the liquid crystal panel 110.
The gamma table 83 is a memory for holding a table value for gamma correction.
The TFT timing control circuit 85 is a circuit that outputs image data in accordance with the drive timing of a circuit formed on the TFT substrate 112 of the liquid crystal panel 110.

Here, FIG. 9 is a functional block diagram showing a configuration for receiving a DTV (digital television) of the TV receiver. The TV receiver 340 also includes an analog television receiver circuit (not shown).
In FIG. 9, a TV receiver 340 includes a detection circuit 342, a timing adjustment unit, a format conversion circuit 343 as a display timing adjustment circuit, and the like.
The detection circuit 342 detects the DTV signal received by the antenna and outputs it to the format conversion circuit 343.
The format conversion circuit 343 resizes the DTV signal obtained by detection,
The signal is converted into an EGA standard signal, and the period of the vertical synchronizing signal is adjusted and output to the image output unit 70. At this time, the format conversion circuit 343 converts the progressive DTV signal into an interlaced signal.

Next, a method of adjusting the period of the vertical synchronization signal by the format conversion circuit 343 will be described with reference to FIG.
Here, FIG. 10A is a timing chart of the vertical synchronizing signal of the display panel 100, and FIG. 10B is a timing chart of the vertical synchronizing signal of the DTV signal in the TV receiving unit 340. FIG. These are timing charts of the vertical synchronization signal of the EGA signal output from the format conversion circuit 343.
As shown in FIG. 10A, the period of the vertical synchronizing signal of the display panel 100 (WVGA) is 16.683 ms (262.5H). In the WVGA standard, 262. Five horizontal synchronization signals are output.
On the other hand, when the DTV signal is converted into an interlace format signal, as shown in FIG. 10B, one cycle of the vertical synchronization signal is 16.636 ms (262H), and the vertical direction of the display panel 100 (WVGA) A difference of about 0.046 ms occurs with respect to the period of the synchronization signal.
If writing and reading to / from the VRAM 80 are executed in the presence of this difference, an overtaking process occurs in which the write timing exceeds the read timing approximately every 6.05 seconds.

For this reason, the format conversion circuit 343 outputs the vertical synchronizing signals alternately at 262H and 263H as shown in FIG. 10C. That is, the period of the vertical synchronizing signal is alternately changed and output to the image output unit 70. As a result, the average period of the vertical synchronization signal is 262.5H.
Thereby, the difference between the write cycle of the write circuit 75 to the VRAM 80 and the read cycle of the read circuit 76 from the VRAM 80 is suppressed, and the occurrence of periodic disturbance of the image displayed on the screen can be suppressed.

  As described above, according to the present embodiment, the period of the vertical synchronization signal of the second image signal before being input to the image output unit 70 is adjusted together with the format conversion in the format conversion circuit 343 of the TV receiving unit 340. As a result, it is possible to suppress the disturbance of the display image caused by the format difference between the image signals.

In the above embodiment, the case where the average period is adjusted by alternately changing the period of the vertical synchronization signal has been described. However, the period of the vertical synchronization signal may be changed from 262H to 262.5H.
Moreover, in the said embodiment, although the vertical synchronizing signal of a WVGA signal is adjusted on average between two periods, if it is the range by which disturbance of an image is suppressed, the structure which adjusts timing over three periods or more, It is also possible to do.

  In the above embodiment, the TV receiver 340 includes the timing adjustment unit and the display timing adjustment circuit. However, the present invention is not limited to this, and the TV receiver 340 may be provided in addition to the TV receiver 340.

  In the above embodiment, the case where a liquid crystal panel is used for the display unit 100 has been described. However, the present invention is not limited to this, and a flat panel display other than the liquid crystal panel, for example, an organic EL display panel, a plasma display panel, a cold cathode A flat panel display or the like can also be used.

  The above embodiment is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.

It is a figure for demonstrating the basic composition of the display apparatus which concerns on one Embodiment of this invention. It is an external appearance perspective view of a display apparatus. It is a perspective view which shows the example of application to the vehicle of a display apparatus. It is a functional block diagram which shows the structure of a vehicle-mounted display apparatus. It is a figure which shows the cross-section of a display part. It is a front view of a liquid crystal panel. It is a circuit diagram of a TFT substrate. It is a functional block diagram which shows the structure of an image output part. It is a functional block diagram which shows the structure for receiving DTV of a TV receiving part. It is a figure for demonstrating the adjustment method of the period of the vertical synchronizing signal by a format conversion circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Display control part 20 ... Control part 30 ... Distribution circuit 50A, 50B ... 1st and 2nd image quality adjustment circuit 60 ... Audio | voice adjustment circuit 70 ... Image output part 71 ... YC separation circuit 72 ... RGB decoder 73 ... Switching circuit 74 ... Resolution conversion circuit 75 ... Write circuit 76 ... Read circuit 77 ... Pixel interpolation circuit 78 ... Output timing control circuit 79 ... Memory IF
80 ... VRAM
81 ... C / B adjustment circuit 82 ... RGB rearrangement circuit 83 ... Gamma table 84 ... Gamma correction circuit 85 ... TFT timing control circuit 100 ... Display unit (display panel)
DESCRIPTION OF SYMBOLS 100A ... Main body 110 ... Liquid crystal panel 120 ... Backlight 130 ... Touch panel 140 ... Memory 150 ... Operation part 170 ... Remote control transmission / reception part 190 ... Brightness detection sensor 200 ... Occupant detection sensor 300A, 300B ... Image source 310 ... Camera 320 ... MD Playback unit 330 ... radio reception unit 340 ... TV reception unit 341 ... selector 342 ... detection circuit 343 ... format conversion circuit (timing adjustment means, display timing adjustment circuit)
350 ... CD / DVD playback unit 360 ... HD playback unit 370 ... navigation unit

Claims (6)

A display device for displaying first and second images by outputting first and second image signals to a display panel having first and second screens that can be viewed from different fields of view, respectively.
An image memory for temporarily storing image signals;
An image output circuit for writing the image signal to the image memory and reading the image signal from the image memory in accordance with a predetermined output timing and outputting the read image signal to the display panel;
Timing adjusting means for adjusting and outputting a period of a vertical synchronizing signal defining a timing for starting writing of the image signal to the image memory;
A display device comprising: The second image signal is an image signal output from a receiving circuit,
The second image signal is input to the image output circuit;
The image output circuit outputs the second image signal to the display panel in accordance with an output timing of the first image signal;
The display device according to claim 1.   The display device according to claim 1, wherein the timing adjustment unit alternately outputs the vertical synchronization signals having different periods.   The timing adjustment means adjusts and outputs the period of the vertical synchronization signal so as to cancel out a time difference between the vertical synchronization signal of the first image signal and a plurality of periods of the vertical synchronization signal. The display device according to claim 1.   The display device according to claim 2, wherein the timing adjusting unit is provided in the receiving circuit. A display timing adjustment circuit in a display device for displaying first and second images by outputting first and second image signals to a display panel having first and second screens that can be viewed from different visual fields. And
A display timing adjustment circuit, wherein a period of a vertical synchronization signal of the second image signal is adjusted in correspondence with a period of a vertical synchronization signal of the first image signal.

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