JP2007080854A - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can increase accumulation charge capacity and is suitable for micro fabrication, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device is provided with a second capacitor which is formed by providing an upper electrode 540, on the upper side of a first electrode 520 (surface strap) electrically connecting a source diffused layer S of a MOS transistor and a storage electrode 330 of a deep trench capacitor C<SB>DT</SB>, by means of a second insulating film 530. In this case, the upper electrode 540 is connected with a plate electrode 320 of the deep trench capacitor C<SB>DT</SB>in the periphery of elements, thus increasing accumulation charge capacity. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a DRAM (Dynamic Random Access Memory) or a DRAM mixed device having a DRAM function and a device suitable for the manufacturing method thereof.

  The DRAM is composed of one transistor (T) and one capacitor (C), and stores information by accumulating electric charge in the capacitor. In recent years, with the miniaturization and integration of DRAMs, the capacitor area per unit memory cell is also miniaturized. In order to operate the DRAM stably, it is necessary to secure a sufficient capacity of the capacitor, but the accumulated charge capacity of the capacitor tends to be reduced due to miniaturization of the memory cell. In a DRAM including a trench type capacitor, the trench diameter of the capacitor is miniaturized, but the depth of the trench has a processing limit. Therefore, in order to ensure the capacity, such as the miniaturization of memory cells accompanying the integration of DRAMs and the introduction of a high dielectric material into the capacitor insulating film. However, it is predicted that it will be difficult to form a capacitor having a sufficient capacity even if the above-described device is applied due to further miniaturization.

Therefore, there is a method to secure the accumulated charge capacity by combining the trench type capacitor and the stack type capacitor, but in order to form the stack type capacitor in addition to the trench type capacitor, processes such as lithography and etching are drastically performed. Increasing, the structure becomes complicated and the production cost increases. (For example, refer to Patent Document 1).
JP 2005-79281 A

  The present invention provides a semiconductor device suitable for miniaturization by increasing the accumulated charge capacity and a method for manufacturing the same.

  One aspect of the present invention includes a semiconductor substrate, a plate electrode made of a diffusion layer in the semiconductor substrate, a storage node electrode formed in a trench reaching the plate electrode from the surface of the semiconductor substrate, the plate electrode, A trench capacitor comprising a first insulating film for insulating the storage node; a gate electrode provided on the substrate; a first diffusion layer extending along the substrate from the gate electrode toward the trench; and the gate A second diffusion layer extending on the opposite side of the first diffusion layer across an electrode; and a substrate on the first diffusion layer, the first diffusion layer and the storage node electrode being electrically connected A surface strap to be connected to each other, and the surface strap as a first electrode, and an upper portion formed on the first electrode via a second insulating film It is characterized in that it comprises a second capacitor consisting of poles.

  According to one embodiment of the present invention, a step of forming an element isolation region in a semiconductor substrate, a step of forming a trench groove in the semiconductor substrate, and a plate electrode are formed by diffusing impurities on the bottom substrate side of the trench groove. Forming a first insulating film in the trench groove; forming a storage node electrode in the trench groove; forming a gate electrode; and first and second diffusion layers. Forming, a step of forming a surface strap on the substrate above the first diffusion layer, a step of forming a second insulating film on the surface strap, and an upper electrode on the second insulating film And a step of forming a bit line contact and a bit line.

  According to the present invention, it is possible to provide a semiconductor device suitable for miniaturization and a method for manufacturing the same by increasing the accumulated charge capacity.

  Examples according to the present invention will be described below.

  A first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a plan view schematically showing a configuration of a semiconductor memory device according to Embodiment 1 of the present invention. A deep trench DT in which the first capacitor is formed and a channel region CA in which the gate electrode is formed are adjacent to each other in a region where the word line WL and the bit line BL intersect, and is sandwiched between the channel region CA and the deep trench DT. A surface strap region SS is formed on the bit line. A surface strap capacitor is formed in the surface strap region SS. A bit line contact BC is formed on the bit line opposite to the surface strap region SS across the channel region CA, and one element is formed. The area of the element according to this configuration is expressed as 8F ² using the minimum processing dimension F. Elements adjacent in the bit line direction share a bit line contact. Thereby, the deep trenches of the elements adjacent in the bit line direction are adjacent to each other via the element isolation region. In addition, elements adjacent in the word line direction are arranged with a phase of one element. Further, a contact of a plate line PL is formed in the peripheral portion of the element.

  FIG. 2 is a cross-sectional configuration diagram showing a cross section taken along line Aa in FIG. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, and the thickness and ratio of each layer are different from the actual ones.

As shown in FIG. 2, the semiconductor memory device according to the first embodiment includes a deep trench capacitor C _DT for information storage formed on a semiconductor substrate 100 made of, for example, p-type silicon, and information formed on the substrate. It consists of a transfer MOS transistor.

Depth 6μm about deep trench capacitor _{C DT} consists storage electrode 330 formed of the plate electrode 320, capacitor insulating film 325 and the conductive type polysilicon. Adjacent deep trench capacitors C _DT are isolated from each other by an element isolation region 430. The plate electrode 320 may not be provided. In this case, when a voltage is applied to the storage electrode 330, a plate electrode corresponding to the deep trench capacitor _CDT of the p-type silicon substrate 100 is formed. A sidewall oxide film 340 made of, for example, a silicon oxide film is formed on the upper side surface of the deep trench capacitor _CDT .

The MOS transistor T includes a gate insulating film 110 formed on a p-type silicon substrate 100, a gate electrode 450 formed on the gate insulating film 110, and a source diffusion region S extending from the gate electrode to the deep trench capacitor side. The drain diffusion region D extends to the side. The source diffusion region S of the MOS transistor T is electrically connected to the storage electrode 330 via a first electrode (surface strap) 520 formed on the substrate. The first electrode (surface strap) 520 is made of conductive polysilicon, for example. The drain diffusion region D is connected to the bit line BL via the bit line contact 570. As a result, the MOS transistor T can transfer the information stored in the deep trench capacitor _CDT to the bit line BL. Here, the bit line BL and the bit line contact 570 may be formed at the same time.

Surface strap to the first electrode 520, the the upper are formed surface strap capacitor C _SS is formed the upper electrode 540 via an insulating film. Upper electrode 540 of the surface strap capacitor C _SS, such as the ends of the elements are electrically with the plate electrode 320 in the substrate (not shown) connected, it is kept at the same potential as the plate electrode 320 is connected to a plate line PL ing. Further, the sidewall oxide film on the side where the first electrode (surface strap) 520 and the source diffusion layer region are in contact with each other at the upper end of the trench is not formed, and the source diffusion layer region S and the first electrode (surface strap) 520 are formed. In addition, the storage electrode 330 is in direct contact. As a result, the contact resistance between the first electrode (surface strap) 520 and the storage electrode 330 is further suppressed.

It will be described with reference to FIG. 3 a circuit including a deep trench capacitor C _DT and surfaces strap capacitor C _SS. Upper electrode 540 of the plate line PL and the surface strap capacitor _{C ss} of the trench capacitor _{C DP} are electrically connected. The lower electrode 520 of the storage electrode 330 and the surface strap capacitor _{C SS} of the deep trench capacitor _{C DT} are electrically connected, it is connected to the bit line BL via the MOS transistor T. As a result, the total charge storage capacity can be increased by providing the surface strap capacitor _Css . When a silicon nitrogen oxide base film is used as the capacitor insulating film of the surface strap capacitor C _ss , the effect of increasing the capacity by about 10% to about 30% compared to the capacity consisting of only the capacitor of the deep trench capacitor C _DT. is there. Further, when a mixed film of an aluminum oxide film and a hafnium oxide film having a relative dielectric constant of about 11 to 30 is used for the surface strap capacitor C _ss insulating film, the total capacity is increased by about 20% to about 70%. effective. Furthermore, since the total capacity can be increased, the data retention characteristics can be improved and the write / read operation speed can be improved.

  Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

  Each of FIGS. 4 to 23 is a sectional view taken along the line Aa in FIG. 1, that is, a sectional view showing a manufacturing process in the section along the bit line.

  First, a silicon oxide film 110a is deposited and formed on the main surface of the p-type silicon substrate 100, for example, by thermal oxidation to a thickness of about 2 nm, for example. Further, a silicon nitride film 200 is deposited on the silicon oxide film 110a to a thickness of about 100 nm, for example. On the silicon nitride film 120, a BSG film 210 serving as a mask material is formed in order of about 1600 nm, a hard mask film 220 is formed about 700 nm, and an SOG (Spin on Glass) film 230 is formed about 10 nm.

  Further, a resist 240 is applied on the SOG film 230, and a mask pattern for forming a deep trench is formed on the resist 240 by an ordinary photoresist method. Note that the hard mask film 220 and the SOG film 230 are used to accurately etch the BSG film 210 (see FIG. 4).

  Next, using the resist 240 as a mask, the SOG film 230, the hard mask film 220, the BSG film 210, the silicon nitride film 200, and the silicon oxide film 110 are sequentially etched by RIE (Reactive Ion Etching), for example, to form a deep trench. A mask for forming is formed. (See FIG. 5).

  Subsequently, using this mask, the substrate 100 is etched by the RIE method or the like to form the deep trench groove 300. (See FIG. 6). Further, post cleaning is performed. Here, the depth of the deep trench groove 300 is, for example, about 6 μm to 7 μm. Thereafter, the resist 240, the SOG film 230, the hard mask film 220, and the BSG film 210 are removed.

Next, a capacitor insulating film 325 made of, for example, a silicon oxide film is formed on the deep trench inner wall. Here, the capacitor insulating film 325 may be a silicon nitride film or a silicon nitrogen oxide film. In addition, it is preferable to use an aluminum oxide film, a hafnium oxide film, a mixed film or a laminated film, etc., having a relative dielectric constant higher than that of a silicon oxide film, because the electric capacity can be further increased. Subsequently, a sidewall oxide film 340 made of, for example, a silicon oxide film is formed on the deep trench inner wall. (See Figure 7)
Next, the bottom of the deep trench pit 300 is etched by about 30 nm using, for example, a CDE (Chemical Dry Etching) method to widen the bottom of the deep trench DT. (Not shown). Subsequently, As (arsenic) or P (phosphorus) is adsorbed and diffused in the deep trench DT by using a solid layer diffusion method, and an n + type diffusion region is formed in the silicon substrate 11. A vapor phase diffusion method may be used instead of solid layer diffusion. This n + type diffusion region becomes the plate electrode 320 of the deep trench capacitor _CDT .

  Subsequently, a capacitor insulating film (not shown) is formed along the inner wall of the bottom of the deep trench groove 300. This becomes a capacitor insulating film of the deep trench capacitor.

Next, a polysilicon layer 330 a is embedded in the deep trench groove 300. Polysilicon 330a within the trench is a storage electrode 330 of the deep trench capacitor _{C DT.} Thereafter, the upper surface is planarized by, for example, a CMP method. (See FIG. 8).

  Next, a TEOS film 410 is deposited to a thickness of, for example, about 550 nm by a CVD (Chemical Vapor Deposition) method using TEOS (Tetra Ethyl Ortho Silicate) as a reaction gas. Further, a hard mask 420 made of an insulating film is formed on the TEOS film 410 to a thickness of about 300 nm, for example. (See FIG. 9). These hard mask films 420 are for accurately forming trenches in the TEOS film in a later step.

  Next, a photoresist (not shown) is applied on the hard mask film 420, and exposure and development are performed to form a pattern on the resist. This pattern is used to form an element isolation region in a later process. The width of the element isolation region and the distance between adjacent element isolation regions differ depending on the memory capacity and generation of the DRAM. For example, the width of the element isolation region is 70 to 110 nm, and the distance between adjacent element isolation regions is 45 to 110 nm. Place with.

  Next, using the resist as a mask, the hard mask film 420 and the TEOS film 410 are sequentially etched by the RIE (Reactive Ion Etching) method or the like to form the groove 425. (See FIG. 10).

  Subsequently, using the hard mask 420 as a mask, the substrate 100 is etched using an RIE method or the like to form an element isolation groove 435 for forming an element isolation region having a width of about 30 nm to 130 nm and a depth of about 250 nm. (See FIG. 11). Thereafter, the resist and hard mask 420 are removed.

Subsequently, an oxide film is formed on the inner wall of the element isolation trench 435 by, for example, thermal oxidation. (Not shown). Further, after embedding the SiO ₂ film by, for example, the CVD method, the surface is flattened by the CMP method. The element isolation region 430 is formed by the above process. (See Figure 12)
Next, the process for forming the transistor T is started. First, the gate electrode 450 is deposited on the silicon insulating film 110a to be the gate insulating film 110, and, for example, a tungsten silicide 460, a silicon nitride film 470, and the like are sequentially deposited thereon. Further, a resist (not shown) is formed thereon, and is patterned by a normal photoresist method to form a transistor gate structure.

  Next, a silicon nitride film is deposited on the entire upper surface of the gate electrode, and the entire surface is etched back by, for example, the RIE method. By this step, a gate sidewall 480 made of a nitride film is formed on the sidewall of the gate electrode. (See FIG. 13).

  Here, As (arsenic) or P (phosphorus), for example, is introduced into the silicon substrate 100 by ion implantation as impurity ions having a conductivity type opposite to that of the substrate 100. After that, by diffusing by annealing, a source region S and a drain region D which are transistor activation regions are formed. . Next, an interlayer film 500 which is an insulating film is deposited by, for example, about 220 nm by, for example, CVD, and the surface of the interlayer film 500 is planarized by, for example, CMP.

  Next, a resist (not shown) is applied on the interlayer film 500, and a pattern is formed so that the resist forms an opening in the source diffusion region S by a normal photoresist method. Next, using the resist as a mask, the interlayer film 500 is etched by, for example, the RIE method to form the groove 505. At this time, the sidewall oxide film 340 of the deep trench and a part of the upper end portion of the storage electrode 330 are removed. Thereafter, the resist is removed. (See FIG. 14).

  Next, polysilicon 540 is deposited so as to completely fill the groove 505. At this time, the polysilicon 540 may be a conductive polysilicon film to which impurities are added in advance. For example, amorphous silicon may be deposited and then impurities may be added from the solid phase or gas phase. The conductive polysilicon film thus formed is formed so as to be in electrical contact with the upper surface of the source region S and the storage electrode 330. (See FIG. 15). This polysilicon portion becomes the surface strap region SS.

Here, the process of forming the second capacitor in the surface strap region SS is started. First, a part of the polysilicon 540 formed in the surface strap region SS is etched. (See FIG. 16). Polysilicon left at this time is the first electrode 520 of the surface strap capacitor C _SS. At this time, for etching polysilicon, a resist may be applied and a normal photolithography method may be used, or a recess method may be used without using the photolithography method. When the recess method is used, the lithography process is not increased and the process can be simplified. Here, the recess method refers to a method of performing etching using the RIE method after planarizing the surface by the CMP method. Alternatively, a method of removing a part of the surface using an RIE method or a wet etching method can be used. By using these methods to make the upper surface of the first electrode 520 convex downward, the electrode area of the surface strap capacitor Css is increased, thereby increasing the electric capacity.

Subsequently, heat treatment is performed in a gas atmosphere containing nitrogen to nitride the surface of the groove formed on the polysilicon, and an insulating film 530 made of a silicon nitride film or a silicon nitrogen oxide film is formed in the surface region. (See FIG. 17). At this time, a gas containing NO, N ₂ O, or ammonia can be used as the gas containing nitrogen. As another method, a method of exposing to nitrogen radicals formed by exciting nitrogen gas can be used. A silicon nitride film can also be deposited. Furthermore, a method of forming a plurality of laminated structures composed of a silicon nitride film and a silicon oxide film, and the above methods can be appropriately combined. This insulating film becomes the capacitor insulating film 530 of the surface strap SS.

Subsequently, polysilicon doped with impurities is deposited so as to completely fill the trench on the capacitor insulating film 530, and the surface is planarized using a CMP method or the like. At this time, polysilicon may be deposited and impurities may be added by heat treatment, or amorphous silicon or polysilicon to which impurities are not added may be deposited, and then impurities may be diffused from the gas phase or solid phase. The polysilicon is an upper electrode 520 of the surface strap capacitor _{C SS.} (See FIG. 18). The upper electrode 520 is electrically connected to the plate line PL at a cell end (not shown).

  Next, an interlayer film 560 made of an SOG film is deposited over the entire surface, and the surface of the interlayer film 560 is planarized by, eg, CMP. (See FIG. 19). Note that a BPSG film or the like can be used for the interlayer film 560.

  Next, a bit line contact forming process is started. First, a resist (not shown) is deposited on the interlayer film 560, and a mask is formed so as to provide an opening above the drain diffusion layer region D of the transistor. Using this mask, the interlayer film 560, the polysilicon film 520 which is a part of the upper electrode, the interlayer film 500, and the polysilicon film 540 are sequentially etched to form a bit line contact groove 575. (See FIG. 20).

  Next, a spacer insulating film 580 is deposited on the entire surface including the inner wall of the bit line contact groove 575. This spacer insulating film 580 is formed to insulate the bit line contact from the surroundings. (See FIG. 21).

  Next, the spacer insulating film 580 deposited on the interlayer film 560 is removed by etching. (See FIG. 22).

  Next, a conductor made of tungsten or the like is embedded in the bit line contact groove 575 to form the bit line contact 570. Further, a bit line BL is formed in the upper part. (See FIG. 23). At this time, the bit line contact is electrically connected to the drain diffusion region D. Further, the bit line contact 570 and the bit line BL may be formed continuously. Through the above manufacturing process, the DRAM structure shown in FIG. 23 is formed.

  In this way, by adding a very simple process to the conventional deep trench capacitor type DRAM process, in addition to the deep trench capacitor, a second capacitor is formed in the surface strap portion, thereby increasing the total capacitor capacity. The data retention characteristics can be improved, and the write / read operation speed can be improved.

In this embodiment, the insulating film surfaces strap capacitor C _SS has been described convex shape in the lower, and a flat shape in forming the lower electrode as shown in FIG. 24, the insulating film on the surface thereof Can also be formed. Also, as shown in FIG. 25, the same effect can be obtained even if the lower electrode is convex. Furthermore, as shown in FIG. 26, for example, the upper surface of the capacitor insulating film may be higher than the silicon nitride film 470 on the gate electrode. In order to form the lower electrode in such a convex shape, for example, by adding an impurity such as arsenic to a part of the lower electrode in advance, the etching rate at both ends compared to the central part of the lower electrode Can be used to speed up.

  In the manufacturing method of the present embodiment, the capacitor insulating film formed in the surface strap region SS is based on a silicon nitrogen oxide film, but a so-called high dielectric film such as an aluminum oxide film or a hafnium oxide film can also be used. In this case, since the high dielectric film has a relative dielectric constant that is about 2 to 8 times higher than that of the silicon nitrogen oxide film, when a capacitor insulating film having the same surface area is formed, the capacitance is 2 to 8 times. It becomes possible to make it about twice as high. Alternatively, a film in which a silicon oxide film, an aluminum oxide film, a hafnium oxide film is mixed, a film in which these films are stacked, or a film in which nitrogen is further added to these films can be used.

1 is a diagram showing a cross-sectional structure of a semiconductor memory device according to Example 1 of the invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor memory device concerning Example 1 of this invention. 1 is a cross-sectional view showing a semiconductor memory device according to Embodiment 1 of the present invention. 1 is a cross-sectional view showing a semiconductor memory device according to Embodiment 1 of the present invention. 1 is a cross-sectional view showing a semiconductor memory device according to Embodiment 1 of the present invention.

Explanation of symbols

WL word line BL bit line DT deep trench CA channel region SS surface strap region BC bit line contact PL plate line C _DT deep trench capacitor C _SS surface strap capacitor T MOS transistor S source diffusion region D drain diffusion region 100 substrate 110 gate insulating film 110a Silicon oxide film 200 Silicon nitride film 210 BSG film 220 Hard mask film 230 SOG film 240 Resist 300 Deep trench groove 320 Plate electrode 325 Capacitor insulating film 330 Storage electrode 330a Polysilicon 340 Side wall oxide film 410 TEOS film 420 Hard mask 425 Groove 430 Element isolation region 435 Element isolation region groove 440 Polysilicon 450 Gate electrode 460 Tungsten silicide 47 0 Silicon nitride film 480 Gate sidewall 500 Interlayer film 505 Groove 515 Surface strap (SS) region 520 520a to 520c First electrode (surface strap)
530 Second insulating film 530a to 530c Second insulating film 540 Upper electrode 540a to 540c Upper electrode 560 Interlayer film 570 Bit line contact 575 Bit line contact groove 580 Spacer insulating film 590 Bit line

Claims (5)

A semiconductor substrate;
A plate electrode formed of a diffusion layer in the semiconductor substrate, a storage node electrode formed in a trench reaching the plate electrode from the surface of the semiconductor substrate, and a first insulating film that insulates the plate electrode and the storage node A trench capacitor,
A gate electrode provided on the substrate;
A first diffusion layer extending along the substrate from the gate electrode toward the trench;
A second diffusion layer extending on the opposite side of the first diffusion layer across the gate electrode;
A surface strap formed on the substrate above the first diffusion layer and electrically connecting the first diffusion layer and the storage node electrode;
A semiconductor memory device comprising: the surface strap as a first electrode; and a second capacitor comprising an upper electrode formed on the first electrode via a second insulating film. The semiconductor memory device according to claim 1, wherein the upper electrode is electrically connected to the plate electrode. 2. The semiconductor memory device according to claim 1, wherein the second insulating film has a shape in which a central portion is depressed downward. 2. The second insulating film includes at least one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, an aluminum nitride film, a hafnium oxide film, a hafnium nitride film, and a tantalum oxide film. The semiconductor memory device described. Forming an element isolation region in a semiconductor substrate;
Forming a trench groove in the semiconductor substrate;
Diffusing impurities on the bottom substrate side of the trench groove to form a plate electrode;
Forming a first insulating film in the trench groove;
Forming a storage node electrode in the trench groove;
Forming a gate electrode;
Forming first and second diffusion layers;
Forming a surface strap on the substrate above the first diffusion layer;
Forming a second insulating film on the surface strap; and
Forming an upper electrode on the second insulating film;
And a step of forming a bit line contact and a bit line.

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