JP2007080025A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of signal lines by sharing a bus used for data transfer from an external I/F and a bus connected with a memory used by a CPU of a device. <P>SOLUTION: In this data transfer device, the CPU 2 is connected to a local bus controller 5 via a CPU bus 12, and a DMAC 3 is connected to the local bus controller 5 via a DMA bus 13. The local bus controller 5 is connected to an external local bus 11, the local bus 11 is connected with an external I/F controller 8, a code ROM 9, and a font ROM 10, and the local bus 11 is shared as the bus used for the data transfer from the external I/F and the bus connected with the code ROM 9 used by the CPU. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer device, and more particularly to a data transfer device that transfers a large amount of data.

  With the widespread use of personal computers (PCs), the spread of various peripheral devices has progressed, making functional differentiation difficult, and cost reduction being a major point. On the other hand, a system including a microcomputer is mounted on a peripheral device of the PC. In such an embedded microcomputer system, it is important to efficiently bring out the performance of the mounted key parts, and depending on the design, high performance can be realized at low cost.

  Here, regarding a data transfer apparatus (data transfer system) that transfers a large amount of image data from a PC, such as an image forming apparatus typified by a printer, a conventional system is provided with a dedicated bus for transferring image data. In addition, a bus that is separate from the memory used by other processor programs is divided to constitute an optimum system for data transfer that is not affected by the bus.

  An example of such a data transfer apparatus will be described with reference to FIG. This apparatus includes a main ASIC 501 for controlling the apparatus. The ASIC 501 includes modules of a CPU (processor) 502, a DMA controller (DMAC: Direct Memory Access Controller) 503, and a local bus controller 505. The local bus controller 505 is connected via a CPU bus 511. Further, a memory 504 for storing image data is connected to the ASIC 501, and an external I / F (interface) controller 508 is connected via the DMA bus 507. Further, the local bus controller 505 is connected to an external local bus 506, and a code ROM 509 and a font ROM 510 are connected to the local bus 506.

  In this apparatus, a program is executed by the CPU 502 in the ASIC 501. This program is read from the code ROM 509 via the local bus controller 505 and the local bus 506 and executed. On the other hand, the DMAC 503 transfers image data from the external I / F controller 508 via the DMA bus 507 without intervention of the CPU 501 and stores it in the memory 504.

On the other hand, in the prior art, in order to perform arbitration according to the use environment for a plurality of DMA buses, each of a plurality of DMA request sources in an information processing device is uniquely associated with a priority. Is set in a rewritable register, and when at least one DMA request signal is received from a plurality of DMA request sources, the received identification number is a unique identification number associated with the priority order. A DMA request that selects the DMA request signal with the highest priority among the rearranged DMA request signals and issues the selected DMA request signal via the DMA controller based on the selected DMA request signal Arbitration is performed so that DMA processing between the source and the memory is performed.
JP 2005-71186 A

Further, Patent Document 2 includes a bus, a memory, a processor, a bus arbitration circuit, and a DMAC, and the bus arbitration circuit includes an interrupt function for preventing monopolization of one of the buses and a determination unit for determining whether or not the bus can be interrupted. By selectively occupying the processor or DMAC or the like, the processor occupies the bus and accesses the memory, or the DMAC occupies the bus and executes DMA transfer between the memory and the outside without going through the processor. A data processing device is described that does the following.
JP-A-8-171528

  In the data transfer apparatus described above, both the signal lines for the data transfer bus and the bus for the CPU (processor) to access the memory are required for the main control device on the system board in the image forming apparatus. However, an increase in the number of signal lines not only causes an increase in the number of pins of each device, but there is a problem that in some cases, the number of cores of the connector and the area of the PWB may be increased.

  The present invention has been made in view of the above problems, and an object thereof is to provide a data transfer apparatus having a reduced number of signal lines.

  In order to solve the above problems, a data transfer device according to the present invention shares a bus for transferring data from an external I / F and a bus to which a memory used by the CPU of the device is connected. It was.

  Here, it is preferable to provide a bus arbitration circuit that arbitrates between DMA access for executing data transfer and CPU access. In this case, it is preferable that the arbitration ratio of the bus arbitration circuit can be set. Furthermore, it is preferable to include control means for setting the rate of arbitration by the bus arbitration circuit based on the type of external I / F to be connected. In this case, it is preferable that either the external I / F type is Ethernet (registered trademark) or the external I / F type is USB.

  According to the data transfer device of the present invention, since the bus for transferring data from the external I / F and the bus to which the memory used by the CPU of the device is connected are shared, the signal line The number decreases.

Embodiments of the present invention will be described below with reference to the accompanying drawings. First, a first embodiment of a data transfer apparatus according to the present invention will be described with reference to FIG.
This data transfer apparatus includes a main ASIC 1 that controls the apparatus, and the ASIC 1 includes a CPU (processor) 2 and a DMA controller (DMAC) 3. A memory 4 for storing image data is connected to the DMAC 3.

  The CPU 2 is connected to the local bus controller 5 via the CPU bus 12 and the DMAC 3 is connected to the local bus controller 5 via the DMA bus 13. The local bus controller 5 is connected to an external local bus 11, and an external I / F controller 8, a code ROM 9, and a font ROM 10 are connected to the local bus 11.

  In this data transfer apparatus, a program is executed by the CPU 2 in the ASIC 1. This program is read from the code ROM 9 via the local bus 11, the local bus controller 5, and the CPU bus 12 and executed. On the other hand, the DMAC 3 accesses the external I / F controller 8 via the DMA bus 13, the local bus controller 5, and the local bus 11 without intervention of the CPU 501, and image data is directly transferred from the external I / F controller 8 to the memory 4. Transfer and store.

  As described above, since the bus for transferring data from the external I / F and the bus to which the memory used by the CPU of the device is connected are shared as a local bus, it is dedicated for image data transfer. Therefore, the number of signal lines can be reduced and the cost can be reduced as compared with the case where a dedicated bus to which the memory used by the CPU and the memory used by the CPU are connected is provided. Furthermore, it is possible to achieve both cost reduction and high performance of the embedded system.

  In this case, since the local bus controller 5 cannot accept access requests from both the CPU 2 and the DMA controller 3 at the same time, it waits for the end of one access and accepts the other access.

Next, a second embodiment of the data transfer apparatus according to the present invention will be described with reference to FIG.
In this data transfer apparatus, in addition to the configuration of the first embodiment, a bus arbitration circuit 15 that arbitrates access between the CPU 2 and the DMA controller 3 is provided. The bus arbitration circuit 15 arbitrates the mutual access of the CPU 2 and the DMA controller 3 at a constant rate, thereby avoiding that one access monopolizes the bus 11.

  In this way, by providing a bus arbitration circuit that arbitrates between DMAC access for executing data transfer and CPU access, it is possible to avoid monopolizing one type of access to the bus, and to share more efficiently. The bus can be used.

  In this case, it is preferable that the arbitration ratio of the bus arbitration circuit 15 can be set. Thereby, it is possible to obtain an ASIC that can be applied to various systems.

  Further, the CPU 2 accesses the external I / F controller 8 to determine the characteristics of the external I / F connected at that time, and determines the type of the external I / F connected to the bus arbitration circuit 15. It is preferable that the optimal arbitration ratio is set, that is, the CPU 2 also serves as a control means for setting the arbitration ratio.

  Thereby, the use efficiency of the bus can be improved. For example, if the same arbitration ratio is used when the external I / F is operating in the high-speed mode and when operating in the low-speed mode, the transfer source specification will not be fully utilized. By optimizing, time for transfer at the transfer source is reduced, so that the transfer source system can be released quickly.

  Further, the external I / F is configured by Ethernet (registered trademark), and the CPU 2 can detect the communication speed of the Ethernet (registered trademark) and set the arbitration ratio optimum for the communication speed in the bus arbitration circuit 15. . Settings corresponding to the communication speed, such as 10BASE-T and 100BASE-TX, can be performed.

  Alternatively, the external I / F can be configured by USB, and the CPU 2 can set the arbitration ratio optimal for the communication speed in the bus arbitration circuit 15 based on the USB communication mode. For example, settings can be made according to the communication speeds of Low-Speed MODE, Full-Speed MODE, and Hi-Speed MODE.

Next, an example of a mechanism unit of an image forming apparatus including the data transfer apparatus according to the present invention will be described with reference to FIGS. FIG. 3 is an explanatory side view for explaining the overall structure of the mechanism part, and FIG. 4 is an explanatory plan view of the mechanism part.
In this image forming apparatus, a carriage 103 is slidably held in a main scanning direction by a guide rod 101 and a guide rail 102 which are horizontally mounted on left and right side plates (not shown), and a driving pulley 106A is driven by a main scanning motor 104. 4 is moved and scanned in the direction indicated by the arrow (main scanning direction) in FIG.

  The carriage 103 includes, for example, four recording heads 107y, 107c, and 107m including droplet discharge heads that discharge yellow (Y), cyan (C), magenta (M), and black (K) ink droplets, respectively. , 107k (referred to as “recording head 107” when colors are not distinguished) are arranged in such a manner that a plurality of ink ejection openings intersect with the main scanning direction and the ink droplet ejection direction faces downward.

  As the liquid discharge head constituting the recording head 107, a piezoelectric actuator such as a piezoelectric element, a thermal actuator that uses film boiling of recording liquid using an electrothermal transducer such as a heating resistor, and a metal phase change due to temperature change are used. A shape memory alloy actuator, an electrostatic actuator using an electrostatic force, or the like provided as energy generating means (pressure generating means) for discharging ink (liquid) can be used.

  The carriage 103 is equipped with a sub tank 108 for each color for supplying each color ink to the recording head 107. Ink is supplied to the sub tank 108 from a main tank (ink cartridge) (not shown) via an ink supply tube 109.

  On the other hand, as a paper feeding unit for feeding paper 112 stacked on a paper stacking unit (pressure plate) 111 such as a paper feeding cassette 110, a half-moon roller (separately feeding paper 112 one by one from the paper stacking unit 111) A separation pad 114 made of a material having a large friction coefficient is provided opposite to the sheet feeding roller 113 and the sheet feeding roller 113, and the separation pad 114 is urged toward the sheet feeding roller 113 side.

  In order to convey the paper 112 fed from the paper feeding unit below the recording head 7, a conveyance belt 121 for electrostatically attracting and conveying the paper 112 and a guide 115 from the paper feeding unit. Counter roller 122 for transporting the paper 112 fed between the conveyor belt 121 and the paper 112 fed substantially vertically upward to change the direction of the paper 112 approximately 90 ° to follow the transport belt 121. A conveyance guide 123 and a pressing roller 125 urged toward the conveyance belt 121 by a pressing member 124 are provided. In addition, a charging roller 126 that is a charging unit for charging the surface of the conveyance belt 121 is provided.

  Here, the conveyance belt 121 is an endless belt, is stretched between the conveyance roller 127 and the tension roller 128, and the conveyance roller 127 is rotated from the sub-scanning motor 131 via the timing belt 132 and the timing roller 133. By doing so, it is configured to circulate in the belt conveyance direction (sub-scanning direction) in FIG. A guide member 129 is disposed on the back side of the conveyance belt 121 in correspondence with the image forming area formed by the recording head 107. In addition, the charging roller 126 is disposed so as to come into contact with the surface layer of the transport belt 121 and to rotate following the rotation of the transport belt 121.

  As shown in FIG. 4, a slit disk 134 is attached to the shaft of the transport roller 127, and a sensor 135 for detecting the slit of the slit disk 134 is provided. A rotary encoder 136 is configured.

  Further, as a paper discharge unit for discharging the paper 112 recorded by the recording head 107, a separation claw 151 for separating the paper 112 from the conveyance belt 121, a paper discharge roller 152 and a paper discharge roller 153, and a discharge A paper discharge tray 154 for stocking paper 112 to be printed is provided.

  Further, as shown in FIG. 4, a maintenance / recovery mechanism 156 for maintaining and recovering the state of the nozzles of the recording head 107 is disposed in a non-printing area on one side of the carriage 103 in the scanning direction.

  The maintenance / recovery machine 156 includes a cap 157 for capping each nozzle surface of the recording head 107, a wiper blade 158 which is a blade member for wiping the nozzle surface, and a discharge unit for discharging the thickened recording liquid. An empty discharge receiver 159 for receiving droplets when performing empty discharge for discharging droplets that do not contribute to recording is provided.

  A double-sided paper feeding unit 161 is detachably attached to the back. The double-sided paper feeding unit 161 takes in the paper 112 returned by the reverse rotation of the transport belt 121, reverses it, and feeds it again between the counter roller 122 and the transport belt 121.

  In the image forming apparatus configured as described above, the sheets 112 are separated and fed one by one from the sheet feeding unit, and the sheet 112 fed substantially vertically upward is guided by the guide 115, and includes the conveyance belt 121 and the counter roller 122. The leading end is guided by the transport guide 123 and pressed against the transport belt 21 by the pressing roller 125, and the transport direction is changed by approximately 90 °.

  At this time, a charging voltage pattern in which a positive output and a negative output are alternately repeated from the AC bias supply unit to the charging roller 126 by a control unit (not shown), that is, an alternating voltage is applied, and the conveying belt 121 is alternating. That is, plus and minus are alternately charged in a band shape with a predetermined width in the sub-scanning direction which is the circumferential direction. When the paper 112 is fed onto the conveyance belt 121 charged alternately with plus and minus, the paper 112 is attracted to the conveyance belt 121 by electrostatic force, and the paper 112 is conveyed in the sub-scanning direction by the circular movement of the conveyance belt 121. Is done.

  Therefore, by driving the recording head 107 according to the image signal while moving the carriage 103 in the forward and backward directions, ink droplets are ejected onto the stopped paper 112 to record one line, and the paper 112 is After transporting a predetermined amount, the next line is recorded. Upon receiving a recording end signal or a signal that the trailing edge of the paper 112 has reached the recording area, the recording operation is finished, and the paper 112 is discharged onto the paper discharge tray 154.

  In the case of double-sided printing, when recording on the front surface (surface to be printed first) is completed, the recording belt 12 is fed into the double-sided paper feeding unit 161 by rotating the conveyor belt 121 in the reverse direction. The paper 112 is reversed (with the back surface being the printing surface), and is fed again between the counter roller 122 and the conveyor belt 121. The timing is controlled, and the sheet is conveyed onto the conveyor bell 121 as described above. After recording on the back side, the sheet is discharged to the discharge tray 154.

  Further, during printing (recording) standby, the carriage 103 is moved to the maintenance / recovery mechanism 155 side, and the nozzle surface of the recording head 107 is capped by the cap 157 so that the nozzles are kept in a wet state. To prevent. In addition, the recording liquid is sucked from the nozzle in a state where the recording head 107 is capped by the cap 157 (referred to as “nozzle suction” or “head suction”), and a recovery operation is performed to discharge the thickened recording liquid or bubbles. Wiping is performed by the wiper blade 158 in order to clean and remove ink adhering to the nozzle surface of the recording head 7 by this recovery operation. In addition, an idle ejection operation for ejecting ink not related to recording is performed before the start of recording or during recording. Thereby, the stable ejection performance of the recording head 107 is maintained.

Next, an outline of the control unit of the image forming apparatus will be described with reference to the block diagram of FIG.
In the control unit 200, the CPU 211 that controls the entire apparatus, the ROM 202 that stores programs executed by the CPU 211 and other fixed data, the RAM 203 that temporarily stores image data and the like, and the power supply of the apparatus are cut off. A rewritable non-volatile memory 204 for holding data, image processing for transferring image data, various signal processing, rearrangement, and other input / output signals for controlling the entire apparatus. ASIC 205 including the data transfer device according to FIG.

  The control unit 200 also includes a head drive control unit 207 including an I / F 206 for transmitting and receiving data and signals to and from the host side, a data transfer unit for driving and controlling the recording head 107, and a drive signal generation unit. A head driver (driver IC) 208 that is a head driving device for driving the recording head 107 provided on the carriage 103 side, a motor driving unit 210 for driving the main scanning motor 104 and the sub-scanning motor 131, and charging. An AC bias supply unit 212 that supplies an AC bias to the roller 126, an I / O 213 for inputting detection signals from various sensors, and the like are provided. The control unit 200 is connected to an operation panel 214 for inputting and displaying information necessary for the apparatus.

  Here, the control unit 200 transmits print data from the host side such as an information processing device such as a personal computer, an image reading device such as an image scanner, an imaging device such as a digital camera, etc. via an I / F 206 via a cable or a network. Receive.

  Then, the CPU 201 of the control unit 200 reads and analyzes the print data in the reception buffer included in the I / F 206, and the ASIC 205 directly transfers the image data from the host side through the external I / F and stores it in the RAM 203. Necessary image processing, data rearrangement processing, and the like are performed, and the image data is transferred from the head drive control unit 207 to the head driver 208. A program executed by the CPU in the ASIC 205 is stored in the ROM 202. In addition, generation of dot pattern data for outputting an image is performed by a printer driver on the host side.

  The head drive control unit 207 transfers the above-described image data as serial data, and outputs a transfer clock, a latch signal, a control signal, and the like necessary for transferring the image data and confirming the transfer to the head driver 208. Includes a D / A converter that performs D / A conversion on drive pulse pattern data stored in the ROM 202 and read by the CPU 201, and a drive signal generation unit including a voltage amplifier, a current amplifier, and the like. A drive signal composed of a plurality of drive pulses is output to the head driver 208.

  The head driver 208 selectively selects a drive pulse constituting a drive signal provided from the head drive control unit 207 based on image data corresponding to one row of the print head 107 input serially. The recording head 7 is driven by applying it to a driving element (for example, a piezoelectric element) that generates energy for discharging the ink. At this time, by selecting a driving pulse constituting the driving signal, for example, dots having different sizes such as a large droplet, a medium droplet, and a small droplet can be sorted.

  The motor drive unit 210 calculates a control value based on a target value given from the CPU 201 side and a speed detection value obtained by sampling a detection pulse from the encoder sensor 143 constituting the linear encoder, and passes through an internal motor driver. The main scanning motor 4 is driven. Further, the control value is calculated based on the target value given from the CPU 201 and the speed detection value obtained by sampling the detection pulse from the encoder sensor 135, and the sub-scanning motor 31 is driven via the internal motor driver.

  Thus, by providing the data transfer device according to the present invention, the number of signal lines can be reduced and the cost can be reduced, and the data transfer device includes a bus arbitration circuit so that efficient data transfer can be performed. it can.

1 is a block explanatory diagram showing a first embodiment of a data transfer apparatus according to the present invention. It is block explanatory drawing which shows 2nd Embodiment of the data transfer apparatus which concerns on this invention. 1 is a side explanatory view for explaining an overall configuration of a mechanism unit of an image forming apparatus including a data transfer apparatus according to the present invention. It is a plane explanatory view of the mechanism part. FIG. 2 is a block explanatory diagram illustrating an overview of a control unit in the image forming apparatus. It is block explanatory drawing which shows an example of the conventional data transfer apparatus.

Explanation of symbols

1 ... ASIC
2 ... CPU (processor)
3 ... DMA controller 4 ... Memory 5 ... Local bus controller 8 ... External I / F controller 9 ... Code ROM
DESCRIPTION OF SYMBOLS 11 ... Local bus 12 ... CPU bus 13 ... DMA bus 103 ... Carriage 107 ... Recording head 205 ... ASIC

Claims (6)

  In a data transfer device for transferring data from an external I / F, a bus for transferring data from the external I / F and a bus to which a memory used by the CPU of the device is connected are shared. A data transfer device.   2. The data transfer apparatus according to claim 1, further comprising a bus arbitration circuit that arbitrates between DMA access for executing data transfer and CPU access.   3. The data transfer apparatus according to claim 2, wherein an arbitration ratio of the bus arbitration circuit can be set.   4. The data transfer device according to claim 3, further comprising control means for setting a rate of arbitration by the bus arbitration circuit based on a type of the external I / F to be connected.   5. The data transfer apparatus according to claim 4, wherein the type of the external I / F is Ethernet (registered trademark). 5. The data transfer device according to claim 4, wherein the type of the external I / F is USB.

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